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RCM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xA byte (0x0)
mem_usage : registers
protection : not protected

Registers

SRS0

SRS1

RPFC

RPFW

MR

SSRS0

SSRS1


SRS0

System Reset Status Register 0
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRS0 SRS0 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WAKEUP LVD LOC LOL WDOG PIN POR

WAKEUP : Low Leakage Wakeup Reset
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Reset not caused by LLWU module wakeup source

#1 : 1

Reset caused by LLWU module wakeup source

End of enumeration elements list.

LVD : Low-Voltage Detect Reset
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Reset not caused by LVD trip or POR

#1 : 1

Reset caused by LVD trip or POR

End of enumeration elements list.

LOC : Loss-of-Clock Reset
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Reset not caused by a loss of external clock.

#1 : 1

Reset caused by a loss of external clock.

End of enumeration elements list.

LOL : Loss-of-Lock Reset
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

#0 : 0

Reset not caused by a loss of lock in the PLL

#1 : 1

Reset caused by a loss of lock in the PLL

End of enumeration elements list.

WDOG : Watchdog
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

Reset not caused by watchdog timeout

#1 : 1

Reset caused by watchdog timeout

End of enumeration elements list.

PIN : External Reset Pin
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Reset not caused by external reset pin

#1 : 1

Reset caused by external reset pin

End of enumeration elements list.

POR : Power-On Reset
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

Reset not caused by POR

#1 : 1

Reset caused by POR

End of enumeration elements list.


SRS1

System Reset Status Register 1
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRS1 SRS1 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 JTAG LOCKUP SW MDM_AP EZPT SACKERR

JTAG : JTAG Generated Reset
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Reset not caused by JTAG

#1 : 1

Reset caused by JTAG

End of enumeration elements list.

LOCKUP : Core Lockup
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Reset not caused by core LOCKUP event

#1 : 1

Reset caused by core LOCKUP event

End of enumeration elements list.

SW : Software
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Reset not caused by software setting of SYSRESETREQ bit

#1 : 1

Reset caused by software setting of SYSRESETREQ bit

End of enumeration elements list.

MDM_AP : MDM-AP System Reset Request
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

#0 : 0

Reset not caused by host debugger system setting of the System Reset Request bit

#1 : 1

Reset caused by host debugger system setting of the System Reset Request bit

End of enumeration elements list.

EZPT : EzPort Reset
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Reset not caused by EzPort receiving the RESET command while the device is in EzPort mode

#1 : 1

Reset caused by EzPort receiving the RESET command while the device is in EzPort mode

End of enumeration elements list.

SACKERR : Stop Mode Acknowledge Error Reset
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

Reset not caused by peripheral failure to acknowledge attempt to enter stop mode

#1 : 1

Reset caused by peripheral failure to acknowledge attempt to enter stop mode

End of enumeration elements list.


RPFC

Reset Pin Filter Control register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RPFC RPFC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RSTFLTSRW RSTFLTSS

RSTFLTSRW : Reset Pin Filter Select in Run and Wait Modes
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

All filtering disabled

#01 : 01

Bus clock filter enabled for normal operation

#10 : 10

LPO clock filter enabled for normal operation

End of enumeration elements list.

RSTFLTSS : Reset Pin Filter Select in Stop Mode
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

All filtering disabled

#1 : 1

LPO clock filter enabled

End of enumeration elements list.


RPFW

Reset Pin Filter Width register
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RPFW RPFW read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RSTFLTSEL

RSTFLTSEL : Reset Pin Filter Bus Clock Select
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

#00000 : 00000

Bus clock filter count is 1

#00001 : 00001

Bus clock filter count is 2

#00010 : 00010

Bus clock filter count is 3

#00011 : 00011

Bus clock filter count is 4

#00100 : 00100

Bus clock filter count is 5

#00101 : 00101

Bus clock filter count is 6

#00110 : 00110

Bus clock filter count is 7

#00111 : 00111

Bus clock filter count is 8

#01000 : 01000

Bus clock filter count is 9

#01001 : 01001

Bus clock filter count is 10

#01010 : 01010

Bus clock filter count is 11

#01011 : 01011

Bus clock filter count is 12

#01100 : 01100

Bus clock filter count is 13

#01101 : 01101

Bus clock filter count is 14

#01110 : 01110

Bus clock filter count is 15

#01111 : 01111

Bus clock filter count is 16

#10000 : 10000

Bus clock filter count is 17

#10001 : 10001

Bus clock filter count is 18

#10010 : 10010

Bus clock filter count is 19

#10011 : 10011

Bus clock filter count is 20

#10100 : 10100

Bus clock filter count is 21

#10101 : 10101

Bus clock filter count is 22

#10110 : 10110

Bus clock filter count is 23

#10111 : 10111

Bus clock filter count is 24

#11000 : 11000

Bus clock filter count is 25

#11001 : 11001

Bus clock filter count is 26

#11010 : 11010

Bus clock filter count is 27

#11011 : 11011

Bus clock filter count is 28

#11100 : 11100

Bus clock filter count is 29

#11101 : 11101

Bus clock filter count is 30

#11110 : 11110

Bus clock filter count is 31

#11111 : 11111

Bus clock filter count is 32

End of enumeration elements list.


MR

Mode Register
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MR MR read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EZP_MS

EZP_MS : EZP_MS_B pin state
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Pin deasserted (logic 1)

#1 : 1

Pin asserted (logic 0)

End of enumeration elements list.


SSRS0

Sticky System Reset Status Register 0
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSRS0 SSRS0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SWAKEUP SLVD SLOC SLOL SWDOG SPIN SPOR

SWAKEUP : Sticky Low Leakage Wakeup Reset
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reset not caused by LLWU module wakeup source

#1 : 1

Reset caused by LLWU module wakeup source

End of enumeration elements list.

SLVD : Sticky Low-Voltage Detect Reset
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reset not caused by LVD trip or POR

#1 : 1

Reset caused by LVD trip or POR

End of enumeration elements list.

SLOC : Sticky Loss-of-Clock Reset
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reset not caused by a loss of external clock.

#1 : 1

Reset caused by a loss of external clock.

End of enumeration elements list.

SLOL : Sticky Loss-of-Lock Reset
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reset not caused by a loss of lock in the PLL

#1 : 1

Reset caused by a loss of lock in the PLL

End of enumeration elements list.

SWDOG : Sticky Watchdog
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reset not caused by watchdog timeout

#1 : 1

Reset caused by watchdog timeout

End of enumeration elements list.

SPIN : Sticky External Reset Pin
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reset not caused by external reset pin

#1 : 1

Reset caused by external reset pin

End of enumeration elements list.

SPOR : Sticky Power-On Reset
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reset not caused by POR

#1 : 1

Reset caused by POR

End of enumeration elements list.


SSRS1

Sticky System Reset Status Register 1
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSRS1 SSRS1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SJTAG SLOCKUP SSW SMDM_AP SEZPT SSACKERR

SJTAG : Sticky JTAG Generated Reset
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reset not caused by JTAG

#1 : 1

Reset caused by JTAG

End of enumeration elements list.

SLOCKUP : Sticky Core Lockup
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reset not caused by core LOCKUP event

#1 : 1

Reset caused by core LOCKUP event

End of enumeration elements list.

SSW : Sticky Software
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reset not caused by software setting of SYSRESETREQ bit

#1 : 1

Reset caused by software setting of SYSRESETREQ bit

End of enumeration elements list.

SMDM_AP : Sticky MDM-AP System Reset Request
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reset not caused by host debugger system setting of the System Reset Request bit

#1 : 1

Reset caused by host debugger system setting of the System Reset Request bit

End of enumeration elements list.

SEZPT : Sticky EzPort Reset
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reset not caused by EzPort receiving the RESET command while the device is in EzPort mode

#1 : 1

Reset caused by EzPort receiving the RESET command while the device is in EzPort mode

End of enumeration elements list.

SSACKERR : Sticky Stop Mode Acknowledge Error Reset
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reset not caused by peripheral failure to acknowledge attempt to enter stop mode

#1 : 1

Reset caused by peripheral failure to acknowledge attempt to enter stop mode

End of enumeration elements list.



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