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DMAMUX

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DMAMUX_C0CR (C0CR)

DMAMUX_C4CR (C4CR)

DMAMUX_RG0CR (RG0CR)

DMAMUX_RG1CR (RG1CR)

DMAMUX_RG2CR (RG2CR)

DMAMUX_RG3CR (RG3CR)

DMAMUX_C5CR (C5CR)

DMAMUX_RGSR (RGSR)

DMAMUX_RGCFR (RGCFR)

DMAMUX_C6CR (C6CR)

DMAMUX_HWCFGR2 (HWCFGR2)

DMAMUX_HWCFGR1 (HWCFGR1)

DMAMUX_VERR (VERR)

DMAMUX_IPIDR (IPIDR)

DMAMUX_SIDR (SIDR)

DMAMUX_C1CR (C1CR)

DMAMUX_C2CR (C2CR)

DMAMUX_CSR (CSR)

DMAMUX_CFR (CFR)

DMAMUX_C3CR (C3CR)


DMAMUX_C0CR (C0CR)

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX_C0CR DMAMUX_C0CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


DMAMUX_C4CR (C4CR)

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX_C4CR DMAMUX_C4CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


DMAMUX_RG0CR (RG0CR)

DMAMux - DMA request generator channel x control register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX_RG0CR DMAMUX_RG0CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : DMA request trigger input selected
bits : 0 - 4 (5 bit)

OIE : Interrupt enable at trigger event overrun
bits : 8 - 8 (1 bit)

GE : DMA request generator channel enable/disable
bits : 16 - 16 (1 bit)

GPOL : DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
bits : 17 - 18 (2 bit)

GNBREQ : Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
bits : 19 - 23 (5 bit)


DMAMUX_RG1CR (RG1CR)

DMAMux - DMA request generator channel x control register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX_RG1CR DMAMUX_RG1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : DMA request trigger input selected
bits : 0 - 4 (5 bit)

OIE : Interrupt enable at trigger event overrun
bits : 8 - 8 (1 bit)

GE : DMA request generator channel enable/disable
bits : 16 - 16 (1 bit)

GPOL : DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
bits : 17 - 18 (2 bit)

GNBREQ : Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
bits : 19 - 23 (5 bit)


DMAMUX_RG2CR (RG2CR)

DMAMux - DMA request generator channel x control register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX_RG2CR DMAMUX_RG2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : DMA request trigger input selected
bits : 0 - 4 (5 bit)

OIE : Interrupt enable at trigger event overrun
bits : 8 - 8 (1 bit)

GE : DMA request generator channel enable/disable
bits : 16 - 16 (1 bit)

GPOL : DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
bits : 17 - 18 (2 bit)

GNBREQ : Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
bits : 19 - 23 (5 bit)


DMAMUX_RG3CR (RG3CR)

DMAMux - DMA request generator channel x control register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX_RG3CR DMAMUX_RG3CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : DMA request trigger input selected
bits : 0 - 4 (5 bit)

OIE : Interrupt enable at trigger event overrun
bits : 8 - 8 (1 bit)

GE : DMA request generator channel enable/disable
bits : 16 - 16 (1 bit)

GPOL : DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
bits : 17 - 18 (2 bit)

GNBREQ : Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
bits : 19 - 23 (5 bit)


DMAMUX_C5CR (C5CR)

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX_C5CR DMAMUX_C5CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


DMAMUX_RGSR (RGSR)

DMAMux - DMA request generator status register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMAMUX_RGSR DMAMUX_RGSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OF

OF : Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register.
bits : 0 - 3 (4 bit)


DMAMUX_RGCFR (RGCFR)

DMAMux - DMA request generator clear flag register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DMAMUX_RGCFR DMAMUX_RGCFR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COF

COF : Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register.
bits : 0 - 3 (4 bit)


DMAMUX_C6CR (C6CR)

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX_C6CR DMAMUX_C6CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


DMAMUX_HWCFGR2 (HWCFGR2)

DMAMUX hardware configuration 2 register
address_offset : 0x3EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMAMUX_HWCFGR2 DMAMUX_HWCFGR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NUM_DMA_EXT_REQ

NUM_DMA_EXT_REQ : Number of DMA request trigger inputs
bits : 0 - 7 (8 bit)


DMAMUX_HWCFGR1 (HWCFGR1)

DMAMUX hardware configuration 1 register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMAMUX_HWCFGR1 DMAMUX_HWCFGR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NUM_DMA_STREAMS NUM_DMA_PERIPH_REQ NUM_DMA_TRIG NUM_DMA_REQGEN

NUM_DMA_STREAMS : number of DMA request line multiplexer (output) channels
bits : 0 - 7 (8 bit)

NUM_DMA_PERIPH_REQ : number of DMA request lines from peripherals
bits : 8 - 15 (8 bit)

NUM_DMA_TRIG : number of synchronization inputs
bits : 16 - 23 (8 bit)

NUM_DMA_REQGEN : number of DMA request generator channels
bits : 24 - 31 (8 bit)


DMAMUX_VERR (VERR)

DMAMUX version register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMAMUX_VERR DMAMUX_VERR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MINREV MAJREV

MINREV : Minor IP revision
bits : 0 - 3 (4 bit)

MAJREV : Major IP revision
bits : 4 - 7 (4 bit)


DMAMUX_IPIDR (IPIDR)

DMAMUX IP identification register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMAMUX_IPIDR DMAMUX_IPIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID

ID : IP identification
bits : 0 - 31 (32 bit)


DMAMUX_SIDR (SIDR)

DMAMUX size identification register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMAMUX_SIDR DMAMUX_SIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SID

SID : Size identification
bits : 0 - 31 (32 bit)


DMAMUX_C1CR (C1CR)

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX_C1CR DMAMUX_C1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


DMAMUX_C2CR (C2CR)

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX_C2CR DMAMUX_C2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)


DMAMUX_CSR (CSR)

DMAMUX request line multiplexer interrupt channel status register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMAMUX_CSR DMAMUX_CSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOF

SOF : Synchronization overrun event flag
bits : 0 - 6 (7 bit)


DMAMUX_CFR (CFR)

DMAMUX request line multiplexer interrupt clear flag register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DMAMUX_CFR DMAMUX_CFR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSOF

CSOF : Clear synchronization overrun event flag
bits : 0 - 6 (7 bit)


DMAMUX_C3CR (C3CR)

DMAMux - DMA request line multiplexer channel x control register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX_C3CR DMAMUX_C3CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : Input DMA request line selected
bits : 0 - 7 (8 bit)

SOIE : Interrupt enable at synchronization event overrun
bits : 8 - 8 (1 bit)

EGE : Event generation enable/disable
bits : 9 - 9 (1 bit)

SE : Synchronous operating mode enable/disable
bits : 16 - 16 (1 bit)

SPOL : Synchronization event type selector Defines the synchronization event on the selected synchronization input:
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization input selected
bits : 24 - 28 (5 bit)



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