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DMAMUX

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CHCFG0

CHCFG1

CHCFG6

CHCFG7

CHCFG8

CHCFG9

CHCFG2

CHCFG10

CHCFG11

CHCFG12

CHCFG13

CHCFG3

CHCFG14

CHCFG15

CHCFG4

CHCFG5


CHCFG0

Channel Configuration register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG0 CHCFG0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOURCE TRIG ENBL

SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

#0 : 0

Disable_Signal

#10 : 2

UART0Rx_Signal

#11 : 3

UART0Tx_Signal

#100 : 4

UART1Rx_Signal

#101 : 5

UART1Tx_Signal

#110 : 6

PWMA0WR_Signal

#111 : 7

PWMA1WR_Signal

#1000 : 8

PWMA2WR_Signal

#1001 : 9

PWMA3WR_Signal

#1010 : 10

PWMA0CP_Signal

#1011 : 11

PWMA1CP_Signal

#1100 : 12

PWMA2CP_Signal

#1101 : 13

PWMA3CP_Signal

#1110 : 14

CAN0Rx_Signal

#1111 : 15

CAN1Rx_Signal

#10000 : 16

SPI0Rx_Signal

#10001 : 17

SPI0Tx_Signal

#10010 : 18

XBARAOut0_Signal

#10011 : 19

XBARAOut1_Signal

#10100 : 20

XBARAOut2_Signal

#10101 : 21

XBARAOut3_Signal

#10110 : 22

I2C0_Signal

#100010 : 34

CMP3_Signal

#101000 : 40

ADCA_Signal

#101001 : 41

ADCB_Signal

#101010 : 42

CMP0_Signal

#101011 : 43

CMP1_Signal

#101100 : 44

CMP2_Signal

#101101 : 45

DAC0_Signal

#101111 : 47

PDB0_Signal

#110000 : 48

PDB1_Signal

#110001 : 49

PortA_Signal

#110010 : 50

PortB_Signal

#110011 : 51

PortC_Signal

#110100 : 52

PortD_Signal

#110101 : 53

PortE_Signal

#111010 : 58

AlwaysOn58_Signal

#111011 : 59

AlwaysOn59_Signal

#111100 : 60

AlwaysOn60_Signal

#111101 : 61

AlwaysOn61_Signal

#111110 : 62

AlwaysOn62_Signal

#111111 : 63

AlwaysOn63_Signal

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

#1 : 1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.

#1 : 1

DMA channel is enabled

End of enumeration elements list.


CHCFG1

Channel Configuration register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG1 CHCFG1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOURCE TRIG ENBL

SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

#0 : 0

Disable_Signal

#10 : 2

UART0Rx_Signal

#11 : 3

UART0Tx_Signal

#100 : 4

UART1Rx_Signal

#101 : 5

UART1Tx_Signal

#110 : 6

PWMA0WR_Signal

#111 : 7

PWMA1WR_Signal

#1000 : 8

PWMA2WR_Signal

#1001 : 9

PWMA3WR_Signal

#1010 : 10

PWMA0CP_Signal

#1011 : 11

PWMA1CP_Signal

#1100 : 12

PWMA2CP_Signal

#1101 : 13

PWMA3CP_Signal

#1110 : 14

CAN0Rx_Signal

#1111 : 15

CAN1Rx_Signal

#10000 : 16

SPI0Rx_Signal

#10001 : 17

SPI0Tx_Signal

#10010 : 18

XBARAOut0_Signal

#10011 : 19

XBARAOut1_Signal

#10100 : 20

XBARAOut2_Signal

#10101 : 21

XBARAOut3_Signal

#10110 : 22

I2C0_Signal

#100010 : 34

CMP3_Signal

#101000 : 40

ADCA_Signal

#101001 : 41

ADCB_Signal

#101010 : 42

CMP0_Signal

#101011 : 43

CMP1_Signal

#101100 : 44

CMP2_Signal

#101101 : 45

DAC0_Signal

#101111 : 47

PDB0_Signal

#110000 : 48

PDB1_Signal

#110001 : 49

PortA_Signal

#110010 : 50

PortB_Signal

#110011 : 51

PortC_Signal

#110100 : 52

PortD_Signal

#110101 : 53

PortE_Signal

#111010 : 58

AlwaysOn58_Signal

#111011 : 59

AlwaysOn59_Signal

#111100 : 60

AlwaysOn60_Signal

#111101 : 61

AlwaysOn61_Signal

#111110 : 62

AlwaysOn62_Signal

#111111 : 63

AlwaysOn63_Signal

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

#1 : 1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.

#1 : 1

DMA channel is enabled

End of enumeration elements list.


CHCFG6

Channel Configuration register
address_offset : 0x15 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG6 CHCFG6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOURCE TRIG ENBL

SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

#0 : 0

Disable_Signal

#10 : 2

UART0Rx_Signal

#11 : 3

UART0Tx_Signal

#100 : 4

UART1Rx_Signal

#101 : 5

UART1Tx_Signal

#110 : 6

PWMA0WR_Signal

#111 : 7

PWMA1WR_Signal

#1000 : 8

PWMA2WR_Signal

#1001 : 9

PWMA3WR_Signal

#1010 : 10

PWMA0CP_Signal

#1011 : 11

PWMA1CP_Signal

#1100 : 12

PWMA2CP_Signal

#1101 : 13

PWMA3CP_Signal

#1110 : 14

CAN0Rx_Signal

#1111 : 15

CAN1Rx_Signal

#10000 : 16

SPI0Rx_Signal

#10001 : 17

SPI0Tx_Signal

#10010 : 18

XBARAOut0_Signal

#10011 : 19

XBARAOut1_Signal

#10100 : 20

XBARAOut2_Signal

#10101 : 21

XBARAOut3_Signal

#10110 : 22

I2C0_Signal

#100010 : 34

CMP3_Signal

#101000 : 40

ADCA_Signal

#101001 : 41

ADCB_Signal

#101010 : 42

CMP0_Signal

#101011 : 43

CMP1_Signal

#101100 : 44

CMP2_Signal

#101101 : 45

DAC0_Signal

#101111 : 47

PDB0_Signal

#110000 : 48

PDB1_Signal

#110001 : 49

PortA_Signal

#110010 : 50

PortB_Signal

#110011 : 51

PortC_Signal

#110100 : 52

PortD_Signal

#110101 : 53

PortE_Signal

#111010 : 58

AlwaysOn58_Signal

#111011 : 59

AlwaysOn59_Signal

#111100 : 60

AlwaysOn60_Signal

#111101 : 61

AlwaysOn61_Signal

#111110 : 62

AlwaysOn62_Signal

#111111 : 63

AlwaysOn63_Signal

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

#1 : 1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.

#1 : 1

DMA channel is enabled

End of enumeration elements list.


CHCFG7

Channel Configuration register
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG7 CHCFG7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOURCE TRIG ENBL

SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

#0 : 0

Disable_Signal

#10 : 2

UART0Rx_Signal

#11 : 3

UART0Tx_Signal

#100 : 4

UART1Rx_Signal

#101 : 5

UART1Tx_Signal

#110 : 6

PWMA0WR_Signal

#111 : 7

PWMA1WR_Signal

#1000 : 8

PWMA2WR_Signal

#1001 : 9

PWMA3WR_Signal

#1010 : 10

PWMA0CP_Signal

#1011 : 11

PWMA1CP_Signal

#1100 : 12

PWMA2CP_Signal

#1101 : 13

PWMA3CP_Signal

#1110 : 14

CAN0Rx_Signal

#1111 : 15

CAN1Rx_Signal

#10000 : 16

SPI0Rx_Signal

#10001 : 17

SPI0Tx_Signal

#10010 : 18

XBARAOut0_Signal

#10011 : 19

XBARAOut1_Signal

#10100 : 20

XBARAOut2_Signal

#10101 : 21

XBARAOut3_Signal

#10110 : 22

I2C0_Signal

#100010 : 34

CMP3_Signal

#101000 : 40

ADCA_Signal

#101001 : 41

ADCB_Signal

#101010 : 42

CMP0_Signal

#101011 : 43

CMP1_Signal

#101100 : 44

CMP2_Signal

#101101 : 45

DAC0_Signal

#101111 : 47

PDB0_Signal

#110000 : 48

PDB1_Signal

#110001 : 49

PortA_Signal

#110010 : 50

PortB_Signal

#110011 : 51

PortC_Signal

#110100 : 52

PortD_Signal

#110101 : 53

PortE_Signal

#111010 : 58

AlwaysOn58_Signal

#111011 : 59

AlwaysOn59_Signal

#111100 : 60

AlwaysOn60_Signal

#111101 : 61

AlwaysOn61_Signal

#111110 : 62

AlwaysOn62_Signal

#111111 : 63

AlwaysOn63_Signal

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

#1 : 1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.

#1 : 1

DMA channel is enabled

End of enumeration elements list.


CHCFG8

Channel Configuration register
address_offset : 0x24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG8 CHCFG8 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOURCE TRIG ENBL

SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

#0 : 0

Disable_Signal

#10 : 2

UART0Rx_Signal

#11 : 3

UART0Tx_Signal

#100 : 4

UART1Rx_Signal

#101 : 5

UART1Tx_Signal

#110 : 6

PWMA0WR_Signal

#111 : 7

PWMA1WR_Signal

#1000 : 8

PWMA2WR_Signal

#1001 : 9

PWMA3WR_Signal

#1010 : 10

PWMA0CP_Signal

#1011 : 11

PWMA1CP_Signal

#1100 : 12

PWMA2CP_Signal

#1101 : 13

PWMA3CP_Signal

#1110 : 14

CAN0Rx_Signal

#1111 : 15

CAN1Rx_Signal

#10000 : 16

SPI0Rx_Signal

#10001 : 17

SPI0Tx_Signal

#10010 : 18

XBARAOut0_Signal

#10011 : 19

XBARAOut1_Signal

#10100 : 20

XBARAOut2_Signal

#10101 : 21

XBARAOut3_Signal

#10110 : 22

I2C0_Signal

#100010 : 34

CMP3_Signal

#101000 : 40

ADCA_Signal

#101001 : 41

ADCB_Signal

#101010 : 42

CMP0_Signal

#101011 : 43

CMP1_Signal

#101100 : 44

CMP2_Signal

#101101 : 45

DAC0_Signal

#101111 : 47

PDB0_Signal

#110000 : 48

PDB1_Signal

#110001 : 49

PortA_Signal

#110010 : 50

PortB_Signal

#110011 : 51

PortC_Signal

#110100 : 52

PortD_Signal

#110101 : 53

PortE_Signal

#111010 : 58

AlwaysOn58_Signal

#111011 : 59

AlwaysOn59_Signal

#111100 : 60

AlwaysOn60_Signal

#111101 : 61

AlwaysOn61_Signal

#111110 : 62

AlwaysOn62_Signal

#111111 : 63

AlwaysOn63_Signal

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

#1 : 1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.

#1 : 1

DMA channel is enabled

End of enumeration elements list.


CHCFG9

Channel Configuration register
address_offset : 0x2D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG9 CHCFG9 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOURCE TRIG ENBL

SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

#0 : 0

Disable_Signal

#10 : 2

UART0Rx_Signal

#11 : 3

UART0Tx_Signal

#100 : 4

UART1Rx_Signal

#101 : 5

UART1Tx_Signal

#110 : 6

PWMA0WR_Signal

#111 : 7

PWMA1WR_Signal

#1000 : 8

PWMA2WR_Signal

#1001 : 9

PWMA3WR_Signal

#1010 : 10

PWMA0CP_Signal

#1011 : 11

PWMA1CP_Signal

#1100 : 12

PWMA2CP_Signal

#1101 : 13

PWMA3CP_Signal

#1110 : 14

CAN0Rx_Signal

#1111 : 15

CAN1Rx_Signal

#10000 : 16

SPI0Rx_Signal

#10001 : 17

SPI0Tx_Signal

#10010 : 18

XBARAOut0_Signal

#10011 : 19

XBARAOut1_Signal

#10100 : 20

XBARAOut2_Signal

#10101 : 21

XBARAOut3_Signal

#10110 : 22

I2C0_Signal

#100010 : 34

CMP3_Signal

#101000 : 40

ADCA_Signal

#101001 : 41

ADCB_Signal

#101010 : 42

CMP0_Signal

#101011 : 43

CMP1_Signal

#101100 : 44

CMP2_Signal

#101101 : 45

DAC0_Signal

#101111 : 47

PDB0_Signal

#110000 : 48

PDB1_Signal

#110001 : 49

PortA_Signal

#110010 : 50

PortB_Signal

#110011 : 51

PortC_Signal

#110100 : 52

PortD_Signal

#110101 : 53

PortE_Signal

#111010 : 58

AlwaysOn58_Signal

#111011 : 59

AlwaysOn59_Signal

#111100 : 60

AlwaysOn60_Signal

#111101 : 61

AlwaysOn61_Signal

#111110 : 62

AlwaysOn62_Signal

#111111 : 63

AlwaysOn63_Signal

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

#1 : 1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.

#1 : 1

DMA channel is enabled

End of enumeration elements list.


CHCFG2

Channel Configuration register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG2 CHCFG2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOURCE TRIG ENBL

SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

#0 : 0

Disable_Signal

#10 : 2

UART0Rx_Signal

#11 : 3

UART0Tx_Signal

#100 : 4

UART1Rx_Signal

#101 : 5

UART1Tx_Signal

#110 : 6

PWMA0WR_Signal

#111 : 7

PWMA1WR_Signal

#1000 : 8

PWMA2WR_Signal

#1001 : 9

PWMA3WR_Signal

#1010 : 10

PWMA0CP_Signal

#1011 : 11

PWMA1CP_Signal

#1100 : 12

PWMA2CP_Signal

#1101 : 13

PWMA3CP_Signal

#1110 : 14

CAN0Rx_Signal

#1111 : 15

CAN1Rx_Signal

#10000 : 16

SPI0Rx_Signal

#10001 : 17

SPI0Tx_Signal

#10010 : 18

XBARAOut0_Signal

#10011 : 19

XBARAOut1_Signal

#10100 : 20

XBARAOut2_Signal

#10101 : 21

XBARAOut3_Signal

#10110 : 22

I2C0_Signal

#100010 : 34

CMP3_Signal

#101000 : 40

ADCA_Signal

#101001 : 41

ADCB_Signal

#101010 : 42

CMP0_Signal

#101011 : 43

CMP1_Signal

#101100 : 44

CMP2_Signal

#101101 : 45

DAC0_Signal

#101111 : 47

PDB0_Signal

#110000 : 48

PDB1_Signal

#110001 : 49

PortA_Signal

#110010 : 50

PortB_Signal

#110011 : 51

PortC_Signal

#110100 : 52

PortD_Signal

#110101 : 53

PortE_Signal

#111010 : 58

AlwaysOn58_Signal

#111011 : 59

AlwaysOn59_Signal

#111100 : 60

AlwaysOn60_Signal

#111101 : 61

AlwaysOn61_Signal

#111110 : 62

AlwaysOn62_Signal

#111111 : 63

AlwaysOn63_Signal

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

#1 : 1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.

#1 : 1

DMA channel is enabled

End of enumeration elements list.


CHCFG10

Channel Configuration register
address_offset : 0x37 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG10 CHCFG10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOURCE TRIG ENBL

SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

#0 : 0

Disable_Signal

#10 : 2

UART0Rx_Signal

#11 : 3

UART0Tx_Signal

#100 : 4

UART1Rx_Signal

#101 : 5

UART1Tx_Signal

#110 : 6

PWMA0WR_Signal

#111 : 7

PWMA1WR_Signal

#1000 : 8

PWMA2WR_Signal

#1001 : 9

PWMA3WR_Signal

#1010 : 10

PWMA0CP_Signal

#1011 : 11

PWMA1CP_Signal

#1100 : 12

PWMA2CP_Signal

#1101 : 13

PWMA3CP_Signal

#1110 : 14

CAN0Rx_Signal

#1111 : 15

CAN1Rx_Signal

#10000 : 16

SPI0Rx_Signal

#10001 : 17

SPI0Tx_Signal

#10010 : 18

XBARAOut0_Signal

#10011 : 19

XBARAOut1_Signal

#10100 : 20

XBARAOut2_Signal

#10101 : 21

XBARAOut3_Signal

#10110 : 22

I2C0_Signal

#100010 : 34

CMP3_Signal

#101000 : 40

ADCA_Signal

#101001 : 41

ADCB_Signal

#101010 : 42

CMP0_Signal

#101011 : 43

CMP1_Signal

#101100 : 44

CMP2_Signal

#101101 : 45

DAC0_Signal

#101111 : 47

PDB0_Signal

#110000 : 48

PDB1_Signal

#110001 : 49

PortA_Signal

#110010 : 50

PortB_Signal

#110011 : 51

PortC_Signal

#110100 : 52

PortD_Signal

#110101 : 53

PortE_Signal

#111010 : 58

AlwaysOn58_Signal

#111011 : 59

AlwaysOn59_Signal

#111100 : 60

AlwaysOn60_Signal

#111101 : 61

AlwaysOn61_Signal

#111110 : 62

AlwaysOn62_Signal

#111111 : 63

AlwaysOn63_Signal

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

#1 : 1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.

#1 : 1

DMA channel is enabled

End of enumeration elements list.


CHCFG11

Channel Configuration register
address_offset : 0x42 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG11 CHCFG11 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOURCE TRIG ENBL

SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

#0 : 0

Disable_Signal

#10 : 2

UART0Rx_Signal

#11 : 3

UART0Tx_Signal

#100 : 4

UART1Rx_Signal

#101 : 5

UART1Tx_Signal

#110 : 6

PWMA0WR_Signal

#111 : 7

PWMA1WR_Signal

#1000 : 8

PWMA2WR_Signal

#1001 : 9

PWMA3WR_Signal

#1010 : 10

PWMA0CP_Signal

#1011 : 11

PWMA1CP_Signal

#1100 : 12

PWMA2CP_Signal

#1101 : 13

PWMA3CP_Signal

#1110 : 14

CAN0Rx_Signal

#1111 : 15

CAN1Rx_Signal

#10000 : 16

SPI0Rx_Signal

#10001 : 17

SPI0Tx_Signal

#10010 : 18

XBARAOut0_Signal

#10011 : 19

XBARAOut1_Signal

#10100 : 20

XBARAOut2_Signal

#10101 : 21

XBARAOut3_Signal

#10110 : 22

I2C0_Signal

#100010 : 34

CMP3_Signal

#101000 : 40

ADCA_Signal

#101001 : 41

ADCB_Signal

#101010 : 42

CMP0_Signal

#101011 : 43

CMP1_Signal

#101100 : 44

CMP2_Signal

#101101 : 45

DAC0_Signal

#101111 : 47

PDB0_Signal

#110000 : 48

PDB1_Signal

#110001 : 49

PortA_Signal

#110010 : 50

PortB_Signal

#110011 : 51

PortC_Signal

#110100 : 52

PortD_Signal

#110101 : 53

PortE_Signal

#111010 : 58

AlwaysOn58_Signal

#111011 : 59

AlwaysOn59_Signal

#111100 : 60

AlwaysOn60_Signal

#111101 : 61

AlwaysOn61_Signal

#111110 : 62

AlwaysOn62_Signal

#111111 : 63

AlwaysOn63_Signal

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

#1 : 1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.

#1 : 1

DMA channel is enabled

End of enumeration elements list.


CHCFG12

Channel Configuration register
address_offset : 0x4E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG12 CHCFG12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOURCE TRIG ENBL

SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

#0 : 0

Disable_Signal

#10 : 2

UART0Rx_Signal

#11 : 3

UART0Tx_Signal

#100 : 4

UART1Rx_Signal

#101 : 5

UART1Tx_Signal

#110 : 6

PWMA0WR_Signal

#111 : 7

PWMA1WR_Signal

#1000 : 8

PWMA2WR_Signal

#1001 : 9

PWMA3WR_Signal

#1010 : 10

PWMA0CP_Signal

#1011 : 11

PWMA1CP_Signal

#1100 : 12

PWMA2CP_Signal

#1101 : 13

PWMA3CP_Signal

#1110 : 14

CAN0Rx_Signal

#1111 : 15

CAN1Rx_Signal

#10000 : 16

SPI0Rx_Signal

#10001 : 17

SPI0Tx_Signal

#10010 : 18

XBARAOut0_Signal

#10011 : 19

XBARAOut1_Signal

#10100 : 20

XBARAOut2_Signal

#10101 : 21

XBARAOut3_Signal

#10110 : 22

I2C0_Signal

#100010 : 34

CMP3_Signal

#101000 : 40

ADCA_Signal

#101001 : 41

ADCB_Signal

#101010 : 42

CMP0_Signal

#101011 : 43

CMP1_Signal

#101100 : 44

CMP2_Signal

#101101 : 45

DAC0_Signal

#101111 : 47

PDB0_Signal

#110000 : 48

PDB1_Signal

#110001 : 49

PortA_Signal

#110010 : 50

PortB_Signal

#110011 : 51

PortC_Signal

#110100 : 52

PortD_Signal

#110101 : 53

PortE_Signal

#111010 : 58

AlwaysOn58_Signal

#111011 : 59

AlwaysOn59_Signal

#111100 : 60

AlwaysOn60_Signal

#111101 : 61

AlwaysOn61_Signal

#111110 : 62

AlwaysOn62_Signal

#111111 : 63

AlwaysOn63_Signal

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

#1 : 1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.

#1 : 1

DMA channel is enabled

End of enumeration elements list.


CHCFG13

Channel Configuration register
address_offset : 0x5B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG13 CHCFG13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOURCE TRIG ENBL

SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

#0 : 0

Disable_Signal

#10 : 2

UART0Rx_Signal

#11 : 3

UART0Tx_Signal

#100 : 4

UART1Rx_Signal

#101 : 5

UART1Tx_Signal

#110 : 6

PWMA0WR_Signal

#111 : 7

PWMA1WR_Signal

#1000 : 8

PWMA2WR_Signal

#1001 : 9

PWMA3WR_Signal

#1010 : 10

PWMA0CP_Signal

#1011 : 11

PWMA1CP_Signal

#1100 : 12

PWMA2CP_Signal

#1101 : 13

PWMA3CP_Signal

#1110 : 14

CAN0Rx_Signal

#1111 : 15

CAN1Rx_Signal

#10000 : 16

SPI0Rx_Signal

#10001 : 17

SPI0Tx_Signal

#10010 : 18

XBARAOut0_Signal

#10011 : 19

XBARAOut1_Signal

#10100 : 20

XBARAOut2_Signal

#10101 : 21

XBARAOut3_Signal

#10110 : 22

I2C0_Signal

#100010 : 34

CMP3_Signal

#101000 : 40

ADCA_Signal

#101001 : 41

ADCB_Signal

#101010 : 42

CMP0_Signal

#101011 : 43

CMP1_Signal

#101100 : 44

CMP2_Signal

#101101 : 45

DAC0_Signal

#101111 : 47

PDB0_Signal

#110000 : 48

PDB1_Signal

#110001 : 49

PortA_Signal

#110010 : 50

PortB_Signal

#110011 : 51

PortC_Signal

#110100 : 52

PortD_Signal

#110101 : 53

PortE_Signal

#111010 : 58

AlwaysOn58_Signal

#111011 : 59

AlwaysOn59_Signal

#111100 : 60

AlwaysOn60_Signal

#111101 : 61

AlwaysOn61_Signal

#111110 : 62

AlwaysOn62_Signal

#111111 : 63

AlwaysOn63_Signal

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

#1 : 1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.

#1 : 1

DMA channel is enabled

End of enumeration elements list.


CHCFG3

Channel Configuration register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG3 CHCFG3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOURCE TRIG ENBL

SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

#0 : 0

Disable_Signal

#10 : 2

UART0Rx_Signal

#11 : 3

UART0Tx_Signal

#100 : 4

UART1Rx_Signal

#101 : 5

UART1Tx_Signal

#110 : 6

PWMA0WR_Signal

#111 : 7

PWMA1WR_Signal

#1000 : 8

PWMA2WR_Signal

#1001 : 9

PWMA3WR_Signal

#1010 : 10

PWMA0CP_Signal

#1011 : 11

PWMA1CP_Signal

#1100 : 12

PWMA2CP_Signal

#1101 : 13

PWMA3CP_Signal

#1110 : 14

CAN0Rx_Signal

#1111 : 15

CAN1Rx_Signal

#10000 : 16

SPI0Rx_Signal

#10001 : 17

SPI0Tx_Signal

#10010 : 18

XBARAOut0_Signal

#10011 : 19

XBARAOut1_Signal

#10100 : 20

XBARAOut2_Signal

#10101 : 21

XBARAOut3_Signal

#10110 : 22

I2C0_Signal

#100010 : 34

CMP3_Signal

#101000 : 40

ADCA_Signal

#101001 : 41

ADCB_Signal

#101010 : 42

CMP0_Signal

#101011 : 43

CMP1_Signal

#101100 : 44

CMP2_Signal

#101101 : 45

DAC0_Signal

#101111 : 47

PDB0_Signal

#110000 : 48

PDB1_Signal

#110001 : 49

PortA_Signal

#110010 : 50

PortB_Signal

#110011 : 51

PortC_Signal

#110100 : 52

PortD_Signal

#110101 : 53

PortE_Signal

#111010 : 58

AlwaysOn58_Signal

#111011 : 59

AlwaysOn59_Signal

#111100 : 60

AlwaysOn60_Signal

#111101 : 61

AlwaysOn61_Signal

#111110 : 62

AlwaysOn62_Signal

#111111 : 63

AlwaysOn63_Signal

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

#1 : 1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.

#1 : 1

DMA channel is enabled

End of enumeration elements list.


CHCFG14

Channel Configuration register
address_offset : 0x69 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG14 CHCFG14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOURCE TRIG ENBL

SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

#0 : 0

Disable_Signal

#10 : 2

UART0Rx_Signal

#11 : 3

UART0Tx_Signal

#100 : 4

UART1Rx_Signal

#101 : 5

UART1Tx_Signal

#110 : 6

PWMA0WR_Signal

#111 : 7

PWMA1WR_Signal

#1000 : 8

PWMA2WR_Signal

#1001 : 9

PWMA3WR_Signal

#1010 : 10

PWMA0CP_Signal

#1011 : 11

PWMA1CP_Signal

#1100 : 12

PWMA2CP_Signal

#1101 : 13

PWMA3CP_Signal

#1110 : 14

CAN0Rx_Signal

#1111 : 15

CAN1Rx_Signal

#10000 : 16

SPI0Rx_Signal

#10001 : 17

SPI0Tx_Signal

#10010 : 18

XBARAOut0_Signal

#10011 : 19

XBARAOut1_Signal

#10100 : 20

XBARAOut2_Signal

#10101 : 21

XBARAOut3_Signal

#10110 : 22

I2C0_Signal

#100010 : 34

CMP3_Signal

#101000 : 40

ADCA_Signal

#101001 : 41

ADCB_Signal

#101010 : 42

CMP0_Signal

#101011 : 43

CMP1_Signal

#101100 : 44

CMP2_Signal

#101101 : 45

DAC0_Signal

#101111 : 47

PDB0_Signal

#110000 : 48

PDB1_Signal

#110001 : 49

PortA_Signal

#110010 : 50

PortB_Signal

#110011 : 51

PortC_Signal

#110100 : 52

PortD_Signal

#110101 : 53

PortE_Signal

#111010 : 58

AlwaysOn58_Signal

#111011 : 59

AlwaysOn59_Signal

#111100 : 60

AlwaysOn60_Signal

#111101 : 61

AlwaysOn61_Signal

#111110 : 62

AlwaysOn62_Signal

#111111 : 63

AlwaysOn63_Signal

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

#1 : 1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.

#1 : 1

DMA channel is enabled

End of enumeration elements list.


CHCFG15

Channel Configuration register
address_offset : 0x78 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG15 CHCFG15 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOURCE TRIG ENBL

SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

#0 : 0

Disable_Signal

#10 : 2

UART0Rx_Signal

#11 : 3

UART0Tx_Signal

#100 : 4

UART1Rx_Signal

#101 : 5

UART1Tx_Signal

#110 : 6

PWMA0WR_Signal

#111 : 7

PWMA1WR_Signal

#1000 : 8

PWMA2WR_Signal

#1001 : 9

PWMA3WR_Signal

#1010 : 10

PWMA0CP_Signal

#1011 : 11

PWMA1CP_Signal

#1100 : 12

PWMA2CP_Signal

#1101 : 13

PWMA3CP_Signal

#1110 : 14

CAN0Rx_Signal

#1111 : 15

CAN1Rx_Signal

#10000 : 16

SPI0Rx_Signal

#10001 : 17

SPI0Tx_Signal

#10010 : 18

XBARAOut0_Signal

#10011 : 19

XBARAOut1_Signal

#10100 : 20

XBARAOut2_Signal

#10101 : 21

XBARAOut3_Signal

#10110 : 22

I2C0_Signal

#100010 : 34

CMP3_Signal

#101000 : 40

ADCA_Signal

#101001 : 41

ADCB_Signal

#101010 : 42

CMP0_Signal

#101011 : 43

CMP1_Signal

#101100 : 44

CMP2_Signal

#101101 : 45

DAC0_Signal

#101111 : 47

PDB0_Signal

#110000 : 48

PDB1_Signal

#110001 : 49

PortA_Signal

#110010 : 50

PortB_Signal

#110011 : 51

PortC_Signal

#110100 : 52

PortD_Signal

#110101 : 53

PortE_Signal

#111010 : 58

AlwaysOn58_Signal

#111011 : 59

AlwaysOn59_Signal

#111100 : 60

AlwaysOn60_Signal

#111101 : 61

AlwaysOn61_Signal

#111110 : 62

AlwaysOn62_Signal

#111111 : 63

AlwaysOn63_Signal

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

#1 : 1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.

#1 : 1

DMA channel is enabled

End of enumeration elements list.


CHCFG4

Channel Configuration register
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG4 CHCFG4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOURCE TRIG ENBL

SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

#0 : 0

Disable_Signal

#10 : 2

UART0Rx_Signal

#11 : 3

UART0Tx_Signal

#100 : 4

UART1Rx_Signal

#101 : 5

UART1Tx_Signal

#110 : 6

PWMA0WR_Signal

#111 : 7

PWMA1WR_Signal

#1000 : 8

PWMA2WR_Signal

#1001 : 9

PWMA3WR_Signal

#1010 : 10

PWMA0CP_Signal

#1011 : 11

PWMA1CP_Signal

#1100 : 12

PWMA2CP_Signal

#1101 : 13

PWMA3CP_Signal

#1110 : 14

CAN0Rx_Signal

#1111 : 15

CAN1Rx_Signal

#10000 : 16

SPI0Rx_Signal

#10001 : 17

SPI0Tx_Signal

#10010 : 18

XBARAOut0_Signal

#10011 : 19

XBARAOut1_Signal

#10100 : 20

XBARAOut2_Signal

#10101 : 21

XBARAOut3_Signal

#10110 : 22

I2C0_Signal

#100010 : 34

CMP3_Signal

#101000 : 40

ADCA_Signal

#101001 : 41

ADCB_Signal

#101010 : 42

CMP0_Signal

#101011 : 43

CMP1_Signal

#101100 : 44

CMP2_Signal

#101101 : 45

DAC0_Signal

#101111 : 47

PDB0_Signal

#110000 : 48

PDB1_Signal

#110001 : 49

PortA_Signal

#110010 : 50

PortB_Signal

#110011 : 51

PortC_Signal

#110100 : 52

PortD_Signal

#110101 : 53

PortE_Signal

#111010 : 58

AlwaysOn58_Signal

#111011 : 59

AlwaysOn59_Signal

#111100 : 60

AlwaysOn60_Signal

#111101 : 61

AlwaysOn61_Signal

#111110 : 62

AlwaysOn62_Signal

#111111 : 63

AlwaysOn63_Signal

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

#1 : 1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.

#1 : 1

DMA channel is enabled

End of enumeration elements list.


CHCFG5

Channel Configuration register
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG5 CHCFG5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOURCE TRIG ENBL

SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

#0 : 0

Disable_Signal

#10 : 2

UART0Rx_Signal

#11 : 3

UART0Tx_Signal

#100 : 4

UART1Rx_Signal

#101 : 5

UART1Tx_Signal

#110 : 6

PWMA0WR_Signal

#111 : 7

PWMA1WR_Signal

#1000 : 8

PWMA2WR_Signal

#1001 : 9

PWMA3WR_Signal

#1010 : 10

PWMA0CP_Signal

#1011 : 11

PWMA1CP_Signal

#1100 : 12

PWMA2CP_Signal

#1101 : 13

PWMA3CP_Signal

#1110 : 14

CAN0Rx_Signal

#1111 : 15

CAN1Rx_Signal

#10000 : 16

SPI0Rx_Signal

#10001 : 17

SPI0Tx_Signal

#10010 : 18

XBARAOut0_Signal

#10011 : 19

XBARAOut1_Signal

#10100 : 20

XBARAOut2_Signal

#10101 : 21

XBARAOut3_Signal

#10110 : 22

I2C0_Signal

#100010 : 34

CMP3_Signal

#101000 : 40

ADCA_Signal

#101001 : 41

ADCB_Signal

#101010 : 42

CMP0_Signal

#101011 : 43

CMP1_Signal

#101100 : 44

CMP2_Signal

#101101 : 45

DAC0_Signal

#101111 : 47

PDB0_Signal

#110000 : 48

PDB1_Signal

#110001 : 49

PortA_Signal

#110010 : 50

PortB_Signal

#110011 : 51

PortC_Signal

#110100 : 52

PortD_Signal

#110101 : 53

PortE_Signal

#111010 : 58

AlwaysOn58_Signal

#111011 : 59

AlwaysOn59_Signal

#111100 : 60

AlwaysOn60_Signal

#111101 : 61

AlwaysOn61_Signal

#111110 : 62

AlwaysOn62_Signal

#111111 : 63

AlwaysOn63_Signal

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

#1 : 1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.

#1 : 1

DMA channel is enabled

End of enumeration elements list.



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