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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL1

SDIS

RSLT6

HILIM1

STAT

RSLT7

LOLIM3

RDY

LOLIMSTAT

RSLT8

HILIM2

OFFST1

LOLIM4

HILIMSTAT

RSLT9

ZXSTAT

RSLT10

LOLIM5

HILIM3

RSLT11

OFFST2

CTRL2

LOLIM6

RSLT12

HILIM4

LOLIM7

RSLT13

OFFST3

RSLT14

LOLIM8

HILIM5

RSLT15

LOLIM9

OFFST4

HILIM6

LOLIM10

HILIM7

RSLT0

OFFST5

LOLIM11

HILIM8

LOLIM12

ZXCTRL1

OFFST6

LOLIM13

HILIM9

LOLIM14

OFFST7

HILIM10

LOLIM15

OFFST8

HILIM11

RSLT1

HILIM12

OFFST9

ZXCTRL2

HILIM13

OFFST10

HILIM14

OFFST11

HILIM15

RSLT2

OFFST12

LOLIM0

OFFST13

CLIST1

OFFST14

OFFST15

RSLT3

PWR

CAL

CLIST2

GC1

GC2

SCTRL

PWR2

CTRL3

SCHLTEN

LOLIM1

HILIM0

RSLT4

CLIST3

CLIST4

RSLT5

LOLIM2

OFFST0


CTRL1

ADC Control Register 1
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL1 CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMODE CHNCFG_L HLMTIE LLMTIE ZCIE EOSIE0 SYNC0 START0 STOP0 DMAEN0

SMODE : ADC Scan Mode Control
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 000

Once (single) sequential

#001 : 001

Once parallel

#010 : 010

Loop sequential

#011 : 011

Loop parallel

#100 : 100

Triggered sequential

#101 : 101

Triggered parallel (default)

End of enumeration elements list.

CHNCFG_L : CHCNF (Channel Configure Low) bits
bits : 4 - 7 (4 bit)
access : read-write

HLMTIE : High Limit Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

LLMTIE : Low Limit Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

ZCIE : Zero Crossing Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

EOSIE0 : End Of Scan Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

SYNC0 : SYNC0 Enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Scan is initiated by a write to CTRL1[START0] only

#1 : 1

Use a SYNC0 input pulse or CTRL1[START0] to initiate a scan

End of enumeration elements list.

START0 : START0 Conversion
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

#0 : 0

No action

#1 : 1

Start command is issued

End of enumeration elements list.

STOP0 : Stop
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal operation

#1 : 1

Stop mode

End of enumeration elements list.

DMAEN0 : DMA enable
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA is not enabled.

#1 : 1

DMA is enabled.

End of enumeration elements list.


SDIS

ADC Sample Disable Register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDIS SDIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DS

DS : Disable Sample Bits
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

#0 : 0

SAMPLEx channel is enabled for ADC scan.

#1 : 1

SAMPLEx channel is disabled for ADC scan and corresponding channels after SAMPLEx also doesn not occur in an ADC scan.

End of enumeration elements list.


RSLT6

ADC Result Registers with sign extension
address_offset : 0x10A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSLT6 RSLT6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSLT SEXT

RSLT : Digital Result of the Conversion
bits : 3 - 14 (12 bit)
access : read-write

SEXT : Sign Extend
bits : 15 - 15 (1 bit)
access : read-only


HILIM1

ADC High Limit Registers
address_offset : 0x116 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HILIM1 HILIM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HLMT

HLMT : High Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


STAT

ADC Status Register
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UNDEFINED HLMTI LLMTI ZCI EOSI0 EOSI1 CIP1 CIP0

UNDEFINED : This read-only bitfield is undefined and will always contain random data.
bits : 0 - 7 (8 bit)
access : read-only

HLMTI : High Limit Interrupt
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

#0 : 0

No high limit interrupt request

#1 : 1

High limit exceeded, IRQ pending if CTRL1[HLMTIE] is set

End of enumeration elements list.

LLMTI : Low Limit Interrupt
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

#0 : 0

No low limit interrupt request

#1 : 1

Low limit exceeded, IRQ pending if CTRL1[LLMTIE] is set

End of enumeration elements list.

ZCI : Zero Crossing Interrupt
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

#0 : 0

No zero crossing interrupt request

#1 : 1

Zero crossing encountered, IRQ pending if CTRL1[ZCIE] is set

End of enumeration elements list.

EOSI0 : End of Scan Interrupt
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

A scan cycle has not been completed, no end of scan IRQ pending

#1 : 1

A scan cycle has been completed, end of scan IRQ pending

End of enumeration elements list.

EOSI1 : End of Scan Interrupt
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

A scan cycle has not been completed, no end of scan IRQ pending

#1 : 1

A scan cycle has been completed, end of scan IRQ pending

End of enumeration elements list.

CIP1 : Conversion in Progress
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

#0 : 0

Idle state

#1 : 1

A scan cycle is in progress. The ADC will ignore all sync pulses or start commands

End of enumeration elements list.

CIP0 : Conversion in Progress
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

#0 : 0

Idle state

#1 : 1

A scan cycle is in progress. The ADC will ignore all sync pulses or start commands

End of enumeration elements list.


RSLT7

ADC Result Registers with sign extension
address_offset : 0x134 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSLT7 RSLT7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSLT SEXT

RSLT : Digital Result of the Conversion
bits : 3 - 14 (12 bit)
access : read-write

SEXT : Sign Extend
bits : 15 - 15 (1 bit)
access : read-only


LOLIM3

ADC Low Limit Registers
address_offset : 0x138 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOLIM3 LOLIM3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LLMT

LLMT : Low Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


RDY

ADC Ready Register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RDY RDY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDY

RDY : Ready Sample
bits : 0 - 15 (16 bit)
access : read-only

Enumeration:

#0 : 0

Sample not ready or has been read

#1 : 1

Sample ready to be read

End of enumeration elements list.


LOLIMSTAT

ADC Low Limit Status Register
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOLIMSTAT LOLIMSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LLS

LLS : Low Limit Status Bits
bits : 0 - 15 (16 bit)
access : read-write


RSLT8

ADC Result Registers with sign extension
address_offset : 0x160 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSLT8 RSLT8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSLT SEXT

RSLT : Digital Result of the Conversion
bits : 3 - 14 (12 bit)
access : read-write

SEXT : Sign Extend
bits : 15 - 15 (1 bit)
access : read-only


HILIM2

ADC High Limit Registers
address_offset : 0x176 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HILIM2 HILIM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HLMT

HLMT : High Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


OFFST1

ADC Offset Registers
address_offset : 0x176 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFFST1 OFFST1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET

OFFSET : ADC Offset Bits
bits : 3 - 14 (12 bit)
access : read-write


LOLIM4

ADC Low Limit Registers
address_offset : 0x17C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOLIM4 LOLIM4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LLMT

LLMT : Low Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


HILIMSTAT

ADC High Limit Status Register
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HILIMSTAT HILIMSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HLS

HLS : High Limit Status Bits
bits : 0 - 15 (16 bit)
access : read-write


RSLT9

ADC Result Registers with sign extension
address_offset : 0x18E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSLT9 RSLT9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSLT SEXT

RSLT : Digital Result of the Conversion
bits : 3 - 14 (12 bit)
access : read-write

SEXT : Sign Extend
bits : 15 - 15 (1 bit)
access : read-only


ZXSTAT

ADC Zero Crossing Status Register
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ZXSTAT ZXSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ZCS

ZCS : Zero Crossing Status
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

#0 : 0

Either: A sign change did not occur in a comparison between the current channelx result and the previous channelx result, or Zero crossing control is disabled for channelx in the zero crossing control register, ZXCTRL

#1 : 1

In a comparison between the current channelx result and the previous channelx result, a sign change condition occurred as defined in the zero crossing control register (ZXCTRL)

End of enumeration elements list.


RSLT10

ADC Result Registers with sign extension
address_offset : 0x1BE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSLT10 RSLT10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSLT SEXT

RSLT : Digital Result of the Conversion
bits : 3 - 14 (12 bit)
access : read-write

SEXT : Sign Extend
bits : 15 - 15 (1 bit)
access : read-only


LOLIM5

ADC Low Limit Registers
address_offset : 0x1C2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOLIM5 LOLIM5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LLMT

LLMT : Low Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


HILIM3

ADC High Limit Registers
address_offset : 0x1D8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HILIM3 HILIM3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HLMT

HLMT : High Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


RSLT11

ADC Result Registers with sign extension
address_offset : 0x1F0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSLT11 RSLT11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSLT SEXT

RSLT : Digital Result of the Conversion
bits : 3 - 14 (12 bit)
access : read-write

SEXT : Sign Extend
bits : 15 - 15 (1 bit)
access : read-only


OFFST2

ADC Offset Registers
address_offset : 0x1F6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFFST2 OFFST2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET

OFFSET : ADC Offset Bits
bits : 3 - 14 (12 bit)
access : read-write


CTRL2

ADC Control Register 2
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL2 CTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV0 SIMULT CHNCFG_H EOSIE1 SYNC1 START1 STOP1 DMAEN1

DIV0 : Clock Divisor Select
bits : 0 - 5 (6 bit)
access : read-write

SIMULT : Simultaneous mode
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Parallel scans done independently

#1 : 1

Parallel scans done simultaneously (default)

End of enumeration elements list.

CHNCFG_H : CHCNF (Channel Configure High) bits
bits : 7 - 10 (4 bit)
access : read-write

EOSIE1 : End Of Scan Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

SYNC1 : SYNC1 Enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

B converter parallel scan is initiated by a write to CTRL2[START1] bit only

#1 : 1

Use a SYNC1 input pulse or CTRL2[START1] bit to initiate a B converter parallel scan

End of enumeration elements list.

START1 : START1 Conversion
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

#0 : 0

No action

#1 : 1

Start command is issued

End of enumeration elements list.

STOP1 : Stop
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal operation

#1 : 1

Stop mode

End of enumeration elements list.

DMAEN1 : DMA enable
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA is not enabled.

#1 : 1

DMA is enabled.

End of enumeration elements list.


LOLIM6

ADC Low Limit Registers
address_offset : 0x20A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOLIM6 LOLIM6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LLMT

LLMT : Low Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


RSLT12

ADC Result Registers with sign extension
address_offset : 0x224 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSLT12 RSLT12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSLT SEXT

RSLT : Digital Result of the Conversion
bits : 3 - 14 (12 bit)
access : read-write

SEXT : Sign Extend
bits : 15 - 15 (1 bit)
access : read-only


HILIM4

ADC High Limit Registers
address_offset : 0x23C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HILIM4 HILIM4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HLMT

HLMT : High Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


LOLIM7

ADC Low Limit Registers
address_offset : 0x254 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOLIM7 LOLIM7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LLMT

LLMT : Low Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


RSLT13

ADC Result Registers with sign extension
address_offset : 0x25A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSLT13 RSLT13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSLT SEXT

RSLT : Digital Result of the Conversion
bits : 3 - 14 (12 bit)
access : read-write

SEXT : Sign Extend
bits : 15 - 15 (1 bit)
access : read-only


OFFST3

ADC Offset Registers
address_offset : 0x278 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFFST3 OFFST3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET

OFFSET : ADC Offset Bits
bits : 3 - 14 (12 bit)
access : read-write


RSLT14

ADC Result Registers with sign extension
address_offset : 0x292 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSLT14 RSLT14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSLT SEXT

RSLT : Digital Result of the Conversion
bits : 3 - 14 (12 bit)
access : read-write

SEXT : Sign Extend
bits : 15 - 15 (1 bit)
access : read-only


LOLIM8

ADC Low Limit Registers
address_offset : 0x2A0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOLIM8 LOLIM8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LLMT

LLMT : Low Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


HILIM5

ADC High Limit Registers
address_offset : 0x2A2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HILIM5 HILIM5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HLMT

HLMT : High Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


RSLT15

ADC Result Registers with sign extension
address_offset : 0x2CC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSLT15 RSLT15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSLT SEXT

RSLT : Digital Result of the Conversion
bits : 3 - 14 (12 bit)
access : read-write

SEXT : Sign Extend
bits : 15 - 15 (1 bit)
access : read-only


LOLIM9

ADC Low Limit Registers
address_offset : 0x2EE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOLIM9 LOLIM9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LLMT

LLMT : Low Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


OFFST4

ADC Offset Registers
address_offset : 0x2FC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFFST4 OFFST4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET

OFFSET : ADC Offset Bits
bits : 3 - 14 (12 bit)
access : read-write


HILIM6

ADC High Limit Registers
address_offset : 0x30A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HILIM6 HILIM6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HLMT

HLMT : High Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


LOLIM10

ADC Low Limit Registers
address_offset : 0x33E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOLIM10 LOLIM10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LLMT

LLMT : Low Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


HILIM7

ADC High Limit Registers
address_offset : 0x374 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HILIM7 HILIM7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HLMT

HLMT : High Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


RSLT0

ADC Result Registers with sign extension
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSLT0 RSLT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSLT SEXT

RSLT : Digital Result of the Conversion
bits : 3 - 14 (12 bit)
access : read-write

SEXT : Sign Extend
bits : 15 - 15 (1 bit)
access : read-only


OFFST5

ADC Offset Registers
address_offset : 0x382 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFFST5 OFFST5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET

OFFSET : ADC Offset Bits
bits : 3 - 14 (12 bit)
access : read-write


LOLIM11

ADC Low Limit Registers
address_offset : 0x390 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOLIM11 LOLIM11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LLMT

LLMT : Low Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


HILIM8

ADC High Limit Registers
address_offset : 0x3E0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HILIM8 HILIM8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HLMT

HLMT : High Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


LOLIM12

ADC Low Limit Registers
address_offset : 0x3E4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOLIM12 LOLIM12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LLMT

LLMT : Low Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


ZXCTRL1

ADC Zero Crossing Control 1 Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ZXCTRL1 ZXCTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ZCE0 ZCE1 ZCE2 ZCE3 ZCE4 ZCE5 ZCE6 ZCE7

ZCE0 : Zero crossing enable 0
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

Zero Crossing disabled

#01 : 01

Zero Crossing enabled for positive to negative sign change

#10 : 10

Zero Crossing enabled for negative to positive sign change

#11 : 11

Zero Crossing enabled for any sign change

End of enumeration elements list.

ZCE1 : Zero crossing enable 1
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 00

Zero Crossing disabled

#01 : 01

Zero Crossing enabled for positive to negative sign change

#10 : 10

Zero Crossing enabled for negative to positive sign change

#11 : 11

Zero Crossing enabled for any sign change

End of enumeration elements list.

ZCE2 : Zero crossing enable 2
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 00

Zero Crossing disabled

#01 : 01

Zero Crossing enabled for positive to negative sign change

#10 : 10

Zero Crossing enabled for negative to positive sign change

#11 : 11

Zero Crossing enabled for any sign change

End of enumeration elements list.

ZCE3 : Zero crossing enable 3
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 00

Zero Crossing disabled

#01 : 01

Zero Crossing enabled for positive to negative sign change

#10 : 10

Zero Crossing enabled for negative to positive sign change

#11 : 11

Zero Crossing enabled for any sign change

End of enumeration elements list.

ZCE4 : Zero crossing enable 4
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 00

Zero Crossing disabled

#01 : 01

Zero Crossing enabled for positive to negative sign change

#10 : 10

Zero Crossing enabled for negative to positive sign change

#11 : 11

Zero Crossing enabled for any sign change

End of enumeration elements list.

ZCE5 : Zero crossing enable 5
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

#00 : 00

Zero Crossing disabled

#01 : 01

Zero Crossing enabled for positive to negative sign change

#10 : 10

Zero Crossing enabled for negative to positive sign change

#11 : 11

Zero Crossing enabled for any sign change

End of enumeration elements list.

ZCE6 : Zero crossing enable 6
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

#00 : 00

Zero Crossing disabled

#01 : 01

Zero Crossing enabled for positive to negative sign change

#10 : 10

Zero Crossing enabled for negative to positive sign change

#11 : 11

Zero Crossing enabled for any sign change

End of enumeration elements list.

ZCE7 : Zero crossing enable 7
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

#00 : 00

Zero Crossing disabled

#01 : 01

Zero Crossing enabled for positive to negative sign change

#10 : 10

Zero Crossing enabled for negative to positive sign change

#11 : 11

Zero Crossing enabled for any sign change

End of enumeration elements list.


OFFST6

ADC Offset Registers
address_offset : 0x40A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFFST6 OFFST6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET

OFFSET : ADC Offset Bits
bits : 3 - 14 (12 bit)
access : read-write


LOLIM13

ADC Low Limit Registers
address_offset : 0x43A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOLIM13 LOLIM13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LLMT

LLMT : Low Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


HILIM9

ADC High Limit Registers
address_offset : 0x44E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HILIM9 HILIM9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HLMT

HLMT : High Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


LOLIM14

ADC Low Limit Registers
address_offset : 0x492 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOLIM14 LOLIM14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LLMT

LLMT : Low Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


OFFST7

ADC Offset Registers
address_offset : 0x494 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFFST7 OFFST7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET

OFFSET : ADC Offset Bits
bits : 3 - 14 (12 bit)
access : read-write


HILIM10

ADC High Limit Registers
address_offset : 0x4BE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HILIM10 HILIM10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HLMT

HLMT : High Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


LOLIM15

ADC Low Limit Registers
address_offset : 0x4EC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOLIM15 LOLIM15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LLMT

LLMT : Low Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


OFFST8

ADC Offset Registers
address_offset : 0x520 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFFST8 OFFST8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET

OFFSET : ADC Offset Bits
bits : 3 - 14 (12 bit)
access : read-write


HILIM11

ADC High Limit Registers
address_offset : 0x530 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HILIM11 HILIM11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HLMT

HLMT : High Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


RSLT1

ADC Result Registers with sign extension
address_offset : 0x56 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSLT1 RSLT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSLT SEXT

RSLT : Digital Result of the Conversion
bits : 3 - 14 (12 bit)
access : read-write

SEXT : Sign Extend
bits : 15 - 15 (1 bit)
access : read-only


HILIM12

ADC High Limit Registers
address_offset : 0x5A4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HILIM12 HILIM12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HLMT

HLMT : High Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


OFFST9

ADC Offset Registers
address_offset : 0x5AE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFFST9 OFFST9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET

OFFSET : ADC Offset Bits
bits : 3 - 14 (12 bit)
access : read-write


ZXCTRL2

ADC Zero Crossing Control 2 Register
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ZXCTRL2 ZXCTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ZCE8 ZCE9 ZCE10 ZCE11 ZCE12 ZCE13 ZCE14 ZCE15

ZCE8 : Zero crossing enable 8
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

Zero Crossing disabled

#01 : 01

Zero Crossing enabled for positive to negative sign change

#10 : 10

Zero Crossing enabled for negative to positive sign change

#11 : 11

Zero Crossing enabled for any sign change

End of enumeration elements list.

ZCE9 : Zero crossing enable 9
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 00

Zero Crossing disabled

#01 : 01

Zero Crossing enabled for positive to negative sign change

#10 : 10

Zero Crossing enabled for negative to positive sign change

#11 : 11

Zero Crossing enabled for any sign change

End of enumeration elements list.

ZCE10 : Zero crossing enable 10
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 00

Zero Crossing disabled

#01 : 01

Zero Crossing enabled for positive to negative sign change

#10 : 10

Zero Crossing enabled for negative to positive sign change

#11 : 11

Zero Crossing enabled for any sign change

End of enumeration elements list.

ZCE11 : Zero crossing enable 11
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 00

Zero Crossing disabled

#01 : 01

Zero Crossing enabled for positive to negative sign change

#10 : 10

Zero Crossing enabled for negative to positive sign change

#11 : 11

Zero Crossing enabled for any sign change

End of enumeration elements list.

ZCE12 : Zero crossing enable 12
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 00

Zero Crossing disabled

#01 : 01

Zero Crossing enabled for positive to negative sign change

#10 : 10

Zero Crossing enabled for negative to positive sign change

#11 : 11

Zero Crossing enabled for any sign change

End of enumeration elements list.

ZCE13 : Zero crossing enable 13
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

#00 : 00

Zero Crossing disabled

#01 : 01

Zero Crossing enabled for positive to negative sign change

#10 : 10

Zero Crossing enabled for negative to positive sign change

#11 : 11

Zero Crossing enabled for any sign change

End of enumeration elements list.

ZCE14 : Zero crossing enable 14
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

#00 : 00

Zero Crossing disabled

#01 : 01

Zero Crossing enabled for positive to negative sign change

#10 : 10

Zero Crossing enabled for negative to positive sign change

#11 : 11

Zero Crossing enabled for any sign change

End of enumeration elements list.

ZCE15 : Zero crossing enable 15
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

#00 : 00

Zero Crossing disabled

#01 : 01

Zero Crossing enabled for positive to negative sign change

#10 : 10

Zero Crossing enabled for negative to positive sign change

#11 : 11

Zero Crossing enabled for any sign change

End of enumeration elements list.


HILIM13

ADC High Limit Registers
address_offset : 0x61A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HILIM13 HILIM13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HLMT

HLMT : High Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


OFFST10

ADC Offset Registers
address_offset : 0x63E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFFST10 OFFST10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET

OFFSET : ADC Offset Bits
bits : 3 - 14 (12 bit)
access : read-write


HILIM14

ADC High Limit Registers
address_offset : 0x692 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HILIM14 HILIM14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HLMT

HLMT : High Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


OFFST11

ADC Offset Registers
address_offset : 0x6D0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFFST11 OFFST11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET

OFFSET : ADC Offset Bits
bits : 3 - 14 (12 bit)
access : read-write


HILIM15

ADC High Limit Registers
address_offset : 0x70C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HILIM15 HILIM15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HLMT

HLMT : High Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


RSLT2

ADC Result Registers with sign extension
address_offset : 0x76 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSLT2 RSLT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSLT SEXT

RSLT : Digital Result of the Conversion
bits : 3 - 14 (12 bit)
access : read-write

SEXT : Sign Extend
bits : 15 - 15 (1 bit)
access : read-only


OFFST12

ADC Offset Registers
address_offset : 0x764 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFFST12 OFFST12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET

OFFSET : ADC Offset Bits
bits : 3 - 14 (12 bit)
access : read-write


LOLIM0

ADC Low Limit Registers
address_offset : 0x78 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOLIM0 LOLIM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LLMT

LLMT : Low Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


OFFST13

ADC Offset Registers
address_offset : 0x7FA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFFST13 OFFST13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET

OFFSET : ADC Offset Bits
bits : 3 - 14 (12 bit)
access : read-write


CLIST1

ADC Channel List Register 1
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLIST1 CLIST1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAMPLE0 SAMPLE1 SAMPLE2 SAMPLE3

SAMPLE0 : Sample Field 0
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1-

#0001 : 0001

Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1-

#0010 : 0010

Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3-

#0011 : 0011

Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3-

#0100 : 0100

Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5-

#0101 : 0101

Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5-

#0110 : 0110

Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7-

#0111 : 0111

Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7-

#1000 : 1000

Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1-

#1001 : 1001

Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1-

#1010 : 1010

Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3-

#1011 : 1011

Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3-

#1100 : 1100

Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5-

#1101 : 1101

Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5-

#1110 : 1110

Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7-

#1111 : 1111

Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7-

End of enumeration elements list.

SAMPLE1 : Sample Field 1
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1-

#0001 : 0001

Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1-

#0010 : 0010

Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3-

#0011 : 0011

Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3-

#0100 : 0100

Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5-

#0101 : 0101

Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5-

#0110 : 0110

Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7-

#0111 : 0111

Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7-

#1000 : 1000

Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1-

#1001 : 1001

Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1-

#1010 : 1010

Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3-

#1011 : 1011

Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3-

#1100 : 1100

Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5-

#1101 : 1101

Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5-

#1110 : 1110

Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7-

#1111 : 1111

Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7-

End of enumeration elements list.

SAMPLE2 : Sample Field 2
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1-

#0001 : 0001

Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1-

#0010 : 0010

Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3-

#0011 : 0011

Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3-

#0100 : 0100

Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5-

#0101 : 0101

Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5-

#0110 : 0110

Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7-

#0111 : 0111

Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7-

#1000 : 1000

Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1-

#1001 : 1001

Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1-

#1010 : 1010

Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3-

#1011 : 1011

Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3-

#1100 : 1100

Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5-

#1101 : 1101

Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5-

#1110 : 1110

Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7-

#1111 : 1111

Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7-

End of enumeration elements list.

SAMPLE3 : Sample Field 3
bits : 12 - 15 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1-

#0001 : 0001

Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1-

#0010 : 0010

Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3-

#0011 : 0011

Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3-

#0100 : 0100

Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5-

#0101 : 0101

Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5-

#0110 : 0110

Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7-

#0111 : 0111

Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7-

#1000 : 1000

Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1-

#1001 : 1001

Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1-

#1010 : 1010

Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3-

#1011 : 1011

Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3-

#1100 : 1100

Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5-

#1101 : 1101

Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5-

#1110 : 1110

Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7-

#1111 : 1111

Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7-

End of enumeration elements list.


OFFST14

ADC Offset Registers
address_offset : 0x892 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFFST14 OFFST14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET

OFFSET : ADC Offset Bits
bits : 3 - 14 (12 bit)
access : read-write


OFFST15

ADC Offset Registers
address_offset : 0x92C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFFST15 OFFST15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET

OFFSET : ADC Offset Bits
bits : 3 - 14 (12 bit)
access : read-write


RSLT3

ADC Result Registers with sign extension
address_offset : 0x98 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSLT3 RSLT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSLT SEXT

RSLT : Digital Result of the Conversion
bits : 3 - 14 (12 bit)
access : read-write

SEXT : Sign Extend
bits : 15 - 15 (1 bit)
access : read-only


PWR

ADC Power Control Register
address_offset : 0x9C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWR PWR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD0 PD1 APD PUDELAY PSTS0 PSTS1 ASB

PD0 : Manual Power Down for Converter A
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Power Up ADC converter A

#1 : 1

Power Down ADC converter A

End of enumeration elements list.

PD1 : Manual Power Down for Converter B
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Power Up ADC converter B

#1 : 1

Power Down ADC converter B

End of enumeration elements list.

APD : Auto Powerdown
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Auto Powerdown Mode is not active

#1 : 1

Auto Powerdown Mode is active

End of enumeration elements list.

PUDELAY : Power Up Delay
bits : 4 - 9 (6 bit)
access : read-write

PSTS0 : ADC Converter A Power Status
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

#0 : 0

ADC Converter A is currently powered up

#1 : 1

ADC Converter A is currently powered down

End of enumeration elements list.

PSTS1 : ADC Converter B Power Status
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

#0 : 0

ADC Converter B is currently powered up

#1 : 1

ADC Converter B is currently powered down

End of enumeration elements list.

ASB : Auto Standby
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Auto standby mode disabled

#1 : 1

Auto standby mode enabled

End of enumeration elements list.


CAL

ADC Calibration Register
address_offset : 0x9E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAL CAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL_VREFLO_A SEL_VREFH_A SEL_VREFLO_B SEL_VREFH_B

SEL_VREFLO_A : Select V REFLO Source
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

VREFL pad

#1 : 1

ADCA_CH3

End of enumeration elements list.

SEL_VREFH_A : Select V REFH Source
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

VREFH pad

#1 : 1

ADCA_CH2

End of enumeration elements list.

SEL_VREFLO_B : Select V REFLO Source
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

VREFL pad

#1 : 1

ADCB_CH3

End of enumeration elements list.

SEL_VREFH_B : Select V REFH Source
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

VREFH pad

#1 : 1

ADCB_CH2

End of enumeration elements list.


CLIST2

ADC Channel List Register 2
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLIST2 CLIST2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAMPLE4 SAMPLE5 SAMPLE6 SAMPLE7

SAMPLE4 : Sample Field 4
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1-

#0001 : 0001

Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1-

#0010 : 0010

Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3-

#0011 : 0011

Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3-

#0100 : 0100

Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5-

#0101 : 0101

Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5-

#0110 : 0110

Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7-

#0111 : 0111

Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7-

#1000 : 1000

Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1-

#1001 : 1001

Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1-

#1010 : 1010

Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3-

#1011 : 1011

Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3-

#1100 : 1100

Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5-

#1101 : 1101

Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5-

#1110 : 1110

Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7-

#1111 : 1111

Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7-

End of enumeration elements list.

SAMPLE5 : Sample Field 5
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1-

#0001 : 0001

Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1-

#0010 : 0010

Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3-

#0011 : 0011

Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3-

#0100 : 0100

Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5-

#0101 : 0101

Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5-

#0110 : 0110

Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7-

#0111 : 0111

Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7-

#1000 : 1000

Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1-

#1001 : 1001

Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1-

#1010 : 1010

Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3-

#1011 : 1011

Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3-

#1100 : 1100

Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5-

#1101 : 1101

Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5-

#1110 : 1110

Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7-

#1111 : 1111

Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7-

End of enumeration elements list.

SAMPLE6 : Sample Field 6
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1-

#0001 : 0001

Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1-

#0010 : 0010

Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3-

#0011 : 0011

Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3-

#0100 : 0100

Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5-

#0101 : 0101

Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5-

#0110 : 0110

Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7-

#0111 : 0111

Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7-

#1000 : 1000

Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1-

#1001 : 1001

Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1-

#1010 : 1010

Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3-

#1011 : 1011

Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3-

#1100 : 1100

Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5-

#1101 : 1101

Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5-

#1110 : 1110

Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7-

#1111 : 1111

Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7-

End of enumeration elements list.

SAMPLE7 : Sample Field 7
bits : 12 - 15 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1-

#0001 : 0001

Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1-

#0010 : 0010

Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3-

#0011 : 0011

Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3-

#0100 : 0100

Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5-

#0101 : 0101

Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5-

#0110 : 0110

Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7-

#0111 : 0111

Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7-

#1000 : 1000

Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1-

#1001 : 1001

Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1-

#1010 : 1010

Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3-

#1011 : 1011

Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3-

#1100 : 1100

Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5-

#1101 : 1101

Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5-

#1110 : 1110

Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7-

#1111 : 1111

Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7-

End of enumeration elements list.


GC1

Gain Control 1 Register
address_offset : 0xA0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GC1 GC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GAIN0 GAIN1 GAIN2 GAIN3 GAIN4 GAIN5 GAIN6 GAIN7

GAIN0 : Gain Control Bit 0
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

x1 amplification

#01 : 01

x2 amplification

#10 : 10

x4 amplification

End of enumeration elements list.

GAIN1 : Gain Control Bit 1
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 00

x1 amplification

#01 : 01

x2 amplification

#10 : 10

x4 amplification

End of enumeration elements list.

GAIN2 : Gain Control Bit 2
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 00

x1 amplification

#01 : 01

x2 amplification

#10 : 10

x4 amplification

End of enumeration elements list.

GAIN3 : Gain Control Bit 3
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 00

x1 amplification

#01 : 01

x2 amplification

#10 : 10

x4 amplification

End of enumeration elements list.

GAIN4 : Gain Control Bit 4
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 00

x1 amplification

#01 : 01

x2 amplification

#10 : 10

x4 amplification

End of enumeration elements list.

GAIN5 : Gain Control Bit 5
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

#00 : 00

x1 amplification

#01 : 01

x2 amplification

#10 : 10

x4 amplification

End of enumeration elements list.

GAIN6 : Gain Control Bit 6
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

#00 : 00

x1 amplification

#01 : 01

x2 amplification

#10 : 10

x4 amplification

End of enumeration elements list.

GAIN7 : Gain Control Bit 7
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

#00 : 00

x1 amplification

#01 : 01

x2 amplification

#10 : 10

x4 amplification

End of enumeration elements list.


GC2

Gain Control 2 Register
address_offset : 0xA2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GC2 GC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GAIN8 GAIN9 GAIN10 GAIN11 GAIN12 GAIN13 GAIN14 GAIN15

GAIN8 : Gain Control Bit 8
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

x1 amplification

#01 : 01

x2 amplification

#10 : 10

x4 amplification

End of enumeration elements list.

GAIN9 : Gain Control Bit 9
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 00

x1 amplification

#01 : 01

x2 amplification

#10 : 10

x4 amplification

End of enumeration elements list.

GAIN10 : Gain Control Bit 10
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 00

x1 amplification

#01 : 01

x2 amplification

#10 : 10

x4 amplification

End of enumeration elements list.

GAIN11 : Gain Control Bit 11
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 00

x1 amplification

#01 : 01

x2 amplification

#10 : 10

x4 amplification

End of enumeration elements list.

GAIN12 : Gain Control Bit 12
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 00

x1 amplification

#01 : 01

x2 amplification

#10 : 10

x4 amplification

End of enumeration elements list.

GAIN13 : Gain Control Bit 13
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

#00 : 00

x1 amplification

#01 : 01

x2 amplification

#10 : 10

x4 amplification

End of enumeration elements list.

GAIN14 : Gain Control Bit 14
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

#00 : 00

x1 amplification

#01 : 01

x2 amplification

#10 : 10

x4 amplification

End of enumeration elements list.

GAIN15 : Gain Control Bit 15
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

#00 : 00

x1 amplification

#01 : 01

x2 amplification

#10 : 10

x4 amplification

End of enumeration elements list.


SCTRL

ADC Scan Control Register
address_offset : 0xA4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCTRL SCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SC

SC : Scan Control Bits
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

#0 : 0

Perform sample immediately after the completion of the current sample.

#1 : 1

Delay sample until a new sync input occurs.

End of enumeration elements list.


PWR2

ADC Power Control Register
address_offset : 0xA6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWR2 PWR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPEEDA SPEEDB DIV1

SPEEDA : ADCA Speed Control Bits
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

Conversion clock frequency <= 6.25 MHz; current consumption per converter = 6 mA

#01 : 01

Conversion clock frequency <= 12.5 MHz; current consumption per converter = 10.8 mA

#10 : 10

Conversion clock frequency <= 18.75 MHz; current consumption per converter = 18 mA

#11 : 11

Conversion clock frequency <= 25 MHz; current consumption per converter = 25.2 mA

End of enumeration elements list.

SPEEDB : ADCB Speed Control Bits
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 00

Conversion clock frequency <= 6.25 MHz; current consumption per converter = 6 mA

#01 : 01

Conversion clock frequency <= 12.5 MHz; current consumption per converter = 10.8 mA

#10 : 10

Conversion clock frequency <= 18.75 MHz; current consumption per converter = 18 mA

#11 : 11

Conversion clock frequency <= 25 MHz; current consumption per converter = 25.2 mA

End of enumeration elements list.

DIV1 : Clock Divisor Select
bits : 8 - 13 (6 bit)
access : read-write


CTRL3

ADC Control Register 3
address_offset : 0xA8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL3 CTRL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCNT0 SCNT1 DMASRC

SCNT0 : Sample Window Count 0
bits : 0 - 2 (3 bit)
access : read-write

SCNT1 : Sample Window Count 1
bits : 3 - 5 (3 bit)
access : read-write

DMASRC : DMA Trigger Source
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA trigger source is end of scan interrupt

#1 : 1

DMA trigger source is RDY bits

End of enumeration elements list.


SCHLTEN

ADC Scan Interrupt Enable Register
address_offset : 0xAA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCHLTEN SCHLTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCHLTEN

SCHLTEN : Scan Interrupt Enable
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

#0 : 0

Scan interrupt is not enabled for this sample.

#1 : 1

Scan interrupt is enabled for this sample.

End of enumeration elements list.


LOLIM1

ADC Low Limit Registers
address_offset : 0xB6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOLIM1 LOLIM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LLMT

LLMT : Low Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


HILIM0

ADC High Limit Registers
address_offset : 0xB8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HILIM0 HILIM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HLMT

HLMT : High Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


RSLT4

ADC Result Registers with sign extension
address_offset : 0xBC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSLT4 RSLT4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSLT SEXT

RSLT : Digital Result of the Conversion
bits : 3 - 14 (12 bit)
access : read-write

SEXT : Sign Extend
bits : 15 - 15 (1 bit)
access : read-only


CLIST3

ADC Channel List Register 3
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLIST3 CLIST3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAMPLE8 SAMPLE9 SAMPLE10 SAMPLE11

SAMPLE8 : Sample Field 8
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1-

#0001 : 0001

Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1-

#0010 : 0010

Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3-

#0011 : 0011

Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3-

#0100 : 0100

Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5-

#0101 : 0101

Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5-

#0110 : 0110

Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7-

#0111 : 0111

Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7-

#1000 : 1000

Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1-

#1001 : 1001

Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1-

#1010 : 1010

Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3-

#1011 : 1011

Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3-

#1100 : 1100

Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5-

#1101 : 1101

Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5-

#1110 : 1110

Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7-

#1111 : 1111

Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7-

End of enumeration elements list.

SAMPLE9 : Sample Field 9
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1-

#0001 : 0001

Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1-

#0010 : 0010

Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3-

#0011 : 0011

Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3-

#0100 : 0100

Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5-

#0101 : 0101

Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5-

#0110 : 0110

Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7-

#0111 : 0111

Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7-

#1000 : 1000

Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1-

#1001 : 1001

Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1-

#1010 : 1010

Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3-

#1011 : 1011

Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3-

#1100 : 1100

Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5-

#1101 : 1101

Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5-

#1110 : 1110

Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7-

#1111 : 1111

Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7-

End of enumeration elements list.

SAMPLE10 : Sample Field 10
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1-

#0001 : 0001

Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1-

#0010 : 0010

Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3-

#0011 : 0011

Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3-

#0100 : 0100

Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5-

#0101 : 0101

Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5-

#0110 : 0110

Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7-

#0111 : 0111

Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7-

#1000 : 1000

Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1-

#1001 : 1001

Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1-

#1010 : 1010

Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3-

#1011 : 1011

Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3-

#1100 : 1100

Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5-

#1101 : 1101

Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5-

#1110 : 1110

Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7-

#1111 : 1111

Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7-

End of enumeration elements list.

SAMPLE11 : Sample Field 11
bits : 12 - 15 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1-

#0001 : 0001

Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1-

#0010 : 0010

Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3-

#0011 : 0011

Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3-

#0100 : 0100

Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5-

#0101 : 0101

Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5-

#0110 : 0110

Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7-

#0111 : 0111

Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7-

#1000 : 1000

Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1-

#1001 : 1001

Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1-

#1010 : 1010

Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3-

#1011 : 1011

Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3-

#1100 : 1100

Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5-

#1101 : 1101

Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5-

#1110 : 1110

Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7-

#1111 : 1111

Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7-

End of enumeration elements list.


CLIST4

ADC Channel List Register 4
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLIST4 CLIST4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAMPLE12 SAMPLE13 SAMPLE14 SAMPLE15

SAMPLE12 : Sample Field 12
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1-

#0001 : 0001

Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1-

#0010 : 0010

Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3-

#0011 : 0011

Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3-

#0100 : 0100

Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5-

#0101 : 0101

Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5-

#0110 : 0110

Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7-

#0111 : 0111

Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7-

#1000 : 1000

Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1-

#1001 : 1001

Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1-

#1010 : 1010

Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3-

#1011 : 1011

Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3-

#1100 : 1100

Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5-

#1101 : 1101

Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5-

#1110 : 1110

Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7-

#1111 : 1111

Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7-

End of enumeration elements list.

SAMPLE13 : Sample Field 13
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1-

#0001 : 0001

Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1-

#0010 : 0010

Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3-

#0011 : 0011

Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3-

#0100 : 0100

Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5-

#0101 : 0101

Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5-

#0110 : 0110

Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7-

#0111 : 0111

Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7-

#1000 : 1000

Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1-

#1001 : 1001

Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1-

#1010 : 1010

Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3-

#1011 : 1011

Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3-

#1100 : 1100

Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5-

#1101 : 1101

Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5-

#1110 : 1110

Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7-

#1111 : 1111

Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7-

End of enumeration elements list.

SAMPLE14 : Sample Field 14
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1-

#0001 : 0001

Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1-

#0010 : 0010

Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3-

#0011 : 0011

Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3-

#0100 : 0100

Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5-

#0101 : 0101

Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5-

#0110 : 0110

Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7-

#0111 : 0111

Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7-

#1000 : 1000

Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1-

#1001 : 1001

Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1-

#1010 : 1010

Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3-

#1011 : 1011

Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3-

#1100 : 1100

Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5-

#1101 : 1101

Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5-

#1110 : 1110

Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7-

#1111 : 1111

Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7-

End of enumeration elements list.

SAMPLE15 : Sample Field 15
bits : 12 - 15 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Single Ended: ADCA_CH0, Differential: ADCA_CH0+, ADCA_CH1-

#0001 : 0001

Single Ended: ADCA_CH1, Differential: ADCA_CH0+, ADCA_CH1-

#0010 : 0010

Single Ended: ADCA_CH2, Differential: ADCA_CH2+, ADCA_CH3-

#0011 : 0011

Single Ended: ADCA_CH3, Differential: ADCA_CH2+, ADCA_CH3-

#0100 : 0100

Single Ended: ADCA_CH4, Differential: ADCA_CH4+, ADCA_CH5-

#0101 : 0101

Single Ended: ADCA_CH5, Differential: ADCA_CH4+, ADCA_CH5-

#0110 : 0110

Single Ended: ADCA_CH6, Differential: ADCA_CH6+, ADCA_CH7-

#0111 : 0111

Single Ended: ADCA_CH7, Differential: ADCA_CH6+, ADCA_CH7-

#1000 : 1000

Single Ended: ADCB_CH0, Differential: ADCB_CH0+, ADCB_CH1-

#1001 : 1001

Single Ended: ADCB_CH1, Differential: ADCB_CH0+, ADCB_CH1-

#1010 : 1010

Single Ended: ADCB_CH2, Differential: ADCB_CH2+, ADCB_CH3-

#1011 : 1011

Single Ended: ADCB_CH3, Differential: ADCB_CH2+, ADCB_CH3-

#1100 : 1100

Single Ended: ADCB_CH4, Differential: ADCB_CH4+, ADCB_CH5-

#1101 : 1101

Single Ended: ADCB_CH5, Differential: ADCB_CH4+, ADCB_CH5-

#1110 : 1110

Single Ended: ADCB_CH6, Differential: ADCB_CH6+, ADCB_CH7-

#1111 : 1111

Single Ended: ADCB_CH7, Differential: ADCB_CH6+, ADCB_CH7-

End of enumeration elements list.


RSLT5

ADC Result Registers with sign extension
address_offset : 0xE2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSLT5 RSLT5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSLT SEXT

RSLT : Digital Result of the Conversion
bits : 3 - 14 (12 bit)
access : read-write

SEXT : Sign Extend
bits : 15 - 15 (1 bit)
access : read-only


LOLIM2

ADC Low Limit Registers
address_offset : 0xF6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOLIM2 LOLIM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LLMT

LLMT : Low Limit Bits
bits : 3 - 14 (12 bit)
access : read-write


OFFST0

ADC Offset Registers
address_offset : 0xF8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFFST0 OFFST0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET

OFFSET : ADC Offset Bits
bits : 3 - 14 (12 bit)
access : read-write



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