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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ISR

CFGR2

SMPR

AWD1TR

AWD2TR

CHSELR

CHSELR_1

AWD3TR

CCR

HWCFGR6

HWCFGR5

HWCFGR4

HWCFGR3

HWCFGR2

HWCFGR1

HWCFGR0

VERR

IPIDR

SIDR

IER

DR

CR

AWD2CR

AWD3CR

CALFACT

CFGR1


ISR

ADC interrupt and status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADRDY EOSMP EOC EOS OVR AWD1 AWD2 AWD3 EOCAL CCRDY

ADRDY : ADC ready flag
bits : 0 - 0 (1 bit)

EOSMP : ADC group regular end of sampling flag
bits : 1 - 1 (1 bit)

EOC : ADC group regular end of unitary conversion flag
bits : 2 - 2 (1 bit)

EOS : ADC group regular end of sequence conversions flag
bits : 3 - 3 (1 bit)

OVR : ADC group regular overrun flag
bits : 4 - 4 (1 bit)

AWD1 : ADC analog watchdog 1 flag
bits : 7 - 7 (1 bit)

AWD2 : ADC analog watchdog 2 flag
bits : 8 - 8 (1 bit)

AWD3 : ADC analog watchdog 3 flag
bits : 9 - 9 (1 bit)

EOCAL : End Of Calibration flag
bits : 11 - 11 (1 bit)

CCRDY : Channel Configuration Ready flag
bits : 13 - 13 (1 bit)


CFGR2

ADC configuration register 2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR2 CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVSE OVSR OVSS TOVS LFTRIG CKMODE

OVSE : ADC oversampler enable on scope ADC group regular
bits : 0 - 0 (1 bit)

OVSR : ADC oversampling ratio
bits : 2 - 4 (3 bit)

OVSS : ADC oversampling shift
bits : 5 - 8 (4 bit)

TOVS : ADC oversampling discontinuous mode (triggered mode) for ADC group regular
bits : 9 - 9 (1 bit)

LFTRIG : Low frequency trigger mode enable
bits : 29 - 29 (1 bit)

CKMODE : ADC clock mode
bits : 30 - 31 (2 bit)


SMPR

ADC sampling time register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMPR SMPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMP1 SMP2 SMPSEL

SMP1 : Sampling time selection
bits : 0 - 2 (3 bit)

SMP2 : Sampling time selection
bits : 4 - 6 (3 bit)

SMPSEL : Channel sampling time selection
bits : 8 - 26 (19 bit)


AWD1TR

watchdog threshold register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AWD1TR AWD1TR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LT1 HT1

LT1 : ADC analog watchdog 1 threshold low
bits : 0 - 11 (12 bit)

HT1 : ADC analog watchdog 1 threshold high
bits : 16 - 27 (12 bit)


AWD2TR

watchdog threshold register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AWD2TR AWD2TR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LT2 HT2

LT2 : ADC analog watchdog 2 threshold low
bits : 0 - 11 (12 bit)

HT2 : ADC analog watchdog 2 threshold high
bits : 16 - 27 (12 bit)


CHSELR

channel selection register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSELR CHSELR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHSEL

CHSEL : Channel-x selection
bits : 0 - 18 (19 bit)


CHSELR_1

channel selection register CHSELRMOD = 1 in ADC_CFGR1
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CHSELR
reset_Mask : 0x0

CHSELR_1 CHSELR_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQ1 SQ2 SQ3 SQ4 SQ5 SQ6 SQ7 SQ8

SQ1 : conversion of the sequence
bits : 0 - 3 (4 bit)

SQ2 : conversion of the sequence
bits : 4 - 7 (4 bit)

SQ3 : conversion of the sequence
bits : 8 - 11 (4 bit)

SQ4 : conversion of the sequence
bits : 12 - 15 (4 bit)

SQ5 : conversion of the sequence
bits : 16 - 19 (4 bit)

SQ6 : conversion of the sequence
bits : 20 - 23 (4 bit)

SQ7 : conversion of the sequence
bits : 24 - 27 (4 bit)

SQ8 : conversion of the sequence
bits : 28 - 31 (4 bit)


AWD3TR

watchdog threshold register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AWD3TR AWD3TR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LT3 HT3

LT3 : ADC analog watchdog 3 threshold high
bits : 0 - 11 (12 bit)

HT3 : ADC analog watchdog 3 threshold high
bits : 16 - 27 (12 bit)


CCR

ADC common control register
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRESC VREFEN TSEN VBATEN

PRESC : ADC prescaler
bits : 18 - 21 (4 bit)

VREFEN : VREFINT enable
bits : 22 - 22 (1 bit)

TSEN : Temperature sensor enable
bits : 23 - 23 (1 bit)

VBATEN : VBAT enable
bits : 24 - 24 (1 bit)


HWCFGR6

Hardware Configuration Register
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HWCFGR6 HWCFGR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHMAP20 CHMAP21 CHMAP22 CHMAP23

CHMAP20 : Input channel mapping
bits : 0 - 4 (5 bit)

CHMAP21 : Input channel mapping
bits : 8 - 12 (5 bit)

CHMAP22 : Input channel mapping
bits : 16 - 20 (5 bit)

CHMAP23 : Input channel mapping
bits : 24 - 28 (5 bit)


HWCFGR5

Hardware Configuration Register
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HWCFGR5 HWCFGR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHMAP19 CHMAP18 CHMAP17 CHMAP16

CHMAP19 : Input channel mapping
bits : 0 - 4 (5 bit)

CHMAP18 : Input channel mapping
bits : 8 - 12 (5 bit)

CHMAP17 : Input channel mapping
bits : 16 - 20 (5 bit)

CHMAP16 : Input channel mapping
bits : 24 - 28 (5 bit)


HWCFGR4

Hardware Configuration Register
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HWCFGR4 HWCFGR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHMAP15 CHMAP14 CHMAP13 CHMAP12

CHMAP15 : Input channel mapping
bits : 0 - 4 (5 bit)

CHMAP14 : Input channel mapping
bits : 8 - 12 (5 bit)

CHMAP13 : Input channel mapping
bits : 16 - 20 (5 bit)

CHMAP12 : Input channel mapping
bits : 24 - 28 (5 bit)


HWCFGR3

Hardware Configuration Register
address_offset : 0x3E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HWCFGR3 HWCFGR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHMAP11 CHMAP10 CHMAP9 CHMAP8

CHMAP11 : Input channel mapping
bits : 0 - 4 (5 bit)

CHMAP10 : Input channel mapping
bits : 8 - 12 (5 bit)

CHMAP9 : Input channel mapping
bits : 16 - 20 (5 bit)

CHMAP8 : Input channel mapping
bits : 24 - 28 (5 bit)


HWCFGR2

Hardware Configuration Register
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HWCFGR2 HWCFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHMAP7 CHMAP6 CHMAP5 CHMAP4

CHMAP7 : Input channel mapping
bits : 0 - 4 (5 bit)

CHMAP6 : Input channel mapping
bits : 8 - 12 (5 bit)

CHMAP5 : Input channel mapping
bits : 16 - 20 (5 bit)

CHMAP4 : Input channel mapping
bits : 24 - 28 (5 bit)


HWCFGR1

Hardware Configuration Register
address_offset : 0x3EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HWCFGR1 HWCFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHMAP3 CHMAP2 CHMAP1 CHMAP0

CHMAP3 : Input channel mapping
bits : 0 - 4 (5 bit)

CHMAP2 : Input channel mapping
bits : 8 - 12 (5 bit)

CHMAP1 : Input channel mapping
bits : 16 - 20 (5 bit)

CHMAP0 : Input channel mapping
bits : 24 - 28 (5 bit)


HWCFGR0

Hardware Configuration Register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HWCFGR0 HWCFGR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NUM_CHAN_24 EXTRA_AWDS OVS

NUM_CHAN_24 : NUM_CHAN_24
bits : 0 - 3 (4 bit)

EXTRA_AWDS : Extra analog watchdog
bits : 4 - 7 (4 bit)

OVS : Oversampling
bits : 8 - 11 (4 bit)


VERR

EXTI IP Version register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VERR VERR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MINREV MAJREV

MINREV : Minor Revision number
bits : 0 - 3 (4 bit)

MAJREV : Major Revision number
bits : 4 - 7 (4 bit)


IPIDR

EXTI Identification register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPIDR IPIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPID

IPID : IP Identification
bits : 0 - 31 (32 bit)


SIDR

EXTI Size ID register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SIDR SIDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SID

SID : Size Identification
bits : 0 - 31 (32 bit)


IER

ADC interrupt enable register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADRDYIE EOSMPIE EOCIE EOSIE OVRIE AWD1IE AWD2IE AWD3IE EOCALIE CCRDYIE

ADRDYIE : ADC ready interrupt
bits : 0 - 0 (1 bit)

EOSMPIE : ADC group regular end of sampling interrupt
bits : 1 - 1 (1 bit)

EOCIE : ADC group regular end of unitary conversion interrupt
bits : 2 - 2 (1 bit)

EOSIE : ADC group regular end of sequence conversions interrupt
bits : 3 - 3 (1 bit)

OVRIE : ADC group regular overrun interrupt
bits : 4 - 4 (1 bit)

AWD1IE : ADC analog watchdog 1 interrupt
bits : 7 - 7 (1 bit)

AWD2IE : ADC analog watchdog 2 interrupt
bits : 8 - 8 (1 bit)

AWD3IE : ADC analog watchdog 3 interrupt
bits : 9 - 9 (1 bit)

EOCALIE : End of calibration interrupt enable
bits : 11 - 11 (1 bit)

CCRDYIE : Channel Configuration Ready Interrupt enable
bits : 13 - 13 (1 bit)


DR

ADC group regular conversion data register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DR DR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 regularDATA

regularDATA : ADC group regular conversion data
bits : 0 - 15 (16 bit)


CR

ADC control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADEN ADDIS ADSTART ADSTP ADVREGEN ADCAL

ADEN : ADC enable
bits : 0 - 0 (1 bit)

ADDIS : ADC disable
bits : 1 - 1 (1 bit)

ADSTART : ADC group regular conversion start
bits : 2 - 2 (1 bit)

ADSTP : ADC group regular conversion stop
bits : 4 - 4 (1 bit)

ADVREGEN : ADC voltage regulator enable
bits : 28 - 28 (1 bit)

ADCAL : ADC calibration
bits : 31 - 31 (1 bit)


AWD2CR

ADC analog watchdog 2 configuration register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AWD2CR AWD2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWD2CH

AWD2CH : ADC analog watchdog 2 monitored channel selection
bits : 0 - 18 (19 bit)


AWD3CR

ADC analog watchdog 3 configuration register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AWD3CR AWD3CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWD3CH

AWD3CH : ADC analog watchdog 3 monitored channel selection
bits : 0 - 18 (19 bit)


CALFACT

ADC calibration factors register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CALFACT CALFACT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALFACT

CALFACT : ADC calibration factor in single-ended mode
bits : 0 - 6 (7 bit)


CFGR1

ADC configuration register 1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR1 CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAEN DMACFG SCANDIR RES ALIGN EXTSEL EXTEN OVRMOD CONT WAIT AUTOFF DISCEN CHSELRMOD AWD1SGL AWD1EN AWDCH1CH

DMAEN : ADC DMA transfer enable
bits : 0 - 0 (1 bit)

DMACFG : ADC DMA transfer configuration
bits : 1 - 1 (1 bit)

SCANDIR : Scan sequence direction
bits : 2 - 2 (1 bit)

RES : ADC data resolution
bits : 3 - 4 (2 bit)

ALIGN : ADC data alignement
bits : 5 - 5 (1 bit)

EXTSEL : ADC group regular external trigger source
bits : 6 - 8 (3 bit)

EXTEN : ADC group regular external trigger polarity
bits : 10 - 11 (2 bit)

OVRMOD : ADC group regular overrun configuration
bits : 12 - 12 (1 bit)

CONT : ADC group regular continuous conversion mode
bits : 13 - 13 (1 bit)

WAIT : Wait conversion mode
bits : 14 - 14 (1 bit)

AUTOFF : Auto-off mode
bits : 15 - 15 (1 bit)

DISCEN : ADC group regular sequencer discontinuous mode
bits : 16 - 16 (1 bit)

CHSELRMOD : Mode selection of the ADC_CHSELR register
bits : 21 - 21 (1 bit)

AWD1SGL : ADC analog watchdog 1 monitoring a single channel or all channels
bits : 22 - 22 (1 bit)

AWD1EN : ADC analog watchdog 1 enable on scope ADC group regular
bits : 23 - 23 (1 bit)

AWDCH1CH : ADC analog watchdog 1 monitored channel selection
bits : 26 - 30 (5 bit)



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