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UCPD

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CFG1

IMR

SR

ICR

TX_ORDSET

TX_PAYSZ

TXDR

RX_ORDSET

RX_PAYSZ

RXDR

RX_ORDEXT1

RX_ORDEXT2

IPVER

IPID

MID

CFG2

CFG3

CR


CFG1

UCPD configuration register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG1 CFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HBITCLKDIV IFRGAP TRANSWIN PSC_USBPDCLK RXORDSETEN TXDMAEN RXDMAEN UCPDEN

HBITCLKDIV : HBITCLKDIV
bits : 0 - 5 (6 bit)

IFRGAP : IFRGAP
bits : 6 - 10 (5 bit)

TRANSWIN : TRANSWIN
bits : 11 - 15 (5 bit)

PSC_USBPDCLK : PSC_USBPDCLK
bits : 17 - 19 (3 bit)

RXORDSETEN : RXORDSETEN
bits : 20 - 28 (9 bit)

TXDMAEN : TXDMAEN
bits : 29 - 29 (1 bit)

RXDMAEN : RXDMAEN:
bits : 30 - 30 (1 bit)

UCPDEN : UCPDEN
bits : 31 - 31 (1 bit)


IMR

UCPD Interrupt Mask Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXISIE TXMSGDISCIE TXMSGSENTIE TXMSGABTIE HRSTDISCIE HRSTSENTIE TXUNDIE RXNEIE RXORDDETIE RXHRSTDETIE RXOVRIE RXMSGENDIE TYPECEVT1IE TYPECEVT2IE FRSEVTIE

TXISIE : TXISIE
bits : 0 - 0 (1 bit)

TXMSGDISCIE : TXMSGDISCIE
bits : 1 - 1 (1 bit)

TXMSGSENTIE : TXMSGSENTIE
bits : 2 - 2 (1 bit)

TXMSGABTIE : TXMSGABTIE
bits : 3 - 3 (1 bit)

HRSTDISCIE : HRSTDISCIE
bits : 4 - 4 (1 bit)

HRSTSENTIE : HRSTSENTIE
bits : 5 - 5 (1 bit)

TXUNDIE : TXUNDIE
bits : 6 - 6 (1 bit)

RXNEIE : RXNEIE
bits : 8 - 8 (1 bit)

RXORDDETIE : RXORDDETIE
bits : 9 - 9 (1 bit)

RXHRSTDETIE : RXHRSTDETIE
bits : 10 - 10 (1 bit)

RXOVRIE : RXOVRIE
bits : 11 - 11 (1 bit)

RXMSGENDIE : RXMSGENDIE
bits : 12 - 12 (1 bit)

TYPECEVT1IE : TYPECEVT1IE
bits : 14 - 14 (1 bit)

TYPECEVT2IE : TYPECEVT2IE
bits : 15 - 15 (1 bit)

FRSEVTIE : FRSEVTIE
bits : 20 - 20 (1 bit)


SR

UCPD Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXIS TXMSGDISC TXMSGSENT TXMSGABT HRSTDISC HRSTSENT TXUND RXNE RXORDDET RXHRSTDET RXOVR RXMSGEND RXERR TYPECEVT1 TYPECEVT2 TYPEC_VSTATE_CC1 TYPEC_VSTATE_CC2 FRSEVT

TXIS : TXIS
bits : 0 - 0 (1 bit)

TXMSGDISC : TXMSGDISC
bits : 1 - 1 (1 bit)

TXMSGSENT : TXMSGSENT
bits : 2 - 2 (1 bit)

TXMSGABT : TXMSGABT
bits : 3 - 3 (1 bit)

HRSTDISC : HRSTDISC
bits : 4 - 4 (1 bit)

HRSTSENT : HRSTSENT
bits : 5 - 5 (1 bit)

TXUND : TXUND
bits : 6 - 6 (1 bit)

RXNE : RXNE
bits : 8 - 8 (1 bit)

RXORDDET : RXORDDET
bits : 9 - 9 (1 bit)

RXHRSTDET : RXHRSTDET
bits : 10 - 10 (1 bit)

RXOVR : RXOVR
bits : 11 - 11 (1 bit)

RXMSGEND : RXMSGEND
bits : 12 - 12 (1 bit)

RXERR : RXERR
bits : 13 - 13 (1 bit)

TYPECEVT1 : TYPECEVT1
bits : 14 - 14 (1 bit)

TYPECEVT2 : TYPECEVT2
bits : 15 - 15 (1 bit)

TYPEC_VSTATE_CC1 : TYPEC_VSTATE_CC1
bits : 16 - 17 (2 bit)

TYPEC_VSTATE_CC2 : TYPEC_VSTATE_CC2
bits : 18 - 19 (2 bit)

FRSEVT : FRSEVT
bits : 20 - 20 (1 bit)


ICR

UCPD Interrupt Clear Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICR ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXMSGDISCCF TXMSGSENTCF TXMSGABTCF HRSTDISCCF HRSTSENTCF TXUNDCF RXORDDETCF RXHRSTDETCF RXOVRCF RXMSGENDCF TYPECEVT1CF TYPECEVT2CF FRSEVTCF

TXMSGDISCCF : TXMSGDISCCF
bits : 1 - 1 (1 bit)

TXMSGSENTCF : TXMSGSENTCF
bits : 2 - 2 (1 bit)

TXMSGABTCF : TXMSGABTCF
bits : 3 - 3 (1 bit)

HRSTDISCCF : HRSTDISCCF
bits : 4 - 4 (1 bit)

HRSTSENTCF : HRSTSENTCF
bits : 5 - 5 (1 bit)

TXUNDCF : TXUNDCF
bits : 6 - 6 (1 bit)

RXORDDETCF : RXORDDETCF
bits : 9 - 9 (1 bit)

RXHRSTDETCF : RXHRSTDETCF
bits : 10 - 10 (1 bit)

RXOVRCF : RXOVRCF
bits : 11 - 11 (1 bit)

RXMSGENDCF : RXMSGENDCF
bits : 12 - 12 (1 bit)

TYPECEVT1CF : TYPECEVT1CF
bits : 14 - 14 (1 bit)

TYPECEVT2CF : TYPECEVT2CF
bits : 15 - 15 (1 bit)

FRSEVTCF : FRSEVTCF
bits : 20 - 20 (1 bit)


TX_ORDSET

UCPD Tx Ordered Set Type Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_ORDSET TX_ORDSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXORDSET

TXORDSET : TXORDSET
bits : 0 - 19 (20 bit)


TX_PAYSZ

UCPD Tx Paysize Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_PAYSZ TX_PAYSZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXPAYSZ

TXPAYSZ : TXPAYSZ
bits : 0 - 9 (10 bit)


TXDR

UCPD Tx Data Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXDR TXDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA

TXDATA : TXDATA
bits : 0 - 7 (8 bit)


RX_ORDSET

UCPD Rx Ordered Set Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RX_ORDSET RX_ORDSET read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXORDSET RXSOP3OF4 RXSOPKINVALID

RXORDSET : RXORDSET
bits : 0 - 2 (3 bit)

RXSOP3OF4 : RXSOP3OF4
bits : 3 - 3 (1 bit)

RXSOPKINVALID : RXSOPKINVALID
bits : 4 - 6 (3 bit)


RX_PAYSZ

UCPD Rx Paysize Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX_PAYSZ RX_PAYSZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXPAYSZ

RXPAYSZ : RXPAYSZ
bits : 0 - 9 (10 bit)


RXDR

UCPD Receive Data Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDR RXDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA

RXDATA : RXDATA
bits : 0 - 7 (8 bit)


RX_ORDEXT1

UCPD Rx Ordered Set Extension Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX_ORDEXT1 RX_ORDEXT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXSOPX1

RXSOPX1 : RXSOPX1
bits : 0 - 19 (20 bit)


RX_ORDEXT2

UCPD Rx Ordered Set Extension Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX_ORDEXT2 RX_ORDEXT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXSOPX2

RXSOPX2 : RXSOPX2
bits : 0 - 19 (20 bit)


IPVER

UCPD IP ID register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPVER IPVER read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPVER

IPVER : IPVER
bits : 0 - 31 (32 bit)


IPID

UCPD IP ID register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPID IPID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPID

IPID : IPID
bits : 0 - 31 (32 bit)


MID

UCPD IP ID register
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MID MID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPID

IPID : IPID
bits : 0 - 31 (32 bit)


CFG2

UCPD configuration register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG2 CFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXFILTDIS RXFILT2N3 FORCECLK WUPEN

RXFILTDIS : RXFILTDIS
bits : 0 - 0 (1 bit)

RXFILT2N3 : RXFILT2N3
bits : 1 - 1 (1 bit)

FORCECLK : FORCECLK
bits : 2 - 2 (1 bit)

WUPEN : WUPEN
bits : 3 - 3 (1 bit)


CFG3

UCPD configuration register 3
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG3 CFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIM1_NG_CCRPD TRIM1_NG_CC1A5 TRIM1_NG_CC3A0 TRIM2_NG_CCRPD TRIM2_NG_CC1A5 TRIM2_NG_CC3A0

TRIM1_NG_CCRPD : TRIM1_NG_CCRPD
bits : 0 - 3 (4 bit)

TRIM1_NG_CC1A5 : TRIM1_NG_CC1A5
bits : 4 - 8 (5 bit)

TRIM1_NG_CC3A0 : TRIM1_NG_CC3A0
bits : 9 - 12 (4 bit)

TRIM2_NG_CCRPD : TRIM2_NG_CCRPD
bits : 16 - 19 (4 bit)

TRIM2_NG_CC1A5 : TRIM2_NG_CC1A5
bits : 20 - 24 (5 bit)

TRIM2_NG_CC3A0 : TRIM2_NG_CC3A0
bits : 25 - 28 (4 bit)


CR

UCPD control register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXMODE TXSEND TXHRST RXMODE PHYRXEN PHYCCSEL ANASUBMODE ANAMODE CCENABLE DBATTEN FRSRXEN FRSTX RDCH CC1TCDIS CC2TCDIS

TXMODE : TXMODE
bits : 0 - 1 (2 bit)

TXSEND : TXSEND
bits : 2 - 2 (1 bit)

TXHRST : TXHRST
bits : 3 - 3 (1 bit)

RXMODE : RXMODE
bits : 4 - 4 (1 bit)

PHYRXEN : PHYRXEN
bits : 5 - 5 (1 bit)

PHYCCSEL : PHYCCSEL
bits : 6 - 6 (1 bit)

ANASUBMODE : ANASUBMODE
bits : 7 - 8 (2 bit)

ANAMODE : ANAMODE
bits : 9 - 9 (1 bit)

CCENABLE : CCENABLE
bits : 10 - 11 (2 bit)

DBATTEN : DBATTEN
bits : 15 - 15 (1 bit)

FRSRXEN : FRSRXEN
bits : 16 - 16 (1 bit)

FRSTX : FRSTX
bits : 17 - 17 (1 bit)

RDCH : RDCH
bits : 18 - 18 (1 bit)

CC1TCDIS : CC1TCDIS
bits : 20 - 20 (1 bit)

CC2TCDIS : CC2TCDIS
bits : 21 - 21 (1 bit)



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