\n
address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPIE : Compare Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare interrupt is disabled
#1 : 1
Compare interrupt is enabled
End of enumeration elements list.
CMPIRQ : Compare Interrupt Request
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No match has occurred
#1 : 1
COMP match has occurred
End of enumeration elements list.
WDE : Watchdog Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Watchdog timer is disabled
#1 : 1
Watchdog timer is enabled
End of enumeration elements list.
DIE : Watchdog Timeout Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Watchdog timer interrupt is disabled
#1 : 1
Watchdog timer interrupt is enabled
End of enumeration elements list.
DIRQ : Watchdog Timeout Interrupt Request
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt has occurred
#1 : 1
Watchdog timeout interrupt has occurred
End of enumeration elements list.
XNE : Use Negative Edge of INDEX Pulse
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Use positive transition edge of INDEX pulse
#1 : 1
Use negative transition edge of INDEX pulse
End of enumeration elements list.
XIP : INDEX Triggered Initialization of Position Counters UPOS and LPOS
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action
#1 : 1
INDEX pulse initializes the position counter
End of enumeration elements list.
XIE : INDEX Pulse Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
INDEX pulse interrupt is disabled
#1 : 1
INDEX pulse interrupt is enabled
End of enumeration elements list.
XIRQ : INDEX Pulse Interrupt Request
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt has occurred
#1 : 1
INDEX pulse interrupt has occurred
End of enumeration elements list.
PH1 : Enable Signal Phase Count Mode
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Use standard quadrature decoder where PHASEA and PHASEB represent a two phase quadrature signal.
#1 : 1
Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The PHASEB input and the REV bit control the counter direction. If CTRL[REV] = 0, PHASEB = 0, then count up If CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1, PHASEB = 0, then count down If CTRL[REV] = 1, PHASEB = 1, then count up
End of enumeration elements list.
REV : Enable Reverse Direction Counting
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Count normally
#1 : 1
Count in the reverse direction
End of enumeration elements list.
SWIP : Software Triggered Initialization of Position Counters UPOS and LPOS
bits : 11 - 11 (1 bit)
access : write-only
Enumeration:
#0 : 0
No action
#1 : 1
Initialize position counter
End of enumeration elements list.
HNE : Use Negative Edge of HOME Input
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Use positive going edge-to-trigger initialization of position counters UPOS and LPOS
#1 : 1
Use negative going edge-to-trigger initialization of position counters UPOS and LPOS
End of enumeration elements list.
HIP : Enable HOME to Initialize Position Counters UPOS and LPOS
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action
#1 : 1
HOME signal initializes the position counter
End of enumeration elements list.
HIE : HOME Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable HOME interrupts
#1 : 1
Enable HOME interrupts
End of enumeration elements list.
HIRQ : HOME Signal Transition Interrupt Request
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt
#1 : 1
HOME signal transition interrupt request
End of enumeration elements list.
Lower Position Counter Register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POS : no description available
bits : 0 - 15 (16 bit)
access : read-write
Upper Position Hold Register
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
POSH : no description available
bits : 0 - 15 (16 bit)
access : read-only
Lower Position Hold Register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
POSH : no description available
bits : 0 - 15 (16 bit)
access : read-only
Upper Initialization Register
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT : no description available
bits : 0 - 15 (16 bit)
access : read-write
Lower Initialization Register
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT : no description available
bits : 0 - 15 (16 bit)
access : read-write
Input Monitor Register
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HOME : no description available
bits : 0 - 0 (1 bit)
access : read-only
INDEX : no description available
bits : 1 - 1 (1 bit)
access : read-only
PHB : no description available
bits : 2 - 2 (1 bit)
access : read-only
PHA : no description available
bits : 3 - 3 (1 bit)
access : read-only
FHOM : no description available
bits : 4 - 4 (1 bit)
access : read-only
FIND : no description available
bits : 5 - 5 (1 bit)
access : read-only
FPHB : no description available
bits : 6 - 6 (1 bit)
access : read-only
FPHA : no description available
bits : 7 - 7 (1 bit)
access : read-only
Test Register
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEST_COUNT : no description available
bits : 0 - 7 (8 bit)
access : read-write
TEST_PERIOD : no description available
bits : 8 - 12 (5 bit)
access : read-write
QDN : Quadrature Decoder Negative Signal
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Leaves quadrature decoder signal in a positive direction
#1 : 1
Generates a negative quadrature decoder signal
End of enumeration elements list.
TCE : Test Counter Enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Test count is not enabled
#1 : 1
Test count is enabled
End of enumeration elements list.
TEN : Test Mode Enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Test module is not enabled
#1 : 1
Test module is enabled
End of enumeration elements list.
Control 2 Register
address_offset : 0x1E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPDHLD : Update Hold Registers
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable updates of hold registers on rising edge of TRIGGER
#1 : 1
Enable updates of hold registers on rising edge of TRIGGER
End of enumeration elements list.
UPDPOS : Update Position Registers
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action for POSD, REV, UPOS and LPOS on rising edge of TRIGGER
#1 : 1
Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER
End of enumeration elements list.
MOD : Enable Modulo Counting
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable modulo counting
#1 : 1
Enable modulo counting
End of enumeration elements list.
DIR : Count Direction Flag
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
Last count was in the down direction
#1 : 1
Last count was in the up direction
End of enumeration elements list.
RUIE : Roll-under Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Roll-under interrupt is disabled
#1 : 1
Roll-under interrupt is enabled
End of enumeration elements list.
RUIRQ : Roll-under Interrupt Request
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No roll-under has occurred
#1 : 1
Roll-under has occurred
End of enumeration elements list.
ROIE : Roll-over Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Roll-over interrupt is disabled
#1 : 1
Roll-over interrupt is enabled
End of enumeration elements list.
ROIRQ : Roll-over Interrupt Request
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No roll-over has occurred
#1 : 1
Roll-over has occurred
End of enumeration elements list.
REVMOD : Revolution Counter Modulus Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Use INDEX pulse to increment/decrement revolution counter (REV).
#1 : 1
Use modulus counting roll-over/under to increment/decrement revolution counter (REV).
End of enumeration elements list.
OUTCTL : Output Control
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
POSMATCH pulses when a match occurs between the position counters (POS) and the compare value (COMP).
#1 : 1
POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read.
End of enumeration elements list.
SABIE : Simultaneous PHASEA and PHASEB Change Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Simultaneous PHASEA and PHASEB change interrupt disabled.
#1 : 1
Simultaneous PHASEA and PHASEB change interrupt enabled.
End of enumeration elements list.
SABIRQ : Simultaneous PHASEA and PHASEB Change Interrupt Request
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
No simultaneous change of PHASEA and PHASEB has occurred.
#1 : 1
A simultaneous change of PHASEA and PHASEB has occurred.
End of enumeration elements list.
Input Filter Register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILT_PER : Input Filter Sample Period
bits : 0 - 7 (8 bit)
access : read-write
FILT_CNT : Input Filter Sample Count
bits : 8 - 10 (3 bit)
access : read-write
Upper Modulus Register
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD : no description available
bits : 0 - 15 (16 bit)
access : read-write
Lower Modulus Register
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD : no description available
bits : 0 - 15 (16 bit)
access : read-write
Upper Position Compare Register
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP : no description available
bits : 0 - 15 (16 bit)
access : read-write
Lower Position Compare Register
address_offset : 0x26 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP : no description available
bits : 0 - 15 (16 bit)
access : read-write
Watchdog Timeout Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDOG : no description available
bits : 0 - 15 (16 bit)
access : read-write
Position Difference Counter Register
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSD : no description available
bits : 0 - 15 (16 bit)
access : read-write
Position Difference Hold Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
POSDH : no description available
bits : 0 - 15 (16 bit)
access : read-only
Revolution Counter Register
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REV : no description available
bits : 0 - 15 (16 bit)
access : read-write
Revolution Hold Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REVH : no description available
bits : 0 - 15 (16 bit)
access : read-only
Upper Position Counter Register
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POS : no description available
bits : 0 - 15 (16 bit)
access : read-write
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