\n
address_offset : 0x0 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection : not protected
Crossbar A Select Register 0
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : no description available
bits : 0 - 5 (6 bit)
access : read-write
SEL1 : no description available
bits : 8 - 13 (6 bit)
access : read-write
Crossbar A Select Register 8
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL16 : no description available
bits : 0 - 5 (6 bit)
access : read-write
SEL17 : no description available
bits : 8 - 13 (6 bit)
access : read-write
Crossbar A Select Register 9
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL18 : no description available
bits : 0 - 5 (6 bit)
access : read-write
SEL19 : no description available
bits : 8 - 13 (6 bit)
access : read-write
Crossbar A Select Register 10
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL20 : no description available
bits : 0 - 5 (6 bit)
access : read-write
SEL21 : no description available
bits : 8 - 13 (6 bit)
access : read-write
Crossbar A Select Register 11
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL22 : no description available
bits : 0 - 5 (6 bit)
access : read-write
SEL23 : no description available
bits : 8 - 13 (6 bit)
access : read-write
Crossbar A Select Register 12
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL24 : no description available
bits : 0 - 5 (6 bit)
access : read-write
SEL25 : no description available
bits : 8 - 13 (6 bit)
access : read-write
Crossbar A Select Register 13
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL26 : no description available
bits : 0 - 5 (6 bit)
access : read-write
SEL27 : no description available
bits : 8 - 13 (6 bit)
access : read-write
Crossbar A Select Register 14
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL28 : no description available
bits : 0 - 5 (6 bit)
access : read-write
SEL29 : no description available
bits : 8 - 13 (6 bit)
access : read-write
Crossbar A Select Register 15
address_offset : 0x1E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL30 : no description available
bits : 0 - 5 (6 bit)
access : read-write
SEL31 : no description available
bits : 8 - 13 (6 bit)
access : read-write
Crossbar A Select Register 1
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL2 : no description available
bits : 0 - 5 (6 bit)
access : read-write
SEL3 : no description available
bits : 8 - 13 (6 bit)
access : read-write
Crossbar A Select Register 16
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL32 : no description available
bits : 0 - 5 (6 bit)
access : read-write
SEL33 : no description available
bits : 8 - 13 (6 bit)
access : read-write
Crossbar A Select Register 17
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL34 : no description available
bits : 0 - 5 (6 bit)
access : read-write
SEL35 : no description available
bits : 8 - 13 (6 bit)
access : read-write
Crossbar A Select Register 18
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL36 : no description available
bits : 0 - 5 (6 bit)
access : read-write
SEL37 : no description available
bits : 8 - 13 (6 bit)
access : read-write
Crossbar A Select Register 19
address_offset : 0x26 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL38 : no description available
bits : 0 - 5 (6 bit)
access : read-write
SEL39 : no description available
bits : 8 - 13 (6 bit)
access : read-write
Crossbar A Select Register 20
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL40 : no description available
bits : 0 - 5 (6 bit)
access : read-write
SEL41 : no description available
bits : 8 - 13 (6 bit)
access : read-write
Crossbar A Select Register 21
address_offset : 0x2A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL42 : no description available
bits : 0 - 5 (6 bit)
access : read-write
SEL43 : no description available
bits : 8 - 13 (6 bit)
access : read-write
Crossbar A Select Register 22
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL44 : no description available
bits : 0 - 5 (6 bit)
access : read-write
SEL45 : no description available
bits : 8 - 13 (6 bit)
access : read-write
Crossbar A Select Register 23
address_offset : 0x2E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL46 : no description available
bits : 0 - 5 (6 bit)
access : read-write
SEL47 : no description available
bits : 8 - 13 (6 bit)
access : read-write
Crossbar A Select Register 24
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL48 : no description available
bits : 0 - 5 (6 bit)
access : read-write
SEL49 : no description available
bits : 8 - 13 (6 bit)
access : read-write
Crossbar A Select Register 25
address_offset : 0x32 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL50 : no description available
bits : 0 - 5 (6 bit)
access : read-write
SEL51 : no description available
bits : 8 - 13 (6 bit)
access : read-write
Crossbar A Select Register 26
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL52 : no description available
bits : 0 - 5 (6 bit)
access : read-write
SEL53 : no description available
bits : 8 - 13 (6 bit)
access : read-write
Crossbar A Select Register 27
address_offset : 0x36 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL54 : no description available
bits : 0 - 5 (6 bit)
access : read-write
SEL55 : no description available
bits : 8 - 13 (6 bit)
access : read-write
Crossbar A Select Register 28
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL56 : no description available
bits : 0 - 5 (6 bit)
access : read-write
SEL57 : no description available
bits : 8 - 13 (6 bit)
access : read-write
Crossbar A Select Register 29
address_offset : 0x3A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL58 : no description available
bits : 0 - 5 (6 bit)
access : read-write
Crossbar A Control Register 0
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEN0 : DMA Enable for XBAR_OUT0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA disabled
#1 : 1
DMA enabled
End of enumeration elements list.
IEN0 : Interrupt Enable for XBAR_OUT0
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt disabled
#1 : 1
Interrupt enabled
End of enumeration elements list.
EDGE0 : Active edge for edge detection on XBAR_OUT0
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
STS0 never asserts
#01 : 01
STS0 asserts on rising edges of XBAR_OUT0
#10 : 10
STS0 asserts on falling edges of XBAR_OUT0
#11 : 11
STS0 asserts on rising and falling edges of XBAR_OUT0
End of enumeration elements list.
STS0 : Edge detection status for XBAR_OUT0
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Active edge not yet detected on XBAR_OUT0
#1 : 1
Active edge detected on XBAR_OUT0
End of enumeration elements list.
DEN1 : DMA Enable for XBAR_OUT1
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA disabled
#1 : 1
DMA enabled
End of enumeration elements list.
IEN1 : Interrupt Enable for XBAR_OUT1
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt disabled
#1 : 1
Interrupt enabled
End of enumeration elements list.
EDGE1 : Active edge for edge detection on XBAR_OUT1
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 00
STS1 never asserts
#01 : 01
STS1 asserts on rising edges of XBAR_OUT1
#10 : 10
STS1 asserts on falling edges of XBAR_OUT1
#11 : 11
STS1 asserts on rising and falling edges of XBAR_OUT1
End of enumeration elements list.
STS1 : Edge detection status for XBAR_OUT1
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Active edge not yet detected on XBAR_OUT1
#1 : 1
Active edge detected on XBAR_OUT1
End of enumeration elements list.
Crossbar A Control Register 1
address_offset : 0x3E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEN2 : DMA Enable for XBAR_OUT2
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA disabled
#1 : 1
DMA enabled
End of enumeration elements list.
IEN2 : Interrupt Enable for XBAR_OUT2
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt disabled
#1 : 1
Interrupt enabled
End of enumeration elements list.
EDGE2 : Active edge for edge detection on XBAR_OUT2
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
STS2 never asserts
#01 : 01
STS2 asserts on rising edges of XBAR_OUT2
#10 : 10
STS2 asserts on falling edges of XBAR_OUT2
#11 : 11
STS2 asserts on rising and falling edges of XBAR_OUT2
End of enumeration elements list.
STS2 : Edge detection status for XBAR_OUT2
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Active edge not yet detected on XBAR_OUT2
#1 : 1
Active edge detected on XBAR_OUT2
End of enumeration elements list.
DEN3 : DMA Enable for XBAR_OUT3
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA disabled
#1 : 1
DMA enabled
End of enumeration elements list.
IEN3 : Interrupt Enable for XBAR_OUT3
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt disabled
#1 : 1
Interrupt enabled
End of enumeration elements list.
EDGE3 : Active edge for edge detection on XBAR_OUT3
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 00
STS3 never asserts
#01 : 01
STS3 asserts on rising edges of XBAR_OUT3
#10 : 10
STS3 asserts on falling edges of XBAR_OUT3
#11 : 11
STS3 asserts on rising and falling edges of XBAR_OUT3
End of enumeration elements list.
STS3 : Edge detection status for XBAR_OUT3
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Active edge not yet detected on XBAR_OUT3
#1 : 1
Active edge detected on XBAR_OUT3
End of enumeration elements list.
Crossbar A Select Register 2
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL4 : no description available
bits : 0 - 5 (6 bit)
access : read-write
SEL5 : no description available
bits : 8 - 13 (6 bit)
access : read-write
Crossbar A Select Register 3
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL6 : no description available
bits : 0 - 5 (6 bit)
access : read-write
SEL7 : no description available
bits : 8 - 13 (6 bit)
access : read-write
Crossbar A Select Register 4
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL8 : no description available
bits : 0 - 5 (6 bit)
access : read-write
SEL9 : no description available
bits : 8 - 13 (6 bit)
access : read-write
Crossbar A Select Register 5
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL10 : no description available
bits : 0 - 5 (6 bit)
access : read-write
SEL11 : no description available
bits : 8 - 13 (6 bit)
access : read-write
Crossbar A Select Register 6
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL12 : no description available
bits : 0 - 5 (6 bit)
access : read-write
SEL13 : no description available
bits : 8 - 13 (6 bit)
access : read-write
Crossbar A Select Register 7
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL14 : no description available
bits : 0 - 5 (6 bit)
access : read-write
SEL15 : no description available
bits : 8 - 13 (6 bit)
access : read-write
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