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XBARA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SEL0

SEL8

SEL9

SEL10

SEL11

SEL12

SEL13

SEL14

SEL15

SEL1

SEL16

SEL17

SEL18

SEL19

SEL20

SEL21

SEL22

SEL23

SEL24

SEL25

SEL26

SEL27

SEL28

SEL29

CTRL0

CTRL1

SEL2

SEL3

SEL4

SEL5

SEL6

SEL7


SEL0

Crossbar A Select Register 0
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL0 SEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1

SEL0 : no description available
bits : 0 - 5 (6 bit)
access : read-write

SEL1 : no description available
bits : 8 - 13 (6 bit)
access : read-write


SEL8

Crossbar A Select Register 8
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL8 SEL8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL16 SEL17

SEL16 : no description available
bits : 0 - 5 (6 bit)
access : read-write

SEL17 : no description available
bits : 8 - 13 (6 bit)
access : read-write


SEL9

Crossbar A Select Register 9
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL9 SEL9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL18 SEL19

SEL18 : no description available
bits : 0 - 5 (6 bit)
access : read-write

SEL19 : no description available
bits : 8 - 13 (6 bit)
access : read-write


SEL10

Crossbar A Select Register 10
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL10 SEL10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL20 SEL21

SEL20 : no description available
bits : 0 - 5 (6 bit)
access : read-write

SEL21 : no description available
bits : 8 - 13 (6 bit)
access : read-write


SEL11

Crossbar A Select Register 11
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL11 SEL11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL22 SEL23

SEL22 : no description available
bits : 0 - 5 (6 bit)
access : read-write

SEL23 : no description available
bits : 8 - 13 (6 bit)
access : read-write


SEL12

Crossbar A Select Register 12
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL12 SEL12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL24 SEL25

SEL24 : no description available
bits : 0 - 5 (6 bit)
access : read-write

SEL25 : no description available
bits : 8 - 13 (6 bit)
access : read-write


SEL13

Crossbar A Select Register 13
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL13 SEL13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL26 SEL27

SEL26 : no description available
bits : 0 - 5 (6 bit)
access : read-write

SEL27 : no description available
bits : 8 - 13 (6 bit)
access : read-write


SEL14

Crossbar A Select Register 14
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL14 SEL14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL28 SEL29

SEL28 : no description available
bits : 0 - 5 (6 bit)
access : read-write

SEL29 : no description available
bits : 8 - 13 (6 bit)
access : read-write


SEL15

Crossbar A Select Register 15
address_offset : 0x1E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL15 SEL15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL30 SEL31

SEL30 : no description available
bits : 0 - 5 (6 bit)
access : read-write

SEL31 : no description available
bits : 8 - 13 (6 bit)
access : read-write


SEL1

Crossbar A Select Register 1
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL1 SEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL2 SEL3

SEL2 : no description available
bits : 0 - 5 (6 bit)
access : read-write

SEL3 : no description available
bits : 8 - 13 (6 bit)
access : read-write


SEL16

Crossbar A Select Register 16
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL16 SEL16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL32 SEL33

SEL32 : no description available
bits : 0 - 5 (6 bit)
access : read-write

SEL33 : no description available
bits : 8 - 13 (6 bit)
access : read-write


SEL17

Crossbar A Select Register 17
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL17 SEL17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL34 SEL35

SEL34 : no description available
bits : 0 - 5 (6 bit)
access : read-write

SEL35 : no description available
bits : 8 - 13 (6 bit)
access : read-write


SEL18

Crossbar A Select Register 18
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL18 SEL18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL36 SEL37

SEL36 : no description available
bits : 0 - 5 (6 bit)
access : read-write

SEL37 : no description available
bits : 8 - 13 (6 bit)
access : read-write


SEL19

Crossbar A Select Register 19
address_offset : 0x26 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL19 SEL19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL38 SEL39

SEL38 : no description available
bits : 0 - 5 (6 bit)
access : read-write

SEL39 : no description available
bits : 8 - 13 (6 bit)
access : read-write


SEL20

Crossbar A Select Register 20
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL20 SEL20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL40 SEL41

SEL40 : no description available
bits : 0 - 5 (6 bit)
access : read-write

SEL41 : no description available
bits : 8 - 13 (6 bit)
access : read-write


SEL21

Crossbar A Select Register 21
address_offset : 0x2A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL21 SEL21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL42 SEL43

SEL42 : no description available
bits : 0 - 5 (6 bit)
access : read-write

SEL43 : no description available
bits : 8 - 13 (6 bit)
access : read-write


SEL22

Crossbar A Select Register 22
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL22 SEL22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL44 SEL45

SEL44 : no description available
bits : 0 - 5 (6 bit)
access : read-write

SEL45 : no description available
bits : 8 - 13 (6 bit)
access : read-write


SEL23

Crossbar A Select Register 23
address_offset : 0x2E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL23 SEL23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL46 SEL47

SEL46 : no description available
bits : 0 - 5 (6 bit)
access : read-write

SEL47 : no description available
bits : 8 - 13 (6 bit)
access : read-write


SEL24

Crossbar A Select Register 24
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL24 SEL24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL48 SEL49

SEL48 : no description available
bits : 0 - 5 (6 bit)
access : read-write

SEL49 : no description available
bits : 8 - 13 (6 bit)
access : read-write


SEL25

Crossbar A Select Register 25
address_offset : 0x32 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL25 SEL25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL50 SEL51

SEL50 : no description available
bits : 0 - 5 (6 bit)
access : read-write

SEL51 : no description available
bits : 8 - 13 (6 bit)
access : read-write


SEL26

Crossbar A Select Register 26
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL26 SEL26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL52 SEL53

SEL52 : no description available
bits : 0 - 5 (6 bit)
access : read-write

SEL53 : no description available
bits : 8 - 13 (6 bit)
access : read-write


SEL27

Crossbar A Select Register 27
address_offset : 0x36 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL27 SEL27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL54 SEL55

SEL54 : no description available
bits : 0 - 5 (6 bit)
access : read-write

SEL55 : no description available
bits : 8 - 13 (6 bit)
access : read-write


SEL28

Crossbar A Select Register 28
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL28 SEL28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL56 SEL57

SEL56 : no description available
bits : 0 - 5 (6 bit)
access : read-write

SEL57 : no description available
bits : 8 - 13 (6 bit)
access : read-write


SEL29

Crossbar A Select Register 29
address_offset : 0x3A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL29 SEL29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL58

SEL58 : no description available
bits : 0 - 5 (6 bit)
access : read-write


CTRL0

Crossbar A Control Register 0
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL0 CTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEN0 IEN0 EDGE0 STS0 DEN1 IEN1 EDGE1 STS1

DEN0 : DMA Enable for XBAR_OUT0
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA disabled

#1 : 1

DMA enabled

End of enumeration elements list.

IEN0 : Interrupt Enable for XBAR_OUT0
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

EDGE0 : Active edge for edge detection on XBAR_OUT0
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 00

STS0 never asserts

#01 : 01

STS0 asserts on rising edges of XBAR_OUT0

#10 : 10

STS0 asserts on falling edges of XBAR_OUT0

#11 : 11

STS0 asserts on rising and falling edges of XBAR_OUT0

End of enumeration elements list.

STS0 : Edge detection status for XBAR_OUT0
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Active edge not yet detected on XBAR_OUT0

#1 : 1

Active edge detected on XBAR_OUT0

End of enumeration elements list.

DEN1 : DMA Enable for XBAR_OUT1
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA disabled

#1 : 1

DMA enabled

End of enumeration elements list.

IEN1 : Interrupt Enable for XBAR_OUT1
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

EDGE1 : Active edge for edge detection on XBAR_OUT1
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

#00 : 00

STS1 never asserts

#01 : 01

STS1 asserts on rising edges of XBAR_OUT1

#10 : 10

STS1 asserts on falling edges of XBAR_OUT1

#11 : 11

STS1 asserts on rising and falling edges of XBAR_OUT1

End of enumeration elements list.

STS1 : Edge detection status for XBAR_OUT1
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Active edge not yet detected on XBAR_OUT1

#1 : 1

Active edge detected on XBAR_OUT1

End of enumeration elements list.


CTRL1

Crossbar A Control Register 1
address_offset : 0x3E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL1 CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEN2 IEN2 EDGE2 STS2 DEN3 IEN3 EDGE3 STS3

DEN2 : DMA Enable for XBAR_OUT2
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA disabled

#1 : 1

DMA enabled

End of enumeration elements list.

IEN2 : Interrupt Enable for XBAR_OUT2
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

EDGE2 : Active edge for edge detection on XBAR_OUT2
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 00

STS2 never asserts

#01 : 01

STS2 asserts on rising edges of XBAR_OUT2

#10 : 10

STS2 asserts on falling edges of XBAR_OUT2

#11 : 11

STS2 asserts on rising and falling edges of XBAR_OUT2

End of enumeration elements list.

STS2 : Edge detection status for XBAR_OUT2
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Active edge not yet detected on XBAR_OUT2

#1 : 1

Active edge detected on XBAR_OUT2

End of enumeration elements list.

DEN3 : DMA Enable for XBAR_OUT3
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA disabled

#1 : 1

DMA enabled

End of enumeration elements list.

IEN3 : Interrupt Enable for XBAR_OUT3
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

EDGE3 : Active edge for edge detection on XBAR_OUT3
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

#00 : 00

STS3 never asserts

#01 : 01

STS3 asserts on rising edges of XBAR_OUT3

#10 : 10

STS3 asserts on falling edges of XBAR_OUT3

#11 : 11

STS3 asserts on rising and falling edges of XBAR_OUT3

End of enumeration elements list.

STS3 : Edge detection status for XBAR_OUT3
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Active edge not yet detected on XBAR_OUT3

#1 : 1

Active edge detected on XBAR_OUT3

End of enumeration elements list.


SEL2

Crossbar A Select Register 2
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL2 SEL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL4 SEL5

SEL4 : no description available
bits : 0 - 5 (6 bit)
access : read-write

SEL5 : no description available
bits : 8 - 13 (6 bit)
access : read-write


SEL3

Crossbar A Select Register 3
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL3 SEL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL6 SEL7

SEL6 : no description available
bits : 0 - 5 (6 bit)
access : read-write

SEL7 : no description available
bits : 8 - 13 (6 bit)
access : read-write


SEL4

Crossbar A Select Register 4
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL4 SEL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL8 SEL9

SEL8 : no description available
bits : 0 - 5 (6 bit)
access : read-write

SEL9 : no description available
bits : 8 - 13 (6 bit)
access : read-write


SEL5

Crossbar A Select Register 5
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL5 SEL5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL10 SEL11

SEL10 : no description available
bits : 0 - 5 (6 bit)
access : read-write

SEL11 : no description available
bits : 8 - 13 (6 bit)
access : read-write


SEL6

Crossbar A Select Register 6
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL6 SEL6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL12 SEL13

SEL12 : no description available
bits : 0 - 5 (6 bit)
access : read-write

SEL13 : no description available
bits : 8 - 13 (6 bit)
access : read-write


SEL7

Crossbar A Select Register 7
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEL7 SEL7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL14 SEL15

SEL14 : no description available
bits : 0 - 5 (6 bit)
access : read-write

SEL15 : no description available
bits : 8 - 13 (6 bit)
access : read-write



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