Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x196 byte (0x0)
mem_usage : registers
protection : not protected
Counter Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Counter Register Bits
bits : 0 - 15 (16 bit)
access : read-only
Capture Compare A Register
address_offset : 0x102 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGCMPA : Edge Compare A
bits : 0 - 7 (8 bit)
access : read-write
EDGCNTA : Edge Counter A
bits : 8 - 15 (8 bit)
access : read-only
Capture Control B Register
address_offset : 0x108 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARMB : Arm B
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Input capture operation is disabled.
#1 : 1
Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled.
End of enumeration elements list.
ONESHOTB : One Shot Mode B
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit.
#1 : 1
One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared.
End of enumeration elements list.
EDGB0 : Edge B 0
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
Disabled
#01 : 01
Capture falling edges
#10 : 10
Capture rising edges
#11 : 11
Capture any edge
End of enumeration elements list.
EDGB1 : Edge B 1
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
Disabled
#01 : 01
Capture falling edges
#10 : 10
Capture rising edges
#11 : 11
Capture any edge
End of enumeration elements list.
INP_SELB : Input Select B
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Raw PWM_B input signal selected as source.
#1 : 1
Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers.
End of enumeration elements list.
EDGCNTB_EN : Edge Counter B Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge counter disabled and held in reset
#1 : 1
Edge counter enabled
End of enumeration elements list.
CFBWM : Capture B FIFOs Water Mark
bits : 8 - 9 (2 bit)
access : read-write
CB0CNT : Capture B0 FIFO Word Count
bits : 10 - 12 (3 bit)
access : read-only
CB1CNT : Capture B1 FIFO Word Count
bits : 13 - 15 (3 bit)
access : read-only
Capture Compare B Register
address_offset : 0x10E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGCMPB : Edge Compare B
bits : 0 - 7 (8 bit)
access : read-write
EDGCNTB : Edge Counter B
bits : 8 - 15 (8 bit)
access : read-only
Capture Control X Register
address_offset : 0x114 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARMX : Arm X
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Input capture operation is disabled.
#1 : 1
Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.
End of enumeration elements list.
ONESHOTX : One Shot Mode Aux
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit.
#1 : 1
One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared.
End of enumeration elements list.
EDGX0 : Edge X 0
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
Disabled
#01 : 01
Capture falling edges
#10 : 10
Capture rising edges
#11 : 11
Capture any edge
End of enumeration elements list.
EDGX1 : Edge X 1
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
Disabled
#01 : 01
Capture falling edges
#10 : 10
Capture rising edges
#11 : 11
Capture any edge
End of enumeration elements list.
INP_SELX : Input Select X
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Raw PWM_X input signal selected as source.
#1 : 1
Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers.
End of enumeration elements list.
EDGCNTX_EN : Edge Counter X Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge counter disabled and held in reset
#1 : 1
Edge counter enabled
End of enumeration elements list.
CFXWM : Capture X FIFOs Water Mark
bits : 8 - 9 (2 bit)
access : read-write
CX0CNT : Capture X0 FIFO Word Count
bits : 10 - 12 (3 bit)
access : read-only
CX1CNT : Capture X1 FIFO Word Count
bits : 13 - 15 (3 bit)
access : read-only
Capture Compare X Register
address_offset : 0x11A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGCMPX : Edge Compare X
bits : 0 - 7 (8 bit)
access : read-write
EDGCNTX : Edge Counter X
bits : 8 - 15 (8 bit)
access : read-only
Counter Register
address_offset : 0x120 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Counter Register Bits
bits : 0 - 15 (16 bit)
access : read-only
Capture Value 0 Register
address_offset : 0x120 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPTVAL0 : This read-only register stores the value captured from the submodule counter
bits : 0 - 15 (16 bit)
access : read-only
Capture Value 0 Cycle Register
address_offset : 0x126 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CVAL0CYC : This read-only register stores the cycle number corresponding to the value captured in CVAL0
bits : 0 - 3 (4 bit)
access : read-only
Initial Count Register
address_offset : 0x128 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT : Initial Count Register Bits
bits : 0 - 15 (16 bit)
access : read-write
Capture Value 1 Register
address_offset : 0x12C Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPTVAL1 : This read-only register stores the value captured from the submodule counter
bits : 0 - 15 (16 bit)
access : read-only
Control 2 Register
address_offset : 0x130 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_SEL : Clock Source Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
The IPBus clock is used as the clock for the local prescaler and counter.
#01 : 01
EXT_CLK is used as the clock for the local prescaler and counter.
#10 : 10
Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0.
End of enumeration elements list.
RELOAD_SEL : Reload Source Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The local RELOAD signal is used to reload registers.
#1 : 1
The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0.
End of enumeration elements list.
FORCE_SEL : This read/write bit determines the source of the FORCE OUTPUT signal for this submodule.
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#000 : 000
The local force signal, CTRL2[FORCE], from this submodule is used to force updates.
#001 : 001
The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0.
#010 : 010
The local reload signal from this submodule is used to force updates without regard to the state of LDOK.
#011 : 011
The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0.
#100 : 100
The local sync signal from this submodule is used to force updates.
#101 : 101
The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0.
#110 : 110
The external force signal, EXT_FORCE, from outside the PWM module causes updates.
#111 : 111
The external sync signal, EXT_SYNC, from outside the PWM module causes updates.
End of enumeration elements list.
FORCE : Force Initialization
bits : 6 - 6 (1 bit)
access : write-only
FRCEN : This bit allows the CTRL2[FORCE] signal to initialize the counter without regard to the signal selected by CTRL2[INIT_SEL]
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Initialization from a FORCE_OUT is disabled.
#1 : 1
Initialization from a FORCE_OUT is enabled.
End of enumeration elements list.
INIT_SEL : Initialization Control Select
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
Local sync (PWM_X) causes initialization.
#01 : 01
Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs.
#10 : 10
Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0.
#11 : 11
EXT_SYNC causes initialization.
End of enumeration elements list.
PWMX_INIT : PWM_X Initial Value
bits : 10 - 10 (1 bit)
access : read-write
PWM45_INIT : PWM45 Initial Value
bits : 11 - 11 (1 bit)
access : read-write
PWM23_INIT : PWM23 Initial Value
bits : 12 - 12 (1 bit)
access : read-write
INDEP : Independent or Complementary Pair Operation
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_A and PWM_B form a complementary PWM pair.
#1 : 1
PWM_A and PWM_B outputs are independent PWMs.
End of enumeration elements list.
WAITEN : WAIT Enable
bits : 14 - 14 (1 bit)
access : read-write
DBGEN : Debug Enable
bits : 15 - 15 (1 bit)
access : read-write
Capture Value 1 Cycle Register
address_offset : 0x132 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CVAL1CYC : This read-only register stores the cycle number corresponding to the value captured in CVAL1
bits : 0 - 3 (4 bit)
access : read-only
Control Register
address_offset : 0x138 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBLEN : Double Switching Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Double switching disabled.
#1 : 1
Double switching enabled.
End of enumeration elements list.
DBLX : PWMX Double Switching Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMX double pulse disabled.
#1 : 1
PWMX double pulse enabled.
End of enumeration elements list.
LDMOD : Load Mode Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL0[LDOK] is set.
#1 : 1
Buffered registers of this submodule are loaded and take effect immediately upon MCTRL0[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF].
End of enumeration elements list.
PRSC : Prescaler
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 000
PWM clock frequency = fclk
#001 : 001
PWM clock frequency = fclk/2
#010 : 010
PWM clock frequency = fclk/4
#011 : 011
PWM clock frequency = fclk/8
#100 : 100
PWM clock frequency = fclk/16
#101 : 101
PWM clock frequency = fclk/32
#110 : 110
PWM clock frequency = fclk/64
#111 : 111
PWM clock frequency = fclk/128
End of enumeration elements list.
DT : Deadtime
bits : 8 - 9 (2 bit)
access : read-only
FULL : Full Cycle Reload
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Full-cycle reloads disabled.
#1 : 1
Full-cycle reloads enabled.
End of enumeration elements list.
HALF : Half Cycle Reload
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Half-cycle reloads disabled.
#1 : 1
Half-cycle reloads enabled.
End of enumeration elements list.
LDFQ : Load Frequency
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Every PWM opportunity
#0001 : 0001
Every 2 PWM opportunities
#0010 : 0010
Every 3 PWM opportunities
#0011 : 0011
Every 4 PWM opportunities
#0100 : 0100
Every 5 PWM opportunities
#0101 : 0101
Every 6 PWM opportunities
#0110 : 0110
Every 7 PWM opportunities
#0111 : 0111
Every 8 PWM opportunities
#1000 : 1000
Every 9 PWM opportunities
#1001 : 1001
Every 10 PWM opportunities
#1010 : 1010
Every 11 PWM opportunities
#1011 : 1011
Every 12 PWM opportunities
#1100 : 1100
Every 13 PWM opportunities
#1101 : 1101
Every 14 PWM opportunities
#1110 : 1110
Every 15 PWM opportunities
#1111 : 1111
Every 16 PWM opportunities
End of enumeration elements list.
Capture Value 2 Register
address_offset : 0x138 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPTVAL2 : This read-only register stores the value captured from the submodule counter
bits : 0 - 15 (16 bit)
access : read-only
Capture Value 2 Cycle Register
address_offset : 0x13E Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CVAL2CYC : This read-only register stores the cycle number corresponding to the value captured in CVAL2
bits : 0 - 3 (4 bit)
access : read-only
Value Register 0
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL0 : Value Register 0
bits : 0 - 15 (16 bit)
access : read-write
Capture Value 3 Register
address_offset : 0x144 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPTVAL3 : This read-only register stores the value captured from the submodule counter
bits : 0 - 15 (16 bit)
access : read-only
Value Register 0
address_offset : 0x148 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL0 : Value Register 0
bits : 0 - 15 (16 bit)
access : read-write
Capture Value 3 Cycle Register
address_offset : 0x14A Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CVAL3CYC : This read-only register stores the cycle number corresponding to the value captured in CVAL3
bits : 0 - 3 (4 bit)
access : read-only
Fractional Value Register 1
address_offset : 0x150 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL1 : Fractional Value 1 Register
bits : 11 - 15 (5 bit)
access : read-write
Capture Value 4 Register
address_offset : 0x150 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPTVAL4 : This read-only register stores the value captured from the submodule counter
bits : 0 - 15 (16 bit)
access : read-only
Capture Value 4 Cycle Register
address_offset : 0x156 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CVAL4CYC : This read-only register stores the cycle number corresponding to the value captured in CVAL4
bits : 0 - 3 (4 bit)
access : read-only
Value Register 1
address_offset : 0x158 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL1 : Value Register 1
bits : 0 - 15 (16 bit)
access : read-write
Capture Value 5 Register
address_offset : 0x15C Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPTVAL5 : This read-only register stores the value captured from the submodule counter
bits : 0 - 15 (16 bit)
access : read-only
Fractional Value Register 2
address_offset : 0x160 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL2 : Fractional Value 2
bits : 11 - 15 (5 bit)
access : read-write
Capture Value 5 Cycle Register
address_offset : 0x162 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CVAL5CYC : This read-only register stores the cycle number corresponding to the value captured in CVAL5
bits : 0 - 3 (4 bit)
access : read-only
Value Register 2
address_offset : 0x168 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL2 : Value Register 2
bits : 0 - 15 (16 bit)
access : read-write
Fractional Value Register 3
address_offset : 0x170 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL3 : Fractional Value 3
bits : 11 - 15 (5 bit)
access : read-write
Value Register 3
address_offset : 0x178 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL3 : Value Register 3
bits : 0 - 15 (16 bit)
access : read-write
Fractional Value Register 1
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL1 : Fractional Value 1 Register
bits : 11 - 15 (5 bit)
access : read-write
Fractional Value Register 4
address_offset : 0x180 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL4 : Fractional Value 4
bits : 11 - 15 (5 bit)
access : read-write
Output Enable Register
address_offset : 0x180 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMX_EN : PWM_X Output Enables
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PWM_X output disabled.
#0001 : 1
PWM_X output enabled.
End of enumeration elements list.
PWMB_EN : PWM_B Output Enables
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PWM_B output disabled.
#0001 : 1
PWM_B output enabled.
End of enumeration elements list.
PWMA_EN : PWM_A Output Enables
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PWM_A output disabled.
#0001 : 1
PWM_A output enabled.
End of enumeration elements list.
Mask Register
address_offset : 0x182 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASKX : PWM_X Masks
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PWM_X output normal.
#0001 : 1
PWM_X output masked.
End of enumeration elements list.
MASKB : PWM_B Masks
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PWM_B output normal.
#0001 : 1
PWM_B output masked.
End of enumeration elements list.
MASKA : PWM_A Masks
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PWM_A output normal.
#0001 : 1
PWM_A output masked.
End of enumeration elements list.
UPDATE_MASK : Update Mask Bits Immediately
bits : 12 - 15 (4 bit)
access : write-only
Enumeration:
#0000 : 0
Normal operation. MASK* bits within the corresponding submodule are not updated until a FORCE_OUT event occurs within the submodule.
#0001 : 1
Immediate operation. MASK* bits within the corresponding submodule are updated on the following clock edge after setting this bit.
End of enumeration elements list.
Software Controlled Output Register
address_offset : 0x184 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SM0OUT45 : Submodule 0 Software Controlled Output 45
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45.
#1 : 1
A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45.
End of enumeration elements list.
SM0OUT23 : Submodule 0 Software Controlled Output 23
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23.
#1 : 1
A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23.
End of enumeration elements list.
SM1OUT45 : Submodule 1 Software Controlled Output 45
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45.
#1 : 1
A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45.
End of enumeration elements list.
SM1OUT23 : Submodule 1 Software Controlled Output 23
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23.
#1 : 1
A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23.
End of enumeration elements list.
SM2OUT45 : Submodule 2 Software Controlled Output 45
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45.
#1 : 1
A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45.
End of enumeration elements list.
SM2OUT23 : Submodule 2 Software Controlled Output 23
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23.
#1 : 1
A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23.
End of enumeration elements list.
SM3OUT45 : Submodule 3 Software Controlled Output 45
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45.
#1 : 1
A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45.
End of enumeration elements list.
SM3OUT23 : Submodule 3 Software Controlled Output 23
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23.
#1 : 1
A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23.
End of enumeration elements list.
PWM Source Select Register
address_offset : 0x186 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SM0SEL45 : Submodule 0 PWM45 Control Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
Generated SM0PWM45 signal is used by the deadtime logic.
#01 : 01
Inverted generated SM0PWM45 signal is used by the deadtime logic.
#10 : 10
SWCOUT[SM0OUT45] is used by the deadtime logic.
#11 : 11
PWMx_EXTB0 signal is used by the deadtime logic.
End of enumeration elements list.
SM0SEL23 : Submodule 0 PWM23 Control Select
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
Generated SM0PWM23 signal is used by the deadtime logic.
#01 : 01
Inverted generated SM0PWM23 signal is used by the deadtime logic.
#10 : 10
SWCOUT[SM0OUT23] is used by the deadtime logic.
#11 : 11
PWMx_EXTA0 signal is used by the deadtime logic.
End of enumeration elements list.
SM1SEL45 : Submodule 1 PWM45 Control Select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
Generated SM1PWM45 signal is used by the deadtime logic.
#01 : 01
Inverted generated SM1PWM45 signal is used by the deadtime logic.
#10 : 10
SWCOUT[SM1OUT45] is used by the deadtime logic.
#11 : 11
PWMx_EXTB1 signal is used by the deadtime logic.
End of enumeration elements list.
SM1SEL23 : Submodule 1 PWM23 Control Select
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
Generated SM1PWM23 signal is used by the deadtime logic.
#01 : 01
Inverted generated SM1PWM23 signal is used by the deadtime logic.
#10 : 10
SWCOUT[SM1OUT23] is used by the deadtime logic.
#11 : 11
PWMx_EXTA1 signal is used by the deadtime logic.
End of enumeration elements list.
SM2SEL45 : Submodule 2 PWM45 Control Select
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
Generated SM2PWM45 signal is used by the deadtime logic.
#01 : 01
Inverted generated SM2PWM45 signal is used by the deadtime logic.
#10 : 10
SWCOUT[SM2OUT45] is used by the deadtime logic.
#11 : 11
PWMx_EXTB2 signal is used by the deadtime logic.
End of enumeration elements list.
SM2SEL23 : Submodule 2 PWM23 Control Select
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 00
Generated SM2PWM23 signal is used by the deadtime logic.
#01 : 01
Inverted generated SM2PWM23 signal is used by the deadtime logic.
#10 : 10
SWCOUT[SM2OUT23] is used by the deadtime logic.
#11 : 11
PWMx_EXTA2 signal is used by the deadtime logic.
End of enumeration elements list.
SM3SEL45 : Submodule 3 PWM45 Control Select
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 00
Generated SM3PWM45 signal is used by the deadtime logic.
#01 : 01
Inverted generated SM3PWM45 signal is used by the deadtime logic.
#10 : 10
SWCOUT[SM3OUT45] is used by the deadtime logic.
#11 : 11
PWMx_EXTB3 signal is used by the deadtime logic.
End of enumeration elements list.
SM3SEL23 : Submodule 3 PWM23 Control Select
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
Generated SM3PWM23 signal is used by the deadtime logic.
#01 : 01
Inverted generated SM3PWM23 signal is used by the deadtime logic.
#10 : 10
SWCOUT[SM3OUT23] is used by the deadtime logic.
#11 : 11
PWMx_EXTA3 signal is used by the deadtime logic.
End of enumeration elements list.
Value Register 4
address_offset : 0x188 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL4 : Value Register 4
bits : 0 - 15 (16 bit)
access : read-write
Master Control Register 0
address_offset : 0x188 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LDOK : Load Okay
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
Do not load new values.
#0001 : 1
Load prescaler, modulus, and PWM values of the corresponding submodule.
End of enumeration elements list.
CLDOK : Clear Load Okay
bits : 4 - 7 (4 bit)
access : write-only
RUN : Run
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PWM generator is disabled in the corresponding submodule.
#0001 : 1
PWM generator is enabled in the corresponding submodule.
End of enumeration elements list.
IPOL : Current Polarity
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PWM23 is used to generate complementary PWM pair in the corresponding submodule.
#0001 : 1
PWM45 is used to generate complementary PWM pair in the corresponding submodule.
End of enumeration elements list.
Master Control Register 1
address_offset : 0x18A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MONPLL : Monitor PLL State
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software.
#01 : 01
Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems.
#10 : 10
Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. These bits are write protected until the next reset.
#11 : 11
Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. These bits are write protected until the next reset.
End of enumeration elements list.
Fault Control Register
address_offset : 0x18C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIE : Fault Interrupt Enables
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
FAULTx CPU interrupt requests disabled.
#0001 : 1
FAULTx CPU interrupt requests enabled.
End of enumeration elements list.
FSAFE : Fault Safety Mode
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of FSTS[FFPINx]. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn).
#0001 : 1
Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL].
End of enumeration elements list.
FAUTO : Automatic Fault Clearing
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending the state of FSTS[FFULL]. This is further controlled by FCTRL[FSAFE].
#0001 : 1
Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of FSTS[FFLAGx].
End of enumeration elements list.
FLVL : Fault Level
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0
A logic 0 on the fault input indicates a fault condition.
#0001 : 1
A logic 1 on the fault input indicates a fault condition.
End of enumeration elements list.
Fault Status Register
address_offset : 0x18E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FFLAG : Fault Flags
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
No fault on the FAULTx pin.
#0001 : 1
Fault on the FAULTx pin.
End of enumeration elements list.
FFULL : Full Cycle
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PWM outputs are not re-enabled at the start of a full cycle
#0001 : 1
PWM outputs are re-enabled at the start of a full cycle
End of enumeration elements list.
FFPIN : Filtered Fault Pins
bits : 8 - 11 (4 bit)
access : read-only
FHALF : Half Cycle Fault Recovery
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PWM outputs are not re-enabled at the start of a half cycle.
#0001 : 1
PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0).
End of enumeration elements list.
Fractional Value Register 5
address_offset : 0x190 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL5 : Fractional Value 5
bits : 11 - 15 (5 bit)
access : read-write
Fault Filter Register
address_offset : 0x190 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILT_PER : Fault Filter Period
bits : 0 - 7 (8 bit)
access : read-write
FILT_CNT : Fault Filter Count
bits : 8 - 10 (3 bit)
access : read-write
GSTR : Fault Glitch Stretch Enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input glitch stretching is disabled.
#1 : 1
Input fault signals will be stretched to at least 2 IPBus clock cycles.
End of enumeration elements list.
Fault Test Register
address_offset : 0x192 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTEST : Fault Test
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No fault
#1 : 1
Cause a simulated fault
End of enumeration elements list.
Fault Control 2 Register
address_offset : 0x194 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NOCOMB : No Combinational Path From Fault Input To PWM Output
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined with the filtered and latched fault signals to disable the PWM outputs.
#0001 : 1
The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered and latched fault signals are used to disable the PWM outputs.
End of enumeration elements list.
Value Register 5
address_offset : 0x198 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL5 : Value Register 5
bits : 0 - 15 (16 bit)
access : read-write
Fractional Control Register
address_offset : 0x1A0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRAC1_EN : Fractional Cycle PWM Period Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable fractional cycle length for the PWM period.
#1 : 1
Enable fractional cycle length for the PWM period.
End of enumeration elements list.
FRAC23_EN : Fractional Cycle Placement Enable for PWM_A
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable fractional cycle placement for PWM_A.
#1 : 1
Enable fractional cycle placement for PWM_A.
End of enumeration elements list.
FRAC45_EN : Fractional Cycle Placement Enable for PWM_B
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable fractional cycle placement for PWM_B.
#1 : 1
Enable fractional cycle placement for PWM_B.
End of enumeration elements list.
FRAC_PU : Fractional Delay Circuit Power Up
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Turn off fractional delay logic.
#1 : 1
Power up fractional delay logic.
End of enumeration elements list.
TEST : Test Status Bit
bits : 15 - 15 (1 bit)
access : read-only
Output Control Register
address_offset : 0x1A8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMXFS : PWM_X Fault State
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
Output is forced to logic 0 state prior to consideration of output polarity control.
#01 : 01
Output is forced to logic 1 state prior to consideration of output polarity control.
#10 : 10
Output is tristated.
#11 : 11
Output is tristated.
End of enumeration elements list.
PWMBFS : PWM_B Fault State
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
Output is forced to logic 0 state prior to consideration of output polarity control.
#01 : 01
Output is forced to logic 1 state prior to consideration of output polarity control.
#10 : 10
Output is tristated.
#11 : 11
Output is tristated.
End of enumeration elements list.
PWMAFS : PWM_A Fault State
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
Output is forced to logic 0 state prior to consideration of output polarity control.
#01 : 01
Output is forced to logic 1 state prior to consideration of output polarity control.
#10 : 10
Output is tristated.
#11 : 11
Output is tristated.
End of enumeration elements list.
POLX : PWM_X Output Polarity
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state.
#1 : 1
PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state.
End of enumeration elements list.
POLB : PWM_B Output Polarity
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state.
#1 : 1
PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state.
End of enumeration elements list.
POLA : PWM_A Output Polarity
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state.
#1 : 1
PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state.
End of enumeration elements list.
PWMX_IN : PWM_X Input
bits : 13 - 13 (1 bit)
access : read-only
PWMB_IN : PWM_B Input
bits : 14 - 14 (1 bit)
access : read-only
PWMA_IN : PWM_A Input
bits : 15 - 15 (1 bit)
access : read-only
Status Register
address_offset : 0x1B0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPF : Compare Flags
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
No compare event has occurred for a particular VALx value.
#1 : 1
A compare event has occurred for a particular VALx value.
End of enumeration elements list.
CFX0 : Capture Flag X0
bits : 6 - 6 (1 bit)
access : read-write
CFX1 : Capture Flag X1
bits : 7 - 7 (1 bit)
access : read-write
CFB0 : Capture Flag B0
bits : 8 - 8 (1 bit)
access : read-write
CFB1 : Capture Flag B1
bits : 9 - 9 (1 bit)
access : read-write
CFA0 : Capture Flag A0
bits : 10 - 10 (1 bit)
access : read-write
CFA1 : Capture Flag A1
bits : 11 - 11 (1 bit)
access : read-write
RF : Reload Flag
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No new reload cycle since last STS[RF] clearing
#1 : 1
New reload cycle since last STS[RF] clearing
End of enumeration elements list.
REF : Reload Error Flag
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reload error occurred.
#1 : 1
Reload signal occurred with non-coherent data and MCTRL0[LDOK] = 0.
End of enumeration elements list.
RUF : Registers Updated Flag
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
#0 : 0
No register update has occurred since last reload.
#1 : 1
At least one of the double buffered registers has been updated since the last reload.
End of enumeration elements list.
Interrupt Enable Register
address_offset : 0x1B8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPIE : Compare Interrupt Enables
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding STS[CMPF] bit will not cause an interrupt request.
#1 : 1
The corresponding STS[CMPF] bit will cause an interrupt request.
End of enumeration elements list.
CX0IE : Capture X 0 Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt request disabled for STS[CFX0].
#1 : 1
Interrupt request enabled for STS[CFX0].
End of enumeration elements list.
CX1IE : Capture X 1 Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt request disabled for STS[CFX1].
#1 : 1
Interrupt request enabled for STS[CFX1].
End of enumeration elements list.
CB0IE : Capture B 0 Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt request disabled for STS[CFB0].
#1 : 1
Interrupt request enabled for STS[CFB0].
End of enumeration elements list.
CB1IE : Capture B 1 Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt request disabled for STS[CFB1].
#1 : 1
Interrupt request enabled for STS[CFB1].
End of enumeration elements list.
CA0IE : Capture A 0 Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt request disabled for STS[CFA0].
#1 : 1
Interrupt request enabled for STS[CFA0].
End of enumeration elements list.
CA1IE : Capture A 1 Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt request disabled for STS[CFA1].
#1 : 1
Interrupt request enabled for STS[CFA1].
End of enumeration elements list.
RIE : Reload Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
STS[RF] CPU interrupt requests disabled
#1 : 1
STS[RF] CPU interrupt requests enabled
End of enumeration elements list.
REIE : Reload Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
STS[REF] CPU interrupt requests disabled
#1 : 1
STS[REF] CPU interrupt requests enabled
End of enumeration elements list.
Value Register 1
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL1 : Value Register 1
bits : 0 - 15 (16 bit)
access : read-write
DMA Enable Register
address_offset : 0x1C0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CX0DE : Capture X0 FIFO DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
CX1DE : Capture X1 FIFO DMA Enable
bits : 1 - 1 (1 bit)
access : read-write
CB0DE : Capture B0 FIFO DMA Enable
bits : 2 - 2 (1 bit)
access : read-write
CB1DE : Capture B1 FIFO DMA Enable
bits : 3 - 3 (1 bit)
access : read-write
CA0DE : Capture A0 FIFO DMA Enable
bits : 4 - 4 (1 bit)
access : read-write
CA1DE : Capture A1 FIFO DMA Enable
bits : 5 - 5 (1 bit)
access : read-write
CAPTDE : Capture DMA Enable Source Select
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
Read DMA requests disabled.
#01 : 01
Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive.
#10 : 10
A local sync (VAL1 matches counter) sets the read DMA request.
#11 : 11
A local reload (STS[RF] being set) sets the read DMA request.
End of enumeration elements list.
FAND : FIFO Watermark AND Control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Selected FIFO watermarks are OR'ed together.
#1 : 1
Selected FIFO watermarks are AND'ed together.
End of enumeration elements list.
VALDE : Value Registers DMA Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA write requests disabled
#1 : 1
DMA write requests for the VALx and FRACVALx registers enabled
End of enumeration elements list.
Output Trigger Control Register
address_offset : 0x1C8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT_TRIG_EN : Output Trigger Enables
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
PWM_OUT_TRIGx will not set when the counter value matches the VALx value.
#1 : 1
PWM_OUT_TRIGx will set when the counter value matches the VALx value.
End of enumeration elements list.
TRGFRQ : Trigger frequency
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.
#1 : 1
Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.
End of enumeration elements list.
PWBOT1 : Output Trigger 1 Source Select
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port.
#1 : 1
Route the PWM1 output to the PWM_OUT_TRIG1 port.
End of enumeration elements list.
PWAOT0 : Output Trigger 0 Source Select
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port.
#1 : 1
Route the PWM0 output to the PWM_OUT_TRIG0 port.
End of enumeration elements list.
Fault Disable Mapping Register 0
address_offset : 0x1D0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIS0A : PWM_A Fault Disable Mask 0
bits : 0 - 3 (4 bit)
access : read-write
DIS0B : PWM_B Fault Disable Mask 0
bits : 4 - 7 (4 bit)
access : read-write
DIS0X : PWM_X Fault Disable Mask 0
bits : 8 - 11 (4 bit)
access : read-write
Deadtime Count Register 0
address_offset : 0x1E0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTCNT0 : The DTCNT0 field is interpreted differently depending on whether or not the fractional delays are being used (FRCNTRL[FRAC23_EN] is set)
bits : 0 - 15 (16 bit)
access : read-write
Deadtime Count Register 1
address_offset : 0x1E8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTCNT1 : The DTCNT1 field is interpreted differently depending on whether or not the fractional delays are being used (FRCNTRL[FRAC45_EN] is set)
bits : 0 - 15 (16 bit)
access : read-write
Capture Control A Register
address_offset : 0x1F0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARMA : Arm A
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Input capture operation is disabled.
#1 : 1
Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled.
End of enumeration elements list.
ONESHOTA : One Shot Mode A
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit.
#1 : 1
One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared.
End of enumeration elements list.
EDGA0 : Edge A 0
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
Disabled
#01 : 01
Capture falling edges
#10 : 10
Capture rising edges
#11 : 11
Capture any edge
End of enumeration elements list.
EDGA1 : Edge A 1
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
Disabled
#01 : 01
Capture falling edges
#10 : 10
Capture rising edges
#11 : 11
Capture any edge
End of enumeration elements list.
INP_SELA : Input Select A
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Raw PWM_A input signal selected as source.
#1 : 1
Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers.
End of enumeration elements list.
EDGCNTA_EN : Edge Counter A Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge counter disabled and held in reset
#1 : 1
Edge counter enabled
End of enumeration elements list.
CFAWM : Capture A FIFOs Water Mark
bits : 8 - 9 (2 bit)
access : read-write
CA0CNT : Capture A0 FIFO Word Count
bits : 10 - 12 (3 bit)
access : read-only
CA1CNT : Capture A1 FIFO Word Count
bits : 13 - 15 (3 bit)
access : read-only
Capture Compare A Register
address_offset : 0x1F8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGCMPA : Edge Compare A
bits : 0 - 7 (8 bit)
access : read-write
EDGCNTA : Edge Counter A
bits : 8 - 15 (8 bit)
access : read-only
Fractional Value Register 2
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL2 : Fractional Value 2
bits : 11 - 15 (5 bit)
access : read-write
Capture Control B Register
address_offset : 0x200 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARMB : Arm B
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Input capture operation is disabled.
#1 : 1
Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled.
End of enumeration elements list.
ONESHOTB : One Shot Mode B
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit.
#1 : 1
One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared.
End of enumeration elements list.
EDGB0 : Edge B 0
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
Disabled
#01 : 01
Capture falling edges
#10 : 10
Capture rising edges
#11 : 11
Capture any edge
End of enumeration elements list.
EDGB1 : Edge B 1
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
Disabled
#01 : 01
Capture falling edges
#10 : 10
Capture rising edges
#11 : 11
Capture any edge
End of enumeration elements list.
INP_SELB : Input Select B
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Raw PWM_B input signal selected as source.
#1 : 1
Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers.
End of enumeration elements list.
EDGCNTB_EN : Edge Counter B Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge counter disabled and held in reset
#1 : 1
Edge counter enabled
End of enumeration elements list.
CFBWM : Capture B FIFOs Water Mark
bits : 8 - 9 (2 bit)
access : read-write
CB0CNT : Capture B0 FIFO Word Count
bits : 10 - 12 (3 bit)
access : read-only
CB1CNT : Capture B1 FIFO Word Count
bits : 13 - 15 (3 bit)
access : read-only
Capture Compare B Register
address_offset : 0x208 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGCMPB : Edge Compare B
bits : 0 - 7 (8 bit)
access : read-write
EDGCNTB : Edge Counter B
bits : 8 - 15 (8 bit)
access : read-only
Capture Control X Register
address_offset : 0x210 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARMX : Arm X
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Input capture operation is disabled.
#1 : 1
Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.
End of enumeration elements list.
ONESHOTX : One Shot Mode Aux
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit.
#1 : 1
One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared.
End of enumeration elements list.
EDGX0 : Edge X 0
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
Disabled
#01 : 01
Capture falling edges
#10 : 10
Capture rising edges
#11 : 11
Capture any edge
End of enumeration elements list.
EDGX1 : Edge X 1
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
Disabled
#01 : 01
Capture falling edges
#10 : 10
Capture rising edges
#11 : 11
Capture any edge
End of enumeration elements list.
INP_SELX : Input Select X
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Raw PWM_X input signal selected as source.
#1 : 1
Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers.
End of enumeration elements list.
EDGCNTX_EN : Edge Counter X Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge counter disabled and held in reset
#1 : 1
Edge counter enabled
End of enumeration elements list.
CFXWM : Capture X FIFOs Water Mark
bits : 8 - 9 (2 bit)
access : read-write
CX0CNT : Capture X0 FIFO Word Count
bits : 10 - 12 (3 bit)
access : read-only
CX1CNT : Capture X1 FIFO Word Count
bits : 13 - 15 (3 bit)
access : read-only
Capture Compare X Register
address_offset : 0x218 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGCMPX : Edge Compare X
bits : 0 - 7 (8 bit)
access : read-write
EDGCNTX : Edge Counter X
bits : 8 - 15 (8 bit)
access : read-only
Capture Value 0 Register
address_offset : 0x220 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPTVAL0 : This read-only register stores the value captured from the submodule counter
bits : 0 - 15 (16 bit)
access : read-only
Capture Value 0 Cycle Register
address_offset : 0x228 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CVAL0CYC : This read-only register stores the cycle number corresponding to the value captured in CVAL0
bits : 0 - 3 (4 bit)
access : read-only
Capture Value 1 Register
address_offset : 0x230 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPTVAL1 : This read-only register stores the value captured from the submodule counter
bits : 0 - 15 (16 bit)
access : read-only
Capture Value 1 Cycle Register
address_offset : 0x238 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CVAL1CYC : This read-only register stores the cycle number corresponding to the value captured in CVAL1
bits : 0 - 3 (4 bit)
access : read-only
Value Register 2
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL2 : Value Register 2
bits : 0 - 15 (16 bit)
access : read-write
Counter Register
address_offset : 0x240 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Counter Register Bits
bits : 0 - 15 (16 bit)
access : read-only
Capture Value 2 Register
address_offset : 0x240 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPTVAL2 : This read-only register stores the value captured from the submodule counter
bits : 0 - 15 (16 bit)
access : read-only
Capture Value 2 Cycle Register
address_offset : 0x248 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CVAL2CYC : This read-only register stores the cycle number corresponding to the value captured in CVAL2
bits : 0 - 3 (4 bit)
access : read-only
Initial Count Register
address_offset : 0x24A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT : Initial Count Register Bits
bits : 0 - 15 (16 bit)
access : read-write
Capture Value 3 Register
address_offset : 0x250 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPTVAL3 : This read-only register stores the value captured from the submodule counter
bits : 0 - 15 (16 bit)
access : read-only
Control 2 Register
address_offset : 0x254 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_SEL : Clock Source Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
The IPBus clock is used as the clock for the local prescaler and counter.
#01 : 01
EXT_CLK is used as the clock for the local prescaler and counter.
#10 : 10
Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0.
End of enumeration elements list.
RELOAD_SEL : Reload Source Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The local RELOAD signal is used to reload registers.
#1 : 1
The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0.
End of enumeration elements list.
FORCE_SEL : This read/write bit determines the source of the FORCE OUTPUT signal for this submodule.
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#000 : 000
The local force signal, CTRL2[FORCE], from this submodule is used to force updates.
#001 : 001
The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0.
#010 : 010
The local reload signal from this submodule is used to force updates without regard to the state of LDOK.
#011 : 011
The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0.
#100 : 100
The local sync signal from this submodule is used to force updates.
#101 : 101
The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0.
#110 : 110
The external force signal, EXT_FORCE, from outside the PWM module causes updates.
#111 : 111
The external sync signal, EXT_SYNC, from outside the PWM module causes updates.
End of enumeration elements list.
FORCE : Force Initialization
bits : 6 - 6 (1 bit)
access : write-only
FRCEN : This bit allows the CTRL2[FORCE] signal to initialize the counter without regard to the signal selected by CTRL2[INIT_SEL]
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Initialization from a FORCE_OUT is disabled.
#1 : 1
Initialization from a FORCE_OUT is enabled.
End of enumeration elements list.
INIT_SEL : Initialization Control Select
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
Local sync (PWM_X) causes initialization.
#01 : 01
Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs.
#10 : 10
Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0.
#11 : 11
EXT_SYNC causes initialization.
End of enumeration elements list.
PWMX_INIT : PWM_X Initial Value
bits : 10 - 10 (1 bit)
access : read-write
PWM45_INIT : PWM45 Initial Value
bits : 11 - 11 (1 bit)
access : read-write
PWM23_INIT : PWM23 Initial Value
bits : 12 - 12 (1 bit)
access : read-write
INDEP : Independent or Complementary Pair Operation
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_A and PWM_B form a complementary PWM pair.
#1 : 1
PWM_A and PWM_B outputs are independent PWMs.
End of enumeration elements list.
WAITEN : WAIT Enable
bits : 14 - 14 (1 bit)
access : read-write
DBGEN : Debug Enable
bits : 15 - 15 (1 bit)
access : read-write
Capture Value 3 Cycle Register
address_offset : 0x258 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CVAL3CYC : This read-only register stores the cycle number corresponding to the value captured in CVAL3
bits : 0 - 3 (4 bit)
access : read-only
Control Register
address_offset : 0x25E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBLEN : Double Switching Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Double switching disabled.
#1 : 1
Double switching enabled.
End of enumeration elements list.
DBLX : PWMX Double Switching Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMX double pulse disabled.
#1 : 1
PWMX double pulse enabled.
End of enumeration elements list.
LDMOD : Load Mode Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL0[LDOK] is set.
#1 : 1
Buffered registers of this submodule are loaded and take effect immediately upon MCTRL0[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF].
End of enumeration elements list.
PRSC : Prescaler
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 000
PWM clock frequency = fclk
#001 : 001
PWM clock frequency = fclk/2
#010 : 010
PWM clock frequency = fclk/4
#011 : 011
PWM clock frequency = fclk/8
#100 : 100
PWM clock frequency = fclk/16
#101 : 101
PWM clock frequency = fclk/32
#110 : 110
PWM clock frequency = fclk/64
#111 : 111
PWM clock frequency = fclk/128
End of enumeration elements list.
DT : Deadtime
bits : 8 - 9 (2 bit)
access : read-only
FULL : Full Cycle Reload
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Full-cycle reloads disabled.
#1 : 1
Full-cycle reloads enabled.
End of enumeration elements list.
HALF : Half Cycle Reload
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Half-cycle reloads disabled.
#1 : 1
Half-cycle reloads enabled.
End of enumeration elements list.
LDFQ : Load Frequency
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Every PWM opportunity
#0001 : 0001
Every 2 PWM opportunities
#0010 : 0010
Every 3 PWM opportunities
#0011 : 0011
Every 4 PWM opportunities
#0100 : 0100
Every 5 PWM opportunities
#0101 : 0101
Every 6 PWM opportunities
#0110 : 0110
Every 7 PWM opportunities
#0111 : 0111
Every 8 PWM opportunities
#1000 : 1000
Every 9 PWM opportunities
#1001 : 1001
Every 10 PWM opportunities
#1010 : 1010
Every 11 PWM opportunities
#1011 : 1011
Every 12 PWM opportunities
#1100 : 1100
Every 13 PWM opportunities
#1101 : 1101
Every 14 PWM opportunities
#1110 : 1110
Every 15 PWM opportunities
#1111 : 1111
Every 16 PWM opportunities
End of enumeration elements list.
Capture Value 4 Register
address_offset : 0x260 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPTVAL4 : This read-only register stores the value captured from the submodule counter
bits : 0 - 15 (16 bit)
access : read-only
Capture Value 4 Cycle Register
address_offset : 0x268 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CVAL4CYC : This read-only register stores the cycle number corresponding to the value captured in CVAL4
bits : 0 - 3 (4 bit)
access : read-only
Capture Value 5 Register
address_offset : 0x270 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPTVAL5 : This read-only register stores the value captured from the submodule counter
bits : 0 - 15 (16 bit)
access : read-only
Value Register 0
address_offset : 0x272 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL0 : Value Register 0
bits : 0 - 15 (16 bit)
access : read-write
Capture Value 5 Cycle Register
address_offset : 0x278 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CVAL5CYC : This read-only register stores the cycle number corresponding to the value captured in CVAL5
bits : 0 - 3 (4 bit)
access : read-only
Fractional Value Register 1
address_offset : 0x27C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL1 : Fractional Value 1 Register
bits : 11 - 15 (5 bit)
access : read-write
Fractional Value Register 3
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL3 : Fractional Value 3
bits : 11 - 15 (5 bit)
access : read-write
Value Register 1
address_offset : 0x286 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL1 : Value Register 1
bits : 0 - 15 (16 bit)
access : read-write
Fractional Value Register 2
address_offset : 0x290 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL2 : Fractional Value 2
bits : 11 - 15 (5 bit)
access : read-write
Value Register 2
address_offset : 0x29A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL2 : Value Register 2
bits : 0 - 15 (16 bit)
access : read-write
Fractional Value Register 3
address_offset : 0x2A4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL3 : Fractional Value 3
bits : 11 - 15 (5 bit)
access : read-write
Value Register 3
address_offset : 0x2AE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL3 : Value Register 3
bits : 0 - 15 (16 bit)
access : read-write
Fractional Value Register 4
address_offset : 0x2B8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL4 : Fractional Value 4
bits : 11 - 15 (5 bit)
access : read-write
Value Register 3
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL3 : Value Register 3
bits : 0 - 15 (16 bit)
access : read-write
Value Register 4
address_offset : 0x2C2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL4 : Value Register 4
bits : 0 - 15 (16 bit)
access : read-write
Fractional Value Register 5
address_offset : 0x2CC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL5 : Fractional Value 5
bits : 11 - 15 (5 bit)
access : read-write
Value Register 5
address_offset : 0x2D6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL5 : Value Register 5
bits : 0 - 15 (16 bit)
access : read-write
Fractional Control Register
address_offset : 0x2E0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRAC1_EN : Fractional Cycle PWM Period Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable fractional cycle length for the PWM period.
#1 : 1
Enable fractional cycle length for the PWM period.
End of enumeration elements list.
FRAC23_EN : Fractional Cycle Placement Enable for PWM_A
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable fractional cycle placement for PWM_A.
#1 : 1
Enable fractional cycle placement for PWM_A.
End of enumeration elements list.
FRAC45_EN : Fractional Cycle Placement Enable for PWM_B
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable fractional cycle placement for PWM_B.
#1 : 1
Enable fractional cycle placement for PWM_B.
End of enumeration elements list.
FRAC_PU : Fractional Delay Circuit Power Up
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Turn off fractional delay logic.
#1 : 1
Power up fractional delay logic.
End of enumeration elements list.
TEST : Test Status Bit
bits : 15 - 15 (1 bit)
access : read-only
Output Control Register
address_offset : 0x2EA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMXFS : PWM_X Fault State
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
Output is forced to logic 0 state prior to consideration of output polarity control.
#01 : 01
Output is forced to logic 1 state prior to consideration of output polarity control.
#10 : 10
Output is tristated.
#11 : 11
Output is tristated.
End of enumeration elements list.
PWMBFS : PWM_B Fault State
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
Output is forced to logic 0 state prior to consideration of output polarity control.
#01 : 01
Output is forced to logic 1 state prior to consideration of output polarity control.
#10 : 10
Output is tristated.
#11 : 11
Output is tristated.
End of enumeration elements list.
PWMAFS : PWM_A Fault State
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
Output is forced to logic 0 state prior to consideration of output polarity control.
#01 : 01
Output is forced to logic 1 state prior to consideration of output polarity control.
#10 : 10
Output is tristated.
#11 : 11
Output is tristated.
End of enumeration elements list.
POLX : PWM_X Output Polarity
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state.
#1 : 1
PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state.
End of enumeration elements list.
POLB : PWM_B Output Polarity
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state.
#1 : 1
PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state.
End of enumeration elements list.
POLA : PWM_A Output Polarity
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state.
#1 : 1
PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state.
End of enumeration elements list.
PWMX_IN : PWM_X Input
bits : 13 - 13 (1 bit)
access : read-only
PWMB_IN : PWM_B Input
bits : 14 - 14 (1 bit)
access : read-only
PWMA_IN : PWM_A Input
bits : 15 - 15 (1 bit)
access : read-only
Status Register
address_offset : 0x2F4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPF : Compare Flags
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
No compare event has occurred for a particular VALx value.
#1 : 1
A compare event has occurred for a particular VALx value.
End of enumeration elements list.
CFX0 : Capture Flag X0
bits : 6 - 6 (1 bit)
access : read-write
CFX1 : Capture Flag X1
bits : 7 - 7 (1 bit)
access : read-write
CFB0 : Capture Flag B0
bits : 8 - 8 (1 bit)
access : read-write
CFB1 : Capture Flag B1
bits : 9 - 9 (1 bit)
access : read-write
CFA0 : Capture Flag A0
bits : 10 - 10 (1 bit)
access : read-write
CFA1 : Capture Flag A1
bits : 11 - 11 (1 bit)
access : read-write
RF : Reload Flag
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No new reload cycle since last STS[RF] clearing
#1 : 1
New reload cycle since last STS[RF] clearing
End of enumeration elements list.
REF : Reload Error Flag
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reload error occurred.
#1 : 1
Reload signal occurred with non-coherent data and MCTRL0[LDOK] = 0.
End of enumeration elements list.
RUF : Registers Updated Flag
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
#0 : 0
No register update has occurred since last reload.
#1 : 1
At least one of the double buffered registers has been updated since the last reload.
End of enumeration elements list.
Interrupt Enable Register
address_offset : 0x2FE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPIE : Compare Interrupt Enables
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding STS[CMPF] bit will not cause an interrupt request.
#1 : 1
The corresponding STS[CMPF] bit will cause an interrupt request.
End of enumeration elements list.
CX0IE : Capture X 0 Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt request disabled for STS[CFX0].
#1 : 1
Interrupt request enabled for STS[CFX0].
End of enumeration elements list.
CX1IE : Capture X 1 Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt request disabled for STS[CFX1].
#1 : 1
Interrupt request enabled for STS[CFX1].
End of enumeration elements list.
CB0IE : Capture B 0 Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt request disabled for STS[CFB0].
#1 : 1
Interrupt request enabled for STS[CFB0].
End of enumeration elements list.
CB1IE : Capture B 1 Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt request disabled for STS[CFB1].
#1 : 1
Interrupt request enabled for STS[CFB1].
End of enumeration elements list.
CA0IE : Capture A 0 Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt request disabled for STS[CFA0].
#1 : 1
Interrupt request enabled for STS[CFA0].
End of enumeration elements list.
CA1IE : Capture A 1 Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt request disabled for STS[CFA1].
#1 : 1
Interrupt request enabled for STS[CFA1].
End of enumeration elements list.
RIE : Reload Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
STS[RF] CPU interrupt requests disabled
#1 : 1
STS[RF] CPU interrupt requests enabled
End of enumeration elements list.
REIE : Reload Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
STS[REF] CPU interrupt requests disabled
#1 : 1
STS[REF] CPU interrupt requests enabled
End of enumeration elements list.
Fractional Value Register 4
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL4 : Fractional Value 4
bits : 11 - 15 (5 bit)
access : read-write
DMA Enable Register
address_offset : 0x308 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CX0DE : Capture X0 FIFO DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
CX1DE : Capture X1 FIFO DMA Enable
bits : 1 - 1 (1 bit)
access : read-write
CB0DE : Capture B0 FIFO DMA Enable
bits : 2 - 2 (1 bit)
access : read-write
CB1DE : Capture B1 FIFO DMA Enable
bits : 3 - 3 (1 bit)
access : read-write
CA0DE : Capture A0 FIFO DMA Enable
bits : 4 - 4 (1 bit)
access : read-write
CA1DE : Capture A1 FIFO DMA Enable
bits : 5 - 5 (1 bit)
access : read-write
CAPTDE : Capture DMA Enable Source Select
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
Read DMA requests disabled.
#01 : 01
Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive.
#10 : 10
A local sync (VAL1 matches counter) sets the read DMA request.
#11 : 11
A local reload (STS[RF] being set) sets the read DMA request.
End of enumeration elements list.
FAND : FIFO Watermark AND Control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Selected FIFO watermarks are OR'ed together.
#1 : 1
Selected FIFO watermarks are AND'ed together.
End of enumeration elements list.
VALDE : Value Registers DMA Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA write requests disabled
#1 : 1
DMA write requests for the VALx and FRACVALx registers enabled
End of enumeration elements list.
Output Trigger Control Register
address_offset : 0x312 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT_TRIG_EN : Output Trigger Enables
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
PWM_OUT_TRIGx will not set when the counter value matches the VALx value.
#1 : 1
PWM_OUT_TRIGx will set when the counter value matches the VALx value.
End of enumeration elements list.
TRGFRQ : Trigger frequency
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.
#1 : 1
Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.
End of enumeration elements list.
PWBOT1 : Output Trigger 1 Source Select
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port.
#1 : 1
Route the PWM1 output to the PWM_OUT_TRIG1 port.
End of enumeration elements list.
PWAOT0 : Output Trigger 0 Source Select
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port.
#1 : 1
Route the PWM0 output to the PWM_OUT_TRIG0 port.
End of enumeration elements list.
Fault Disable Mapping Register 0
address_offset : 0x31C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIS0A : PWM_A Fault Disable Mask 0
bits : 0 - 3 (4 bit)
access : read-write
DIS0B : PWM_B Fault Disable Mask 0
bits : 4 - 7 (4 bit)
access : read-write
DIS0X : PWM_X Fault Disable Mask 0
bits : 8 - 11 (4 bit)
access : read-write
Deadtime Count Register 0
address_offset : 0x330 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTCNT0 : The DTCNT0 field is interpreted differently depending on whether or not the fractional delays are being used (FRCNTRL[FRAC23_EN] is set)
bits : 0 - 15 (16 bit)
access : read-write
Deadtime Count Register 1
address_offset : 0x33A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTCNT1 : The DTCNT1 field is interpreted differently depending on whether or not the fractional delays are being used (FRCNTRL[FRAC45_EN] is set)
bits : 0 - 15 (16 bit)
access : read-write
Value Register 4
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL4 : Value Register 4
bits : 0 - 15 (16 bit)
access : read-write
Capture Control A Register
address_offset : 0x344 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARMA : Arm A
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Input capture operation is disabled.
#1 : 1
Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled.
End of enumeration elements list.
ONESHOTA : One Shot Mode A
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit.
#1 : 1
One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared.
End of enumeration elements list.
EDGA0 : Edge A 0
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
Disabled
#01 : 01
Capture falling edges
#10 : 10
Capture rising edges
#11 : 11
Capture any edge
End of enumeration elements list.
EDGA1 : Edge A 1
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
Disabled
#01 : 01
Capture falling edges
#10 : 10
Capture rising edges
#11 : 11
Capture any edge
End of enumeration elements list.
INP_SELA : Input Select A
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Raw PWM_A input signal selected as source.
#1 : 1
Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers.
End of enumeration elements list.
EDGCNTA_EN : Edge Counter A Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge counter disabled and held in reset
#1 : 1
Edge counter enabled
End of enumeration elements list.
CFAWM : Capture A FIFOs Water Mark
bits : 8 - 9 (2 bit)
access : read-write
CA0CNT : Capture A0 FIFO Word Count
bits : 10 - 12 (3 bit)
access : read-only
CA1CNT : Capture A1 FIFO Word Count
bits : 13 - 15 (3 bit)
access : read-only
Capture Compare A Register
address_offset : 0x34E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGCMPA : Edge Compare A
bits : 0 - 7 (8 bit)
access : read-write
EDGCNTA : Edge Counter A
bits : 8 - 15 (8 bit)
access : read-only
Capture Control B Register
address_offset : 0x358 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARMB : Arm B
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Input capture operation is disabled.
#1 : 1
Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled.
End of enumeration elements list.
ONESHOTB : One Shot Mode B
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit.
#1 : 1
One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared.
End of enumeration elements list.
EDGB0 : Edge B 0
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
Disabled
#01 : 01
Capture falling edges
#10 : 10
Capture rising edges
#11 : 11
Capture any edge
End of enumeration elements list.
EDGB1 : Edge B 1
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
Disabled
#01 : 01
Capture falling edges
#10 : 10
Capture rising edges
#11 : 11
Capture any edge
End of enumeration elements list.
INP_SELB : Input Select B
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Raw PWM_B input signal selected as source.
#1 : 1
Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers.
End of enumeration elements list.
EDGCNTB_EN : Edge Counter B Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge counter disabled and held in reset
#1 : 1
Edge counter enabled
End of enumeration elements list.
CFBWM : Capture B FIFOs Water Mark
bits : 8 - 9 (2 bit)
access : read-write
CB0CNT : Capture B0 FIFO Word Count
bits : 10 - 12 (3 bit)
access : read-only
CB1CNT : Capture B1 FIFO Word Count
bits : 13 - 15 (3 bit)
access : read-only
Capture Compare B Register
address_offset : 0x362 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGCMPB : Edge Compare B
bits : 0 - 7 (8 bit)
access : read-write
EDGCNTB : Edge Counter B
bits : 8 - 15 (8 bit)
access : read-only
Capture Control X Register
address_offset : 0x36C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARMX : Arm X
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Input capture operation is disabled.
#1 : 1
Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.
End of enumeration elements list.
ONESHOTX : One Shot Mode Aux
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit.
#1 : 1
One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared.
End of enumeration elements list.
EDGX0 : Edge X 0
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
Disabled
#01 : 01
Capture falling edges
#10 : 10
Capture rising edges
#11 : 11
Capture any edge
End of enumeration elements list.
EDGX1 : Edge X 1
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
Disabled
#01 : 01
Capture falling edges
#10 : 10
Capture rising edges
#11 : 11
Capture any edge
End of enumeration elements list.
INP_SELX : Input Select X
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Raw PWM_X input signal selected as source.
#1 : 1
Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers.
End of enumeration elements list.
EDGCNTX_EN : Edge Counter X Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge counter disabled and held in reset
#1 : 1
Edge counter enabled
End of enumeration elements list.
CFXWM : Capture X FIFOs Water Mark
bits : 8 - 9 (2 bit)
access : read-write
CX0CNT : Capture X0 FIFO Word Count
bits : 10 - 12 (3 bit)
access : read-only
CX1CNT : Capture X1 FIFO Word Count
bits : 13 - 15 (3 bit)
access : read-only
Capture Compare X Register
address_offset : 0x376 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGCMPX : Edge Compare X
bits : 0 - 7 (8 bit)
access : read-write
EDGCNTX : Edge Counter X
bits : 8 - 15 (8 bit)
access : read-only
Fractional Value Register 5
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL5 : Fractional Value 5
bits : 11 - 15 (5 bit)
access : read-write
Capture Value 0 Register
address_offset : 0x380 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPTVAL0 : This read-only register stores the value captured from the submodule counter
bits : 0 - 15 (16 bit)
access : read-only
Capture Value 0 Cycle Register
address_offset : 0x38A Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CVAL0CYC : This read-only register stores the cycle number corresponding to the value captured in CVAL0
bits : 0 - 3 (4 bit)
access : read-only
Capture Value 1 Register
address_offset : 0x394 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPTVAL1 : This read-only register stores the value captured from the submodule counter
bits : 0 - 15 (16 bit)
access : read-only
Capture Value 1 Cycle Register
address_offset : 0x39E Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CVAL1CYC : This read-only register stores the cycle number corresponding to the value captured in CVAL1
bits : 0 - 3 (4 bit)
access : read-only
Capture Value 2 Register
address_offset : 0x3A8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPTVAL2 : This read-only register stores the value captured from the submodule counter
bits : 0 - 15 (16 bit)
access : read-only
Capture Value 2 Cycle Register
address_offset : 0x3B2 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CVAL2CYC : This read-only register stores the cycle number corresponding to the value captured in CVAL2
bits : 0 - 3 (4 bit)
access : read-only
Capture Value 3 Register
address_offset : 0x3BC Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPTVAL3 : This read-only register stores the value captured from the submodule counter
bits : 0 - 15 (16 bit)
access : read-only
Value Register 5
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL5 : Value Register 5
bits : 0 - 15 (16 bit)
access : read-write
Capture Value 3 Cycle Register
address_offset : 0x3C6 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CVAL3CYC : This read-only register stores the cycle number corresponding to the value captured in CVAL3
bits : 0 - 3 (4 bit)
access : read-only
Capture Value 4 Register
address_offset : 0x3D0 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPTVAL4 : This read-only register stores the value captured from the submodule counter
bits : 0 - 15 (16 bit)
access : read-only
Capture Value 4 Cycle Register
address_offset : 0x3DA Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CVAL4CYC : This read-only register stores the cycle number corresponding to the value captured in CVAL4
bits : 0 - 3 (4 bit)
access : read-only
Capture Value 5 Register
address_offset : 0x3E4 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPTVAL5 : This read-only register stores the value captured from the submodule counter
bits : 0 - 15 (16 bit)
access : read-only
Capture Value 5 Cycle Register
address_offset : 0x3EE Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CVAL5CYC : This read-only register stores the cycle number corresponding to the value captured in CVAL5
bits : 0 - 3 (4 bit)
access : read-only
Initial Count Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT : Initial Count Register Bits
bits : 0 - 15 (16 bit)
access : read-write
Fractional Control Register
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRAC1_EN : Fractional Cycle PWM Period Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable fractional cycle length for the PWM period.
#1 : 1
Enable fractional cycle length for the PWM period.
End of enumeration elements list.
FRAC23_EN : Fractional Cycle Placement Enable for PWM_A
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable fractional cycle placement for PWM_A.
#1 : 1
Enable fractional cycle placement for PWM_A.
End of enumeration elements list.
FRAC45_EN : Fractional Cycle Placement Enable for PWM_B
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable fractional cycle placement for PWM_B.
#1 : 1
Enable fractional cycle placement for PWM_B.
End of enumeration elements list.
FRAC_PU : Fractional Delay Circuit Power Up
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Turn off fractional delay logic.
#1 : 1
Power up fractional delay logic.
End of enumeration elements list.
TEST : Test Status Bit
bits : 15 - 15 (1 bit)
access : read-only
Output Control Register
address_offset : 0x44 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMXFS : PWM_X Fault State
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
Output is forced to logic 0 state prior to consideration of output polarity control.
#01 : 01
Output is forced to logic 1 state prior to consideration of output polarity control.
#10 : 10
Output is tristated.
#11 : 11
Output is tristated.
End of enumeration elements list.
PWMBFS : PWM_B Fault State
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
Output is forced to logic 0 state prior to consideration of output polarity control.
#01 : 01
Output is forced to logic 1 state prior to consideration of output polarity control.
#10 : 10
Output is tristated.
#11 : 11
Output is tristated.
End of enumeration elements list.
PWMAFS : PWM_A Fault State
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
Output is forced to logic 0 state prior to consideration of output polarity control.
#01 : 01
Output is forced to logic 1 state prior to consideration of output polarity control.
#10 : 10
Output is tristated.
#11 : 11
Output is tristated.
End of enumeration elements list.
POLX : PWM_X Output Polarity
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state.
#1 : 1
PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state.
End of enumeration elements list.
POLB : PWM_B Output Polarity
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state.
#1 : 1
PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state.
End of enumeration elements list.
POLA : PWM_A Output Polarity
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state.
#1 : 1
PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state.
End of enumeration elements list.
PWMX_IN : PWM_X Input
bits : 13 - 13 (1 bit)
access : read-only
PWMB_IN : PWM_B Input
bits : 14 - 14 (1 bit)
access : read-only
PWMA_IN : PWM_A Input
bits : 15 - 15 (1 bit)
access : read-only
Status Register
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPF : Compare Flags
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
No compare event has occurred for a particular VALx value.
#1 : 1
A compare event has occurred for a particular VALx value.
End of enumeration elements list.
CFX0 : Capture Flag X0
bits : 6 - 6 (1 bit)
access : read-write
CFX1 : Capture Flag X1
bits : 7 - 7 (1 bit)
access : read-write
CFB0 : Capture Flag B0
bits : 8 - 8 (1 bit)
access : read-write
CFB1 : Capture Flag B1
bits : 9 - 9 (1 bit)
access : read-write
CFA0 : Capture Flag A0
bits : 10 - 10 (1 bit)
access : read-write
CFA1 : Capture Flag A1
bits : 11 - 11 (1 bit)
access : read-write
RF : Reload Flag
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No new reload cycle since last STS[RF] clearing
#1 : 1
New reload cycle since last STS[RF] clearing
End of enumeration elements list.
REF : Reload Error Flag
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reload error occurred.
#1 : 1
Reload signal occurred with non-coherent data and MCTRL0[LDOK] = 0.
End of enumeration elements list.
RUF : Registers Updated Flag
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
#0 : 0
No register update has occurred since last reload.
#1 : 1
At least one of the double buffered registers has been updated since the last reload.
End of enumeration elements list.
Interrupt Enable Register
address_offset : 0x4C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPIE : Compare Interrupt Enables
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding STS[CMPF] bit will not cause an interrupt request.
#1 : 1
The corresponding STS[CMPF] bit will cause an interrupt request.
End of enumeration elements list.
CX0IE : Capture X 0 Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt request disabled for STS[CFX0].
#1 : 1
Interrupt request enabled for STS[CFX0].
End of enumeration elements list.
CX1IE : Capture X 1 Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt request disabled for STS[CFX1].
#1 : 1
Interrupt request enabled for STS[CFX1].
End of enumeration elements list.
CB0IE : Capture B 0 Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt request disabled for STS[CFB0].
#1 : 1
Interrupt request enabled for STS[CFB0].
End of enumeration elements list.
CB1IE : Capture B 1 Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt request disabled for STS[CFB1].
#1 : 1
Interrupt request enabled for STS[CFB1].
End of enumeration elements list.
CA0IE : Capture A 0 Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt request disabled for STS[CFA0].
#1 : 1
Interrupt request enabled for STS[CFA0].
End of enumeration elements list.
CA1IE : Capture A 1 Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt request disabled for STS[CFA1].
#1 : 1
Interrupt request enabled for STS[CFA1].
End of enumeration elements list.
RIE : Reload Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
STS[RF] CPU interrupt requests disabled
#1 : 1
STS[RF] CPU interrupt requests enabled
End of enumeration elements list.
REIE : Reload Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
STS[REF] CPU interrupt requests disabled
#1 : 1
STS[REF] CPU interrupt requests enabled
End of enumeration elements list.
DMA Enable Register
address_offset : 0x50 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CX0DE : Capture X0 FIFO DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
CX1DE : Capture X1 FIFO DMA Enable
bits : 1 - 1 (1 bit)
access : read-write
CB0DE : Capture B0 FIFO DMA Enable
bits : 2 - 2 (1 bit)
access : read-write
CB1DE : Capture B1 FIFO DMA Enable
bits : 3 - 3 (1 bit)
access : read-write
CA0DE : Capture A0 FIFO DMA Enable
bits : 4 - 4 (1 bit)
access : read-write
CA1DE : Capture A1 FIFO DMA Enable
bits : 5 - 5 (1 bit)
access : read-write
CAPTDE : Capture DMA Enable Source Select
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
Read DMA requests disabled.
#01 : 01
Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive.
#10 : 10
A local sync (VAL1 matches counter) sets the read DMA request.
#11 : 11
A local reload (STS[RF] being set) sets the read DMA request.
End of enumeration elements list.
FAND : FIFO Watermark AND Control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Selected FIFO watermarks are OR'ed together.
#1 : 1
Selected FIFO watermarks are AND'ed together.
End of enumeration elements list.
VALDE : Value Registers DMA Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA write requests disabled
#1 : 1
DMA write requests for the VALx and FRACVALx registers enabled
End of enumeration elements list.
Output Trigger Control Register
address_offset : 0x54 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT_TRIG_EN : Output Trigger Enables
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
PWM_OUT_TRIGx will not set when the counter value matches the VALx value.
#1 : 1
PWM_OUT_TRIGx will set when the counter value matches the VALx value.
End of enumeration elements list.
TRGFRQ : Trigger frequency
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.
#1 : 1
Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.
End of enumeration elements list.
PWBOT1 : Output Trigger 1 Source Select
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port.
#1 : 1
Route the PWM1 output to the PWM_OUT_TRIG1 port.
End of enumeration elements list.
PWAOT0 : Output Trigger 0 Source Select
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port.
#1 : 1
Route the PWM0 output to the PWM_OUT_TRIG0 port.
End of enumeration elements list.
Fault Disable Mapping Register 0
address_offset : 0x58 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIS0A : PWM_A Fault Disable Mask 0
bits : 0 - 3 (4 bit)
access : read-write
DIS0B : PWM_B Fault Disable Mask 0
bits : 4 - 7 (4 bit)
access : read-write
DIS0X : PWM_X Fault Disable Mask 0
bits : 8 - 11 (4 bit)
access : read-write
Counter Register
address_offset : 0x60 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Counter Register Bits
bits : 0 - 15 (16 bit)
access : read-only
Deadtime Count Register 0
address_offset : 0x60 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTCNT0 : The DTCNT0 field is interpreted differently depending on whether or not the fractional delays are being used (FRCNTRL[FRAC23_EN] is set)
bits : 0 - 15 (16 bit)
access : read-write
Deadtime Count Register 1
address_offset : 0x64 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTCNT1 : The DTCNT1 field is interpreted differently depending on whether or not the fractional delays are being used (FRCNTRL[FRAC45_EN] is set)
bits : 0 - 15 (16 bit)
access : read-write
Initial Count Register
address_offset : 0x66 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT : Initial Count Register Bits
bits : 0 - 15 (16 bit)
access : read-write
Capture Control A Register
address_offset : 0x68 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARMA : Arm A
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Input capture operation is disabled.
#1 : 1
Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled.
End of enumeration elements list.
ONESHOTA : One Shot Mode A
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit.
#1 : 1
One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared.
End of enumeration elements list.
EDGA0 : Edge A 0
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
Disabled
#01 : 01
Capture falling edges
#10 : 10
Capture rising edges
#11 : 11
Capture any edge
End of enumeration elements list.
EDGA1 : Edge A 1
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
Disabled
#01 : 01
Capture falling edges
#10 : 10
Capture rising edges
#11 : 11
Capture any edge
End of enumeration elements list.
INP_SELA : Input Select A
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Raw PWM_A input signal selected as source.
#1 : 1
Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers.
End of enumeration elements list.
EDGCNTA_EN : Edge Counter A Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge counter disabled and held in reset
#1 : 1
Edge counter enabled
End of enumeration elements list.
CFAWM : Capture A FIFOs Water Mark
bits : 8 - 9 (2 bit)
access : read-write
CA0CNT : Capture A0 FIFO Word Count
bits : 10 - 12 (3 bit)
access : read-only
CA1CNT : Capture A1 FIFO Word Count
bits : 13 - 15 (3 bit)
access : read-only
Control 2 Register
address_offset : 0x6C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_SEL : Clock Source Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
The IPBus clock is used as the clock for the local prescaler and counter.
#01 : 01
EXT_CLK is used as the clock for the local prescaler and counter.
#10 : 10
Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0.
End of enumeration elements list.
RELOAD_SEL : Reload Source Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The local RELOAD signal is used to reload registers.
#1 : 1
The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0.
End of enumeration elements list.
FORCE_SEL : This read/write bit determines the source of the FORCE OUTPUT signal for this submodule.
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#000 : 000
The local force signal, CTRL2[FORCE], from this submodule is used to force updates.
#001 : 001
The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0.
#010 : 010
The local reload signal from this submodule is used to force updates without regard to the state of LDOK.
#011 : 011
The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0.
#100 : 100
The local sync signal from this submodule is used to force updates.
#101 : 101
The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0.
#110 : 110
The external force signal, EXT_FORCE, from outside the PWM module causes updates.
#111 : 111
The external sync signal, EXT_SYNC, from outside the PWM module causes updates.
End of enumeration elements list.
FORCE : Force Initialization
bits : 6 - 6 (1 bit)
access : write-only
FRCEN : This bit allows the CTRL2[FORCE] signal to initialize the counter without regard to the signal selected by CTRL2[INIT_SEL]
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Initialization from a FORCE_OUT is disabled.
#1 : 1
Initialization from a FORCE_OUT is enabled.
End of enumeration elements list.
INIT_SEL : Initialization Control Select
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
Local sync (PWM_X) causes initialization.
#01 : 01
Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs.
#10 : 10
Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0.
#11 : 11
EXT_SYNC causes initialization.
End of enumeration elements list.
PWMX_INIT : PWM_X Initial Value
bits : 10 - 10 (1 bit)
access : read-write
PWM45_INIT : PWM45 Initial Value
bits : 11 - 11 (1 bit)
access : read-write
PWM23_INIT : PWM23 Initial Value
bits : 12 - 12 (1 bit)
access : read-write
INDEP : Independent or Complementary Pair Operation
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_A and PWM_B form a complementary PWM pair.
#1 : 1
PWM_A and PWM_B outputs are independent PWMs.
End of enumeration elements list.
WAITEN : WAIT Enable
bits : 14 - 14 (1 bit)
access : read-write
DBGEN : Debug Enable
bits : 15 - 15 (1 bit)
access : read-write
Capture Compare A Register
address_offset : 0x6C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGCMPA : Edge Compare A
bits : 0 - 7 (8 bit)
access : read-write
EDGCNTA : Edge Counter A
bits : 8 - 15 (8 bit)
access : read-only
Capture Control B Register
address_offset : 0x70 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARMB : Arm B
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Input capture operation is disabled.
#1 : 1
Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled.
End of enumeration elements list.
ONESHOTB : One Shot Mode B
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit.
#1 : 1
One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared.
End of enumeration elements list.
EDGB0 : Edge B 0
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
Disabled
#01 : 01
Capture falling edges
#10 : 10
Capture rising edges
#11 : 11
Capture any edge
End of enumeration elements list.
EDGB1 : Edge B 1
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
Disabled
#01 : 01
Capture falling edges
#10 : 10
Capture rising edges
#11 : 11
Capture any edge
End of enumeration elements list.
INP_SELB : Input Select B
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Raw PWM_B input signal selected as source.
#1 : 1
Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers.
End of enumeration elements list.
EDGCNTB_EN : Edge Counter B Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge counter disabled and held in reset
#1 : 1
Edge counter enabled
End of enumeration elements list.
CFBWM : Capture B FIFOs Water Mark
bits : 8 - 9 (2 bit)
access : read-write
CB0CNT : Capture B0 FIFO Word Count
bits : 10 - 12 (3 bit)
access : read-only
CB1CNT : Capture B1 FIFO Word Count
bits : 13 - 15 (3 bit)
access : read-only
Control Register
address_offset : 0x72 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBLEN : Double Switching Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Double switching disabled.
#1 : 1
Double switching enabled.
End of enumeration elements list.
DBLX : PWMX Double Switching Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMX double pulse disabled.
#1 : 1
PWMX double pulse enabled.
End of enumeration elements list.
LDMOD : Load Mode Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL0[LDOK] is set.
#1 : 1
Buffered registers of this submodule are loaded and take effect immediately upon MCTRL0[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF].
End of enumeration elements list.
PRSC : Prescaler
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 000
PWM clock frequency = fclk
#001 : 001
PWM clock frequency = fclk/2
#010 : 010
PWM clock frequency = fclk/4
#011 : 011
PWM clock frequency = fclk/8
#100 : 100
PWM clock frequency = fclk/16
#101 : 101
PWM clock frequency = fclk/32
#110 : 110
PWM clock frequency = fclk/64
#111 : 111
PWM clock frequency = fclk/128
End of enumeration elements list.
DT : Deadtime
bits : 8 - 9 (2 bit)
access : read-only
FULL : Full Cycle Reload
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Full-cycle reloads disabled.
#1 : 1
Full-cycle reloads enabled.
End of enumeration elements list.
HALF : Half Cycle Reload
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Half-cycle reloads disabled.
#1 : 1
Half-cycle reloads enabled.
End of enumeration elements list.
LDFQ : Load Frequency
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Every PWM opportunity
#0001 : 0001
Every 2 PWM opportunities
#0010 : 0010
Every 3 PWM opportunities
#0011 : 0011
Every 4 PWM opportunities
#0100 : 0100
Every 5 PWM opportunities
#0101 : 0101
Every 6 PWM opportunities
#0110 : 0110
Every 7 PWM opportunities
#0111 : 0111
Every 8 PWM opportunities
#1000 : 1000
Every 9 PWM opportunities
#1001 : 1001
Every 10 PWM opportunities
#1010 : 1010
Every 11 PWM opportunities
#1011 : 1011
Every 12 PWM opportunities
#1100 : 1100
Every 13 PWM opportunities
#1101 : 1101
Every 14 PWM opportunities
#1110 : 1110
Every 15 PWM opportunities
#1111 : 1111
Every 16 PWM opportunities
End of enumeration elements list.
Capture Compare B Register
address_offset : 0x74 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGCMPB : Edge Compare B
bits : 0 - 7 (8 bit)
access : read-write
EDGCNTB : Edge Counter B
bits : 8 - 15 (8 bit)
access : read-only
Capture Control X Register
address_offset : 0x78 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARMX : Arm X
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Input capture operation is disabled.
#1 : 1
Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.
End of enumeration elements list.
ONESHOTX : One Shot Mode Aux
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit.
#1 : 1
One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared.
End of enumeration elements list.
EDGX0 : Edge X 0
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
Disabled
#01 : 01
Capture falling edges
#10 : 10
Capture rising edges
#11 : 11
Capture any edge
End of enumeration elements list.
EDGX1 : Edge X 1
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
Disabled
#01 : 01
Capture falling edges
#10 : 10
Capture rising edges
#11 : 11
Capture any edge
End of enumeration elements list.
INP_SELX : Input Select X
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Raw PWM_X input signal selected as source.
#1 : 1
Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers.
End of enumeration elements list.
EDGCNTX_EN : Edge Counter X Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge counter disabled and held in reset
#1 : 1
Edge counter enabled
End of enumeration elements list.
CFXWM : Capture X FIFOs Water Mark
bits : 8 - 9 (2 bit)
access : read-write
CX0CNT : Capture X0 FIFO Word Count
bits : 10 - 12 (3 bit)
access : read-only
CX1CNT : Capture X1 FIFO Word Count
bits : 13 - 15 (3 bit)
access : read-only
Capture Compare X Register
address_offset : 0x7C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGCMPX : Edge Compare X
bits : 0 - 7 (8 bit)
access : read-write
EDGCNTX : Edge Counter X
bits : 8 - 15 (8 bit)
access : read-only
Value Register 0
address_offset : 0x7E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL0 : Value Register 0
bits : 0 - 15 (16 bit)
access : read-write
Control 2 Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_SEL : Clock Source Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
The IPBus clock is used as the clock for the local prescaler and counter.
#01 : 01
EXT_CLK is used as the clock for the local prescaler and counter.
#10 : 10
Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0.
End of enumeration elements list.
RELOAD_SEL : Reload Source Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The local RELOAD signal is used to reload registers.
#1 : 1
The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0.
End of enumeration elements list.
FORCE_SEL : This read/write bit determines the source of the FORCE OUTPUT signal for this submodule.
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#000 : 000
The local force signal, CTRL2[FORCE], from this submodule is used to force updates.
#001 : 001
The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0.
#010 : 010
The local reload signal from this submodule is used to force updates without regard to the state of LDOK.
#011 : 011
The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0.
#100 : 100
The local sync signal from this submodule is used to force updates.
#101 : 101
The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0.
#110 : 110
The external force signal, EXT_FORCE, from outside the PWM module causes updates.
#111 : 111
The external sync signal, EXT_SYNC, from outside the PWM module causes updates.
End of enumeration elements list.
FORCE : Force Initialization
bits : 6 - 6 (1 bit)
access : write-only
FRCEN : This bit allows the CTRL2[FORCE] signal to initialize the counter without regard to the signal selected by CTRL2[INIT_SEL]
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Initialization from a FORCE_OUT is disabled.
#1 : 1
Initialization from a FORCE_OUT is enabled.
End of enumeration elements list.
INIT_SEL : Initialization Control Select
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
Local sync (PWM_X) causes initialization.
#01 : 01
Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs.
#10 : 10
Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0.
#11 : 11
EXT_SYNC causes initialization.
End of enumeration elements list.
PWMX_INIT : PWM_X Initial Value
bits : 10 - 10 (1 bit)
access : read-write
PWM45_INIT : PWM45 Initial Value
bits : 11 - 11 (1 bit)
access : read-write
PWM23_INIT : PWM23 Initial Value
bits : 12 - 12 (1 bit)
access : read-write
INDEP : Independent or Complementary Pair Operation
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_A and PWM_B form a complementary PWM pair.
#1 : 1
PWM_A and PWM_B outputs are independent PWMs.
End of enumeration elements list.
WAITEN : WAIT Enable
bits : 14 - 14 (1 bit)
access : read-write
DBGEN : Debug Enable
bits : 15 - 15 (1 bit)
access : read-write
Capture Value 0 Register
address_offset : 0x80 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPTVAL0 : This read-only register stores the value captured from the submodule counter
bits : 0 - 15 (16 bit)
access : read-only
Fractional Value Register 1
address_offset : 0x84 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL1 : Fractional Value 1 Register
bits : 11 - 15 (5 bit)
access : read-write
Capture Value 0 Cycle Register
address_offset : 0x84 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CVAL0CYC : This read-only register stores the cycle number corresponding to the value captured in CVAL0
bits : 0 - 3 (4 bit)
access : read-only
Capture Value 1 Register
address_offset : 0x88 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPTVAL1 : This read-only register stores the value captured from the submodule counter
bits : 0 - 15 (16 bit)
access : read-only
Value Register 1
address_offset : 0x8A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL1 : Value Register 1
bits : 0 - 15 (16 bit)
access : read-write
Capture Value 1 Cycle Register
address_offset : 0x8C Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CVAL1CYC : This read-only register stores the cycle number corresponding to the value captured in CVAL1
bits : 0 - 3 (4 bit)
access : read-only
Fractional Value Register 2
address_offset : 0x90 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL2 : Fractional Value 2
bits : 11 - 15 (5 bit)
access : read-write
Capture Value 2 Register
address_offset : 0x90 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPTVAL2 : This read-only register stores the value captured from the submodule counter
bits : 0 - 15 (16 bit)
access : read-only
Capture Value 2 Cycle Register
address_offset : 0x94 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CVAL2CYC : This read-only register stores the cycle number corresponding to the value captured in CVAL2
bits : 0 - 3 (4 bit)
access : read-only
Value Register 2
address_offset : 0x96 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL2 : Value Register 2
bits : 0 - 15 (16 bit)
access : read-write
Capture Value 3 Register
address_offset : 0x98 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPTVAL3 : This read-only register stores the value captured from the submodule counter
bits : 0 - 15 (16 bit)
access : read-only
Fractional Value Register 3
address_offset : 0x9C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL3 : Fractional Value 3
bits : 11 - 15 (5 bit)
access : read-write
Capture Value 3 Cycle Register
address_offset : 0x9C Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CVAL3CYC : This read-only register stores the cycle number corresponding to the value captured in CVAL3
bits : 0 - 3 (4 bit)
access : read-only
Capture Value 4 Register
address_offset : 0xA0 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPTVAL4 : This read-only register stores the value captured from the submodule counter
bits : 0 - 15 (16 bit)
access : read-only
Value Register 3
address_offset : 0xA2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL3 : Value Register 3
bits : 0 - 15 (16 bit)
access : read-write
Capture Value 4 Cycle Register
address_offset : 0xA4 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CVAL4CYC : This read-only register stores the cycle number corresponding to the value captured in CVAL4
bits : 0 - 3 (4 bit)
access : read-only
Fractional Value Register 4
address_offset : 0xA8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL4 : Fractional Value 4
bits : 11 - 15 (5 bit)
access : read-write
Capture Value 5 Register
address_offset : 0xA8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPTVAL5 : This read-only register stores the value captured from the submodule counter
bits : 0 - 15 (16 bit)
access : read-only
Capture Value 5 Cycle Register
address_offset : 0xAC Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CVAL5CYC : This read-only register stores the cycle number corresponding to the value captured in CVAL5
bits : 0 - 3 (4 bit)
access : read-only
Value Register 4
address_offset : 0xAE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL4 : Value Register 4
bits : 0 - 15 (16 bit)
access : read-write
Fractional Value Register 5
address_offset : 0xB4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL5 : Fractional Value 5
bits : 11 - 15 (5 bit)
access : read-write
Value Register 5
address_offset : 0xBA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL5 : Value Register 5
bits : 0 - 15 (16 bit)
access : read-write
Control Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBLEN : Double Switching Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Double switching disabled.
#1 : 1
Double switching enabled.
End of enumeration elements list.
DBLX : PWMX Double Switching Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMX double pulse disabled.
#1 : 1
PWMX double pulse enabled.
End of enumeration elements list.
LDMOD : Load Mode Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL0[LDOK] is set.
#1 : 1
Buffered registers of this submodule are loaded and take effect immediately upon MCTRL0[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF].
End of enumeration elements list.
PRSC : Prescaler
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 000
PWM clock frequency = fclk
#001 : 001
PWM clock frequency = fclk/2
#010 : 010
PWM clock frequency = fclk/4
#011 : 011
PWM clock frequency = fclk/8
#100 : 100
PWM clock frequency = fclk/16
#101 : 101
PWM clock frequency = fclk/32
#110 : 110
PWM clock frequency = fclk/64
#111 : 111
PWM clock frequency = fclk/128
End of enumeration elements list.
DT : Deadtime
bits : 8 - 9 (2 bit)
access : read-only
FULL : Full Cycle Reload
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Full-cycle reloads disabled.
#1 : 1
Full-cycle reloads enabled.
End of enumeration elements list.
HALF : Half Cycle Reload
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Half-cycle reloads disabled.
#1 : 1
Half-cycle reloads enabled.
End of enumeration elements list.
LDFQ : Load Frequency
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Every PWM opportunity
#0001 : 0001
Every 2 PWM opportunities
#0010 : 0010
Every 3 PWM opportunities
#0011 : 0011
Every 4 PWM opportunities
#0100 : 0100
Every 5 PWM opportunities
#0101 : 0101
Every 6 PWM opportunities
#0110 : 0110
Every 7 PWM opportunities
#0111 : 0111
Every 8 PWM opportunities
#1000 : 1000
Every 9 PWM opportunities
#1001 : 1001
Every 10 PWM opportunities
#1010 : 1010
Every 11 PWM opportunities
#1011 : 1011
Every 12 PWM opportunities
#1100 : 1100
Every 13 PWM opportunities
#1101 : 1101
Every 14 PWM opportunities
#1110 : 1110
Every 15 PWM opportunities
#1111 : 1111
Every 16 PWM opportunities
End of enumeration elements list.
Fractional Control Register
address_offset : 0xC0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRAC1_EN : Fractional Cycle PWM Period Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable fractional cycle length for the PWM period.
#1 : 1
Enable fractional cycle length for the PWM period.
End of enumeration elements list.
FRAC23_EN : Fractional Cycle Placement Enable for PWM_A
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable fractional cycle placement for PWM_A.
#1 : 1
Enable fractional cycle placement for PWM_A.
End of enumeration elements list.
FRAC45_EN : Fractional Cycle Placement Enable for PWM_B
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable fractional cycle placement for PWM_B.
#1 : 1
Enable fractional cycle placement for PWM_B.
End of enumeration elements list.
FRAC_PU : Fractional Delay Circuit Power Up
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Turn off fractional delay logic.
#1 : 1
Power up fractional delay logic.
End of enumeration elements list.
TEST : Test Status Bit
bits : 15 - 15 (1 bit)
access : read-only
Output Control Register
address_offset : 0xC6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMXFS : PWM_X Fault State
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
Output is forced to logic 0 state prior to consideration of output polarity control.
#01 : 01
Output is forced to logic 1 state prior to consideration of output polarity control.
#10 : 10
Output is tristated.
#11 : 11
Output is tristated.
End of enumeration elements list.
PWMBFS : PWM_B Fault State
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
Output is forced to logic 0 state prior to consideration of output polarity control.
#01 : 01
Output is forced to logic 1 state prior to consideration of output polarity control.
#10 : 10
Output is tristated.
#11 : 11
Output is tristated.
End of enumeration elements list.
PWMAFS : PWM_A Fault State
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
Output is forced to logic 0 state prior to consideration of output polarity control.
#01 : 01
Output is forced to logic 1 state prior to consideration of output polarity control.
#10 : 10
Output is tristated.
#11 : 11
Output is tristated.
End of enumeration elements list.
POLX : PWM_X Output Polarity
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state.
#1 : 1
PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state.
End of enumeration elements list.
POLB : PWM_B Output Polarity
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state.
#1 : 1
PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state.
End of enumeration elements list.
POLA : PWM_A Output Polarity
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state.
#1 : 1
PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state.
End of enumeration elements list.
PWMX_IN : PWM_X Input
bits : 13 - 13 (1 bit)
access : read-only
PWMB_IN : PWM_B Input
bits : 14 - 14 (1 bit)
access : read-only
PWMA_IN : PWM_A Input
bits : 15 - 15 (1 bit)
access : read-only
Status Register
address_offset : 0xCC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPF : Compare Flags
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
No compare event has occurred for a particular VALx value.
#1 : 1
A compare event has occurred for a particular VALx value.
End of enumeration elements list.
CFX0 : Capture Flag X0
bits : 6 - 6 (1 bit)
access : read-write
CFX1 : Capture Flag X1
bits : 7 - 7 (1 bit)
access : read-write
CFB0 : Capture Flag B0
bits : 8 - 8 (1 bit)
access : read-write
CFB1 : Capture Flag B1
bits : 9 - 9 (1 bit)
access : read-write
CFA0 : Capture Flag A0
bits : 10 - 10 (1 bit)
access : read-write
CFA1 : Capture Flag A1
bits : 11 - 11 (1 bit)
access : read-write
RF : Reload Flag
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No new reload cycle since last STS[RF] clearing
#1 : 1
New reload cycle since last STS[RF] clearing
End of enumeration elements list.
REF : Reload Error Flag
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reload error occurred.
#1 : 1
Reload signal occurred with non-coherent data and MCTRL0[LDOK] = 0.
End of enumeration elements list.
RUF : Registers Updated Flag
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
#0 : 0
No register update has occurred since last reload.
#1 : 1
At least one of the double buffered registers has been updated since the last reload.
End of enumeration elements list.
Interrupt Enable Register
address_offset : 0xD2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPIE : Compare Interrupt Enables
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding STS[CMPF] bit will not cause an interrupt request.
#1 : 1
The corresponding STS[CMPF] bit will cause an interrupt request.
End of enumeration elements list.
CX0IE : Capture X 0 Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt request disabled for STS[CFX0].
#1 : 1
Interrupt request enabled for STS[CFX0].
End of enumeration elements list.
CX1IE : Capture X 1 Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt request disabled for STS[CFX1].
#1 : 1
Interrupt request enabled for STS[CFX1].
End of enumeration elements list.
CB0IE : Capture B 0 Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt request disabled for STS[CFB0].
#1 : 1
Interrupt request enabled for STS[CFB0].
End of enumeration elements list.
CB1IE : Capture B 1 Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt request disabled for STS[CFB1].
#1 : 1
Interrupt request enabled for STS[CFB1].
End of enumeration elements list.
CA0IE : Capture A 0 Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt request disabled for STS[CFA0].
#1 : 1
Interrupt request enabled for STS[CFA0].
End of enumeration elements list.
CA1IE : Capture A 1 Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt request disabled for STS[CFA1].
#1 : 1
Interrupt request enabled for STS[CFA1].
End of enumeration elements list.
RIE : Reload Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
STS[RF] CPU interrupt requests disabled
#1 : 1
STS[RF] CPU interrupt requests enabled
End of enumeration elements list.
REIE : Reload Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
STS[REF] CPU interrupt requests disabled
#1 : 1
STS[REF] CPU interrupt requests enabled
End of enumeration elements list.
DMA Enable Register
address_offset : 0xD8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CX0DE : Capture X0 FIFO DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
CX1DE : Capture X1 FIFO DMA Enable
bits : 1 - 1 (1 bit)
access : read-write
CB0DE : Capture B0 FIFO DMA Enable
bits : 2 - 2 (1 bit)
access : read-write
CB1DE : Capture B1 FIFO DMA Enable
bits : 3 - 3 (1 bit)
access : read-write
CA0DE : Capture A0 FIFO DMA Enable
bits : 4 - 4 (1 bit)
access : read-write
CA1DE : Capture A1 FIFO DMA Enable
bits : 5 - 5 (1 bit)
access : read-write
CAPTDE : Capture DMA Enable Source Select
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
Read DMA requests disabled.
#01 : 01
Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive.
#10 : 10
A local sync (VAL1 matches counter) sets the read DMA request.
#11 : 11
A local reload (STS[RF] being set) sets the read DMA request.
End of enumeration elements list.
FAND : FIFO Watermark AND Control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Selected FIFO watermarks are OR'ed together.
#1 : 1
Selected FIFO watermarks are AND'ed together.
End of enumeration elements list.
VALDE : Value Registers DMA Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA write requests disabled
#1 : 1
DMA write requests for the VALx and FRACVALx registers enabled
End of enumeration elements list.
Output Trigger Control Register
address_offset : 0xDE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT_TRIG_EN : Output Trigger Enables
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
PWM_OUT_TRIGx will not set when the counter value matches the VALx value.
#1 : 1
PWM_OUT_TRIGx will set when the counter value matches the VALx value.
End of enumeration elements list.
TRGFRQ : Trigger frequency
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.
#1 : 1
Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.
End of enumeration elements list.
PWBOT1 : Output Trigger 1 Source Select
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port.
#1 : 1
Route the PWM1 output to the PWM_OUT_TRIG1 port.
End of enumeration elements list.
PWAOT0 : Output Trigger 0 Source Select
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port.
#1 : 1
Route the PWM0 output to the PWM_OUT_TRIG0 port.
End of enumeration elements list.
Fault Disable Mapping Register 0
address_offset : 0xE4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIS0A : PWM_A Fault Disable Mask 0
bits : 0 - 3 (4 bit)
access : read-write
DIS0B : PWM_B Fault Disable Mask 0
bits : 4 - 7 (4 bit)
access : read-write
DIS0X : PWM_X Fault Disable Mask 0
bits : 8 - 11 (4 bit)
access : read-write
Deadtime Count Register 0
address_offset : 0xF0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTCNT0 : The DTCNT0 field is interpreted differently depending on whether or not the fractional delays are being used (FRCNTRL[FRAC23_EN] is set)
bits : 0 - 15 (16 bit)
access : read-write
Deadtime Count Register 1
address_offset : 0xF6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTCNT1 : The DTCNT1 field is interpreted differently depending on whether or not the fractional delays are being used (FRCNTRL[FRAC45_EN] is set)
bits : 0 - 15 (16 bit)
access : read-write
Capture Control A Register
address_offset : 0xFC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARMA : Arm A
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Input capture operation is disabled.
#1 : 1
Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled.
End of enumeration elements list.
ONESHOTA : One Shot Mode A
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely. If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit.
#1 : 1
One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again. If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared.
End of enumeration elements list.
EDGA0 : Edge A 0
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
Disabled
#01 : 01
Capture falling edges
#10 : 10
Capture rising edges
#11 : 11
Capture any edge
End of enumeration elements list.
EDGA1 : Edge A 1
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
Disabled
#01 : 01
Capture falling edges
#10 : 10
Capture rising edges
#11 : 11
Capture any edge
End of enumeration elements list.
INP_SELA : Input Select A
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Raw PWM_A input signal selected as source.
#1 : 1
Output of edge counter/compare selected as source. When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers.
End of enumeration elements list.
EDGCNTA_EN : Edge Counter A Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge counter disabled and held in reset
#1 : 1
Edge counter enabled
End of enumeration elements list.
CFAWM : Capture A FIFOs Water Mark
bits : 8 - 9 (2 bit)
access : read-write
CA0CNT : Capture A0 FIFO Word Count
bits : 10 - 12 (3 bit)
access : read-only
CA1CNT : Capture A1 FIFO Word Count
bits : 13 - 15 (3 bit)
access : read-only
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