\n
address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
Flash Access Protection Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0AP : Master 0 Access Protection
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No access may be performed by this master
#01 : 01
Only read accesses may be performed by this master
#10 : 10
Only write accesses may be performed by this master
#11 : 11
Both read and write accesses may be performed by this master
End of enumeration elements list.
M1AP : Master 1 Access Protection
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
No access may be performed by this master
#01 : 01
Only read accesses may be performed by this master
#10 : 10
Only write accesses may be performed by this master
#11 : 11
Both read and write accesses may be performed by this master
End of enumeration elements list.
M2AP : Master 2 Access Protection
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
No access may be performed by this master
#01 : 01
Only read accesses may be performed by this master
#10 : 10
Only write accesses may be performed by this master
#11 : 11
Both read and write accesses may be performed by this master
End of enumeration elements list.
M3AP : Master 3 Access Protection
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
No access may be performed by this master
#01 : 01
Only read accesses may be performed by this master
#10 : 10
Only write accesses may be performed by this master
#11 : 11
Both read and write accesses may be performed by this master
End of enumeration elements list.
M0PFD : Master 0 Prefetch Disable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Prefetching for this master is enabled.
#1 : 1
Prefetching for this master is disabled.
End of enumeration elements list.
M1PFD : Master 1 Prefetch Disable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Prefetching for this master is enabled.
#1 : 1
Prefetching for this master is disabled.
End of enumeration elements list.
M2PFD : Master 2 Prefetch Disable
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Prefetching for this master is enabled.
#1 : 1
Prefetching for this master is disabled.
End of enumeration elements list.
M3PFD : Master 3 Prefetch Disable
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Prefetching for this master is enabled.
#1 : 1
Prefetching for this master is disabled.
End of enumeration elements list.
Flash Bank 0 Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
B0IPE : Bank 0 Instruction Prefetch Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not prefetch in response to instruction fetches.
#1 : 1
Enable prefetches in response to instruction fetches.
End of enumeration elements list.
B0DPE : Bank 0 Data Prefetch Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not prefetch in response to data references.
#1 : 1
Enable prefetches in response to data references.
End of enumeration elements list.
B0MW : Bank 0 Memory Width
bits : 17 - 18 (2 bit)
access : read-only
Enumeration:
#00 : 00
32 bits
#01 : 01
64 bits
#10 : 10
128 bits
#11 : 11
256 bits
End of enumeration elements list.
S_INV : Invalidate Prefetch Speculation Buffer
bits : 19 - 19 (1 bit)
access : write-only
Enumeration:
#0 : 0
Speculation buffer is not affected.
#1 : 1
Invalidate (clear) the speculation buffer.
End of enumeration elements list.
B0RWSC : Bank 0 Read Wait State Control
bits : 28 - 31 (4 bit)
access : read-only
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