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PDB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x19C byte (0x0)
mem_usage : registers
protection : not protected

Registers

SC

DACINTC

DACINT

POEN

CH0C1

CH0S

CH0DLY0

PO0DLY

CH0DLY1

MOD

PO1DLY

CH1C1

CH1S

CH1DLY0

CH1DLY1

CNT

IDLY


SC

Status and Control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SC SC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LDOK CONT MULT PDBIE PDBIF PDBEN TRGSEL PRESCALER DMAEN SWTRIG PDBEIE LDMOD

LDOK : Load OK
bits : 0 - 0 (1 bit)
access : read-write

CONT : Continuous Mode Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

PDB operation in One-Shot mode

#1 : 1

PDB operation in Continuous mode

End of enumeration elements list.

MULT : Multiplication Factor Select for Prescaler
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 00

Multiplication factor is 1.

#01 : 01

Multiplication factor is 10.

#10 : 10

Multiplication factor is 20.

#11 : 11

Multiplication factor is 40.

End of enumeration elements list.

PDBIE : PDB Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

PDB interrupt disabled.

#1 : 1

PDB interrupt enabled.

End of enumeration elements list.

PDBIF : PDB Interrupt Flag
bits : 6 - 6 (1 bit)
access : read-write

PDBEN : PDB Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

PDB disabled. Counter is off.

#1 : 1

PDB enabled.

End of enumeration elements list.

TRGSEL : Trigger Input Source Select
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Trigger-In 0 is selected.

#0001 : 0001

Trigger-In 1 is selected.

#0010 : 0010

Trigger-In 2 is selected.

#0011 : 0011

Trigger-In 3 is selected.

#0100 : 0100

Trigger-In 4 is selected.

#0101 : 0101

Trigger-In 5 is selected.

#0110 : 0110

Trigger-In 6 is selected.

#0111 : 0111

Trigger-In 7 is selected.

#1000 : 1000

Trigger-In 8 is selected.

#1001 : 1001

Trigger-In 9 is selected.

#1010 : 1010

Trigger-In 10 is selected.

#1011 : 1011

Trigger-In 11 is selected.

#1100 : 1100

Trigger-In 12 is selected.

#1101 : 1101

Trigger-In 13 is selected.

#1110 : 1110

Trigger-In 14 is selected.

#1111 : 1111

Software trigger is selected.

End of enumeration elements list.

PRESCALER : Prescaler Divider Select
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#000 : 000

Counting uses the peripheral clock divided by multiplication factor selected by MULT.

#001 : 001

Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT.

#010 : 010

Counting uses the peripheral clock divided by four times of the multiplication factor selected by MULT.

#011 : 011

Counting uses the peripheral clock divided by eight times of the multiplication factor selected by MULT.

#100 : 100

Counting uses the peripheral clock divided by 16 times of the multiplication factor selected by MULT.

#101 : 101

Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT.

#110 : 110

Counting uses the peripheral clock divided by 64 times of the multiplication factor selected by MULT.

#111 : 111

Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT.

End of enumeration elements list.

DMAEN : DMA Enable
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA disabled.

#1 : 1

DMA enabled.

End of enumeration elements list.

SWTRIG : Software Trigger
bits : 16 - 16 (1 bit)
access : write-only

PDBEIE : PDB Sequence Error Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

PDB sequence error interrupt disabled.

#1 : 1

PDB sequence error interrupt enabled.

End of enumeration elements list.

LDMOD : Load Mode Select
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

#00 : 00

The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK.

#01 : 01

The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to LDOK.

#10 : 10

The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK.

#11 : 11

The internal registers are loaded with the values from their buffers when either the PDB counter reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK.

End of enumeration elements list.


DACINTC

DAC Interval Trigger n Control register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DACINTC DACINTC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOE EXT

TOE : DAC Interval Trigger Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC interval trigger disabled.

#1 : 1

DAC interval trigger enabled.

End of enumeration elements list.

EXT : DAC External Trigger Input Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC external trigger input disabled. DAC interval counter is reset and started counting when a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.

#1 : 1

DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger.

End of enumeration elements list.


DACINT

DAC Interval n register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DACINT DACINT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT

INT : DAC Interval
bits : 0 - 15 (16 bit)
access : read-write


POEN

Pulse-Out n Enable register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POEN POEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POEN

POEN : PDB Pulse-Out Enable
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

#0 : 0

PDB Pulse-Out disabled

#1 : 1

PDB Pulse-Out enabled

End of enumeration elements list.


CH0C1

Channel n Control register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0C1 CH0C1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TOS BB

EN : PDB Channel Pre-Trigger Enable
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

#0 : 0

PDB channel's corresponding pre-trigger disabled.

#1 : 1

PDB channel's corresponding pre-trigger enabled.

End of enumeration elements list.

TOS : PDB Channel Pre-Trigger Output Select
bits : 8 - 15 (8 bit)
access : read-write

Enumeration:

#0 : 0

PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.

#1 : 1

PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1.

End of enumeration elements list.

BB : PDB Channel Pre-Trigger Back-to-Back Operation Enable
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

#0 : 0

PDB channel's corresponding pre-trigger back-to-back operation disabled.

#1 : 1

PDB channel's corresponding pre-trigger back-to-back operation enabled.

End of enumeration elements list.


CH0S

Channel n Status register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0S CH0S read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERR CF

ERR : PDB Channel Sequence Error Flags
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

#0 : 0

Sequence error not detected on PDB channel's corresponding pre-trigger.

#1 : 1

Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags.

End of enumeration elements list.

CF : PDB Channel Flags
bits : 16 - 23 (8 bit)
access : read-write


CH0DLY0

Channel n Delay 0 register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0DLY0 CH0DLY0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY

DLY : PDB Channel Delay
bits : 0 - 15 (16 bit)
access : read-write


PO0DLY

Pulse-Out n Delay register
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PO0DLY PO0DLY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY2 DLY1

DLY2 : PDB Pulse-Out Delay 2
bits : 0 - 15 (16 bit)
access : read-write

DLY1 : PDB Pulse-Out Delay 1
bits : 16 - 31 (16 bit)
access : read-write


CH0DLY1

Channel n Delay 1 register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0DLY1 CH0DLY1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY

DLY : PDB Channel Delay
bits : 0 - 15 (16 bit)
access : read-write


MOD

Modulus register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOD MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOD

MOD : PDB Modulus
bits : 0 - 15 (16 bit)
access : read-write


PO1DLY

Pulse-Out n Delay register
address_offset : 0x4C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PO1DLY PO1DLY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY2 DLY1

DLY2 : PDB Pulse-Out Delay 2
bits : 0 - 15 (16 bit)
access : read-write

DLY1 : PDB Pulse-Out Delay 1
bits : 16 - 31 (16 bit)
access : read-write


CH1C1

Channel n Control register 1
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1C1 CH1C1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TOS BB

EN : PDB Channel Pre-Trigger Enable
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

#0 : 0

PDB channel's corresponding pre-trigger disabled.

#1 : 1

PDB channel's corresponding pre-trigger enabled.

End of enumeration elements list.

TOS : PDB Channel Pre-Trigger Output Select
bits : 8 - 15 (8 bit)
access : read-write

Enumeration:

#0 : 0

PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.

#1 : 1

PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1.

End of enumeration elements list.

BB : PDB Channel Pre-Trigger Back-to-Back Operation Enable
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

#0 : 0

PDB channel's corresponding pre-trigger back-to-back operation disabled.

#1 : 1

PDB channel's corresponding pre-trigger back-to-back operation enabled.

End of enumeration elements list.


CH1S

Channel n Status register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1S CH1S read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERR CF

ERR : PDB Channel Sequence Error Flags
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

#0 : 0

Sequence error not detected on PDB channel's corresponding pre-trigger.

#1 : 1

Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags.

End of enumeration elements list.

CF : PDB Channel Flags
bits : 16 - 23 (8 bit)
access : read-write


CH1DLY0

Channel n Delay 0 register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1DLY0 CH1DLY0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY

DLY : PDB Channel Delay
bits : 0 - 15 (16 bit)
access : read-write


CH1DLY1

Channel n Delay 1 register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1DLY1 CH1DLY1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLY

DLY : PDB Channel Delay
bits : 0 - 15 (16 bit)
access : read-write


CNT

Counter register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CNT CNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : PDB Counter
bits : 0 - 15 (16 bit)
access : read-only


IDLY

Interrupt Delay register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IDLY IDLY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDLY

IDLY : PDB Interrupt Delay
bits : 0 - 15 (16 bit)
access : read-write



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