\n
address_offset : 0x0 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection : not protected
Crossbar A Select Register 0
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Input (XBARA_INn) to be muxed to XBARA_OUT0 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
SEL1 : Input (XBARA_INn) to be muxed to XBARA_OUT1 (refer to Functional Description section for input/output assignment)
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
Crossbar A Select Register 8
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL16 : Input (XBARA_INn) to be muxed to XBARA_OUT16 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
SEL17 : Input (XBARA_INn) to be muxed to XBARA_OUT17 (refer to Functional Description section for input/output assignment)
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
Crossbar A Select Register 9
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL18 : Input (XBARA_INn) to be muxed to XBARA_OUT18 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
SEL19 : Input (XBARA_INn) to be muxed to XBARA_OUT19 (refer to Functional Description section for input/output assignment)
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
Crossbar A Select Register 10
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL20 : Input (XBARA_INn) to be muxed to XBARA_OUT20 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
SEL21 : Input (XBARA_INn) to be muxed to XBARA_OUT21 (refer to Functional Description section for input/output assignment)
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
Crossbar A Select Register 11
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL22 : Input (XBARA_INn) to be muxed to XBARA_OUT22 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
SEL23 : Input (XBARA_INn) to be muxed to XBARA_OUT23 (refer to Functional Description section for input/output assignment)
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
Crossbar A Select Register 12
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL24 : Input (XBARA_INn) to be muxed to XBARA_OUT24 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
SEL25 : Input (XBARA_INn) to be muxed to XBARA_OUT25 (refer to Functional Description section for input/output assignment)
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
Crossbar A Select Register 13
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL26 : Input (XBARA_INn) to be muxed to XBARA_OUT26 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
SEL27 : Input (XBARA_INn) to be muxed to XBARA_OUT27 (refer to Functional Description section for input/output assignment)
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
Crossbar A Select Register 14
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL28 : Input (XBARA_INn) to be muxed to XBARA_OUT28 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
SEL29 : Input (XBARA_INn) to be muxed to XBARA_OUT29 (refer to Functional Description section for input/output assignment)
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
Crossbar A Select Register 15
address_offset : 0x1E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL30 : Input (XBARA_INn) to be muxed to XBARA_OUT30 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
SEL31 : Input (XBARA_INn) to be muxed to XBARA_OUT31 (refer to Functional Description section for input/output assignment)
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
Crossbar A Select Register 1
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL2 : Input (XBARA_INn) to be muxed to XBARA_OUT2 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
SEL3 : Input (XBARA_INn) to be muxed to XBARA_OUT3 (refer to Functional Description section for input/output assignment)
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
Crossbar A Select Register 16
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL32 : Input (XBARA_INn) to be muxed to XBARA_OUT32 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
SEL33 : Input (XBARA_INn) to be muxed to XBARA_OUT33 (refer to Functional Description section for input/output assignment)
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
Crossbar A Select Register 17
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL34 : Input (XBARA_INn) to be muxed to XBARA_OUT34 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
SEL35 : Input (XBARA_INn) to be muxed to XBARA_OUT35 (refer to Functional Description section for input/output assignment)
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
Crossbar A Select Register 18
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL36 : Input (XBARA_INn) to be muxed to XBARA_OUT36 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
SEL37 : Input (XBARA_INn) to be muxed to XBARA_OUT37 (refer to Functional Description section for input/output assignment)
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
Crossbar A Select Register 19
address_offset : 0x26 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL38 : Input (XBARA_INn) to be muxed to XBARA_OUT38 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
SEL39 : Input (XBARA_INn) to be muxed to XBARA_OUT39 (refer to Functional Description section for input/output assignment)
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
Crossbar A Select Register 20
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL40 : Input (XBARA_INn) to be muxed to XBARA_OUT40 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
SEL41 : Input (XBARA_INn) to be muxed to XBARA_OUT41 (refer to Functional Description section for input/output assignment)
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
Crossbar A Select Register 21
address_offset : 0x2A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL42 : Input (XBARA_INn) to be muxed to XBARA_OUT42 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
SEL43 : Input (XBARA_INn) to be muxed to XBARA_OUT43 (refer to Functional Description section for input/output assignment)
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
Crossbar A Select Register 22
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL44 : Input (XBARA_INn) to be muxed to XBARA_OUT44 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
SEL45 : Input (XBARA_INn) to be muxed to XBARA_OUT45 (refer to Functional Description section for input/output assignment)
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
Crossbar A Select Register 23
address_offset : 0x2E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL46 : Input (XBARA_INn) to be muxed to XBARA_OUT46 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
SEL47 : Input (XBARA_INn) to be muxed to XBARA_OUT47 (refer to Functional Description section for input/output assignment)
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
Crossbar A Select Register 24
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL48 : Input (XBARA_INn) to be muxed to XBARA_OUT48 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
SEL49 : Input (XBARA_INn) to be muxed to XBARA_OUT49 (refer to Functional Description section for input/output assignment)
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
Crossbar A Select Register 25
address_offset : 0x32 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL50 : Input (XBARA_INn) to be muxed to XBARA_OUT50 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
SEL51 : Input (XBARA_INn) to be muxed to XBARA_OUT51 (refer to Functional Description section for input/output assignment)
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
Crossbar A Select Register 26
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL52 : Input (XBARA_INn) to be muxed to XBARA_OUT52 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
SEL53 : Input (XBARA_INn) to be muxed to XBARA_OUT53 (refer to Functional Description section for input/output assignment)
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
Crossbar A Select Register 27
address_offset : 0x36 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL54 : Input (XBARA_INn) to be muxed to XBARA_OUT54 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
SEL55 : Input (XBARA_INn) to be muxed to XBARA_OUT55 (refer to Functional Description section for input/output assignment)
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
Crossbar A Select Register 28
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL56 : Input (XBARA_INn) to be muxed to XBARA_OUT56 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
SEL57 : Input (XBARA_INn) to be muxed to XBARA_OUT57 (refer to Functional Description section for input/output assignment)
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
Crossbar A Select Register 29
address_offset : 0x3A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL58 : Input (XBARA_INn) to be muxed to XBARA_OUT58 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
Crossbar A Control Register 0
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEN0 : DMA Enable for XBAR_OUT0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA disabled
#1 : 1
DMA enabled
End of enumeration elements list.
IEN0 : Interrupt Enable for XBAR_OUT0
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt disabled
#1 : 1
Interrupt enabled
End of enumeration elements list.
EDGE0 : Active edge for edge detection on XBAR_OUT0
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
STS0 never asserts
#01 : 01
STS0 asserts on rising edges of XBAR_OUT0
#10 : 10
STS0 asserts on falling edges of XBAR_OUT0
#11 : 11
STS0 asserts on rising and falling edges of XBAR_OUT0
End of enumeration elements list.
STS0 : Edge detection status for XBAR_OUT0
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Active edge not yet detected on XBAR_OUT0
#1 : 1
Active edge detected on XBAR_OUT0
End of enumeration elements list.
DEN1 : DMA Enable for XBAR_OUT1
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA disabled
#1 : 1
DMA enabled
End of enumeration elements list.
IEN1 : Interrupt Enable for XBAR_OUT1
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt disabled
#1 : 1
Interrupt enabled
End of enumeration elements list.
EDGE1 : Active edge for edge detection on XBAR_OUT1
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 00
STS1 never asserts
#01 : 01
STS1 asserts on rising edges of XBAR_OUT1
#10 : 10
STS1 asserts on falling edges of XBAR_OUT1
#11 : 11
STS1 asserts on rising and falling edges of XBAR_OUT1
End of enumeration elements list.
STS1 : Edge detection status for XBAR_OUT1
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Active edge not yet detected on XBAR_OUT1
#1 : 1
Active edge detected on XBAR_OUT1
End of enumeration elements list.
Crossbar A Control Register 1
address_offset : 0x3E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEN2 : DMA Enable for XBAR_OUT2
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA disabled
#1 : 1
DMA enabled
End of enumeration elements list.
IEN2 : Interrupt Enable for XBAR_OUT2
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt disabled
#1 : 1
Interrupt enabled
End of enumeration elements list.
EDGE2 : Active edge for edge detection on XBAR_OUT2
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
STS2 never asserts
#01 : 01
STS2 asserts on rising edges of XBAR_OUT2
#10 : 10
STS2 asserts on falling edges of XBAR_OUT2
#11 : 11
STS2 asserts on rising and falling edges of XBAR_OUT2
End of enumeration elements list.
STS2 : Edge detection status for XBAR_OUT2
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Active edge not yet detected on XBAR_OUT2
#1 : 1
Active edge detected on XBAR_OUT2
End of enumeration elements list.
DEN3 : DMA Enable for XBAR_OUT3
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA disabled
#1 : 1
DMA enabled
End of enumeration elements list.
IEN3 : Interrupt Enable for XBAR_OUT3
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt disabled
#1 : 1
Interrupt enabled
End of enumeration elements list.
EDGE3 : Active edge for edge detection on XBAR_OUT3
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 00
STS3 never asserts
#01 : 01
STS3 asserts on rising edges of XBAR_OUT3
#10 : 10
STS3 asserts on falling edges of XBAR_OUT3
#11 : 11
STS3 asserts on rising and falling edges of XBAR_OUT3
End of enumeration elements list.
STS3 : Edge detection status for XBAR_OUT3
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Active edge not yet detected on XBAR_OUT3
#1 : 1
Active edge detected on XBAR_OUT3
End of enumeration elements list.
Crossbar A Select Register 2
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL4 : Input (XBARA_INn) to be muxed to XBARA_OUT4 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
SEL5 : Input (XBARA_INn) to be muxed to XBARA_OUT5 (refer to Functional Description section for input/output assignment)
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
Crossbar A Select Register 3
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL6 : Input (XBARA_INn) to be muxed to XBARA_OUT6 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
SEL7 : Input (XBARA_INn) to be muxed to XBARA_OUT7 (refer to Functional Description section for input/output assignment)
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
Crossbar A Select Register 4
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL8 : Input (XBARA_INn) to be muxed to XBARA_OUT8 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
SEL9 : Input (XBARA_INn) to be muxed to XBARA_OUT9 (refer to Functional Description section for input/output assignment)
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
Crossbar A Select Register 5
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL10 : Input (XBARA_INn) to be muxed to XBARA_OUT10 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
SEL11 : Input (XBARA_INn) to be muxed to XBARA_OUT11 (refer to Functional Description section for input/output assignment)
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
Crossbar A Select Register 6
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL12 : Input (XBARA_INn) to be muxed to XBARA_OUT12 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
SEL13 : Input (XBARA_INn) to be muxed to XBARA_OUT13 (refer to Functional Description section for input/output assignment)
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
Crossbar A Select Register 7
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL14 : Input (XBARA_INn) to be muxed to XBARA_OUT14 (refer to Functional Description section for input/output assignment)
bits : 0 - 5 (6 bit)
access : read-write
SEL15 : Input (XBARA_INn) to be muxed to XBARA_OUT15 (refer to Functional Description section for input/output assignment)
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 0
Logic zero
#1 : 1
Logic one
#10 : 2
XBAR0_IN2 input pin
#11 : 3
XBAR0_IN3 input pin
#100 : 4
XBAR0_IN4 input pin
#101 : 5
XBAR0_IN5 input pin
#110 : 6
XBAR0_IN6 input pin
#111 : 7
XBAR0_IN7 input pin
#1000 : 8
XBAR0_IN8 input pin
#1001 : 9
XBAR0_IN9 input pin
#1010 : 10
XBAR0_IN10 input pin
#1011 : 11
XBAR0_IN11 input pin
#1100 : 12
CMP0 Output
#1101 : 13
CMP1 Output
#1110 : 14
CMP2 Output
#1111 : 15
CMP3 Output
#10000 : 16
FTM0 all channels output compare ORed together
#10001 : 17
FTM0 all channels counter init ORed together
#10010 : 18
FTM3 all channels output compare ORed together
#10011 : 19
FTM3 all channels counter init ORed together
#10100 : 20
PWMA channel 0 trigger 0
#10101 : 21
PWMA channel 0 trigger 1
#10110 : 22
PWMA channel 1 trigger 0
#10111 : 23
PWMA channel 1 trigger 1
#11000 : 24
PWMA channel 2 trigger 0
#11001 : 25
PWMA channel 2 trigger 1
#11010 : 26
PWMA channel 3 trigger 0
#11011 : 27
PWMA channel 3 trigger 1
#11100 : 28
PDB0 channel 1 output trigger
#11101 : 29
PDB0 channel 0 output trigger
#11110 : 30
PDB1 channel 1 output trigger
#11111 : 31
PDB1 channel 0 output trigger
#100000 : 32
High Speed Analog-to-Digital Converter 1 conversion A complete
#100001 : 33
High Speed Analog-to-Digital Converter 0 conversion A complete
#100010 : 34
High Speed Analog-to-Digital Converter 1 conversion B complete
#100011 : 35
High Speed Analog-to-Digital Converter 0 conversion B complete
#100100 : 36
FTM1 all channels output compare ORed together
#100101 : 37
FTM1 all channels counter init ORed together
#100110 : 38
DMA channel 0 done
#100111 : 39
DMA channel 1 done
#101000 : 40
DMA channel 6 done
#101001 : 41
DMA channel 7 done
#101010 : 42
PIT trigger 0
#101011 : 43
PIT trigger 1
#101100 : 44
Analog-to-Digital Converter 0 conversion complete
#101101 : 45
ENC compare trigger and position match
#101110 : 46
AOI output 0
#101111 : 47
AOI output 1
#110000 : 48
AOI output 2
#110001 : 49
AOI output 3
#110010 : 50
PIT trigger 2
#110011 : 51
PIT trigger 3
#110100 : 52
PWMB channel 0 trigger 0 or trigger 1
#110101 : 53
PWMB channel 1 trigger 0 or trigger 1
#110110 : 54
PWMB channel 2 trigger 0 or trigger 1
#110111 : 55
PWMB channel 3 trigger 0 or trigger 1
#111000 : 56
FTM2 all channels output compare ORed together
#111001 : 57
FTM2 all channels counter init ORed together
End of enumeration elements list.
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