Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1108 byte (0x0)
mem_usage : registers
protection : not protected
System Options Register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSC32KOUT : 32K oscillator clock output
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
ERCLK32K is not output.
#01 : 01
ERCLK32K is output on PTB3.
End of enumeration elements list.
OSC32KSEL : 32K Oscillator Clock Select
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
32kHz oscillator (OSC32KCLK)
#10 : 10
RTC_CLKIN
#11 : 11
LPO 1kHz
End of enumeration elements list.
SIM_MISCTL : This bit control the function of RF_ACTIVE on PTC1/PTC19 ALT7
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Radio active status is output from RF_ACTIVE
#1 : 1
MCU low power status is output from RF_ACTIVE. Output logic is high when MCU is in STOP, VLPS, LLSx or VLLSx modes and low when not.
End of enumeration elements list.
System Options Register 2
address_offset : 0x1004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKOUTSEL : CLKOUT select
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
#000 : 000
OSCERCLK DIV2
#001 : 001
OSCERCLK DIV4
#010 : 010
Bus clock
#011 : 011
LPO clock 1 kHz
#100 : 100
MCGIRCLK
#101 : 101
OSCERCLK DIV8
#110 : 110
OSCERCLK
End of enumeration elements list.
TPMSRC : TPM Clock Source Select
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
Clock disabled
#01 : 01
MCGFLLCLK clock
#10 : 10
OSCERCLK clock
#11 : 11
MCGIRCLK clock
End of enumeration elements list.
LPUART0SRC : LPUART0 Clock Source Select
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 00
Clock disabled
#01 : 01
MCGFLLCLK clock
#10 : 10
OSCERCLK clock
#11 : 11
MCGIRCLK clock
End of enumeration elements list.
System Options Register 4
address_offset : 0x100C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPM1CH0SRC : TPM1 Channel 0 Input Capture Source Select
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
TPM1_CH0 signal
#1 : 1
CMP0 output
End of enumeration elements list.
TPM2CH0SRC : TPM2 Channel 0 Input Capture Source Select
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
TPM2_CH0 signal
#1 : 1
CMP0 output
End of enumeration elements list.
TPM0CLKSEL : TPM0 External Clock Pin Select
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
TPM0 external clock driven by TPM_CLKIN0 pin.
#1 : 1
TPM0 external clock driven by TPM_CLKIN1 pin.
End of enumeration elements list.
TPM1CLKSEL : TPM1 External Clock Pin Select
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
TPM1 external clock driven by TPM_CLKIN0 pin.
#1 : 1
TPM1 external clock driven by TPM_CLKIN1 pin.
End of enumeration elements list.
TPM2CLKSEL : TPM2 External Clock Pin Select
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
TPM2 external clock driven by TPM_CLKIN0 pin.
#1 : 1
TPM2 external clock driven by TPM_CLKIN1 pin.
End of enumeration elements list.
System Options Register 5
address_offset : 0x1010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPUART0TXSRC : LPUART0 Transmit Data Source Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
LPUART0_TX pin
#01 : 01
LPUART0_TX pin modulated with TPM1 channel 0 output
#10 : 10
LPUART0_TX pin modulated with TPM2 channel 0 output
End of enumeration elements list.
LPUART0RXSRC : LPUART0 Receive Data Source Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
LPUART_RX pin
#1 : 1
CMP0 output
End of enumeration elements list.
LPUART0ODE : LPUART0 Open Drain Enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain is disabled on LPUART0.
#1 : 1
Open drain is enabled on LPUART0.
End of enumeration elements list.
System Options Register 7
address_offset : 0x1018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC0TRGSEL : ADC0 Trigger Select
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
External trigger pin input (EXTRG_IN)
#0001 : 0001
CMP0 output
#0100 : 0100
PIT trigger 0
#0101 : 0101
PIT trigger 1
#1000 : 1000
TPM0 overflow
#1001 : 1001
TPM1 overflow
#1010 : 1010
TPM2 overflow
#1100 : 1100
RTC alarm
#1101 : 1101
RTC seconds
#1110 : 1110
LPTMR0 trigger
#1111 : 1111
Radio TSM
End of enumeration elements list.
ADC0PRETRGSEL : ADC0 Pretrigger Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pre-trigger ADHDWTSA is selected, thus ADC0 will use ADC0_SC1A configuration for the next ADC conversion and store the result in ADC0_RA register.
#1 : 1
Pre-trigger ADHDWTSB is selected, thus ADC0 will use ADC0_SC1B configuration for the next ADC conversion and store the result in ADC0_RB register.
End of enumeration elements list.
ADC0ALTTRGEN : ADC0 Alternate Trigger Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADC ADHWT trigger comes from TPM1 channel 0 and channel1. Prior to the assertion of TPM1 channel 0, a pre-trigger pulse will be sent to ADHWTSA to initiate an ADC acquisition using ADCx_SC1A configuration and store ADC conversion in ADCx_RA Register. Prior to the assertion of TPM1 channel 1 a pre-trigger pulse will be sent to ADHWTSB to initiate an ADC acquisition using ADCx_SC1Bconfiguration and store ADC conversion in ADCx_RB Register.
#1 : 1
ADC ADHWT trigger comes from a peripheral event selected by ADC0TRGSEL bits.ADC0PRETRGSEL bit will select the optional ADHWTSA or ADHWTSB select lines for choosing the ADCx_SC1x config and ADCx_Rx result regsiter to store the ADC conversion.
End of enumeration elements list.
System Device Identification Register
address_offset : 0x1024 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PINID : Pin count Identification
bits : 0 - 3 (4 bit)
access : read-only
Enumeration:
#0010 : 0010
32-pin
#0100 : 0100
48-pin
#1011 : 1011
CSP
End of enumeration elements list.
DIEID : Device Die Number
bits : 7 - 11 (5 bit)
access : read-only
REVID : Device Revision Number
bits : 12 - 15 (4 bit)
access : read-only
SRAMSIZE : System SRAM Size
bits : 16 - 19 (4 bit)
access : read-only
SERIESID : Kinetis Series ID
bits : 20 - 23 (4 bit)
access : read-only
Enumeration:
#0101 : 0101
KW family
End of enumeration elements list.
SUBFAMID : Kinetis Sub-Family ID.
bits : 24 - 25 (2 bit)
access : read-only
Enumeration:
#00 : 00
KWx0 Subfamily
#01 : 01
KWx1 Subfamily
#10 : 10
KWx2 Subfamily
#11 : 11
KWx3 Subfamily
End of enumeration elements list.
FAMID : Kinetis family ID
bits : 28 - 31 (4 bit)
access : read-only
Enumeration:
#0010 : 0010
KW20 Family (802.15.4/ZigBee)
#0011 : 0011
KW30 Family (BTLE)
#0100 : 0100
KW40 Family (802.15.4/ZigBee or BTLE)
End of enumeration elements list.
System Clock Gating Control Register 4
address_offset : 0x1034 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMT : CMT Clock Gate Control
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
I2C0 : I2C0 Clock Gate Control
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
I2C1 : I2C1 Clock Gate Control
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
CMP : Comparator Clock Gate Control
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
System Clock Gating Control Register 5
address_offset : 0x1038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTMR : Low Power Timer Access Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Access disabled
#1 : 1
Access enabled
End of enumeration elements list.
TSI : TSI Access Control
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Access disabled
#1 : 1
Access enabled
End of enumeration elements list.
PORTA : Port A Clock Gate Control
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTB : Port B Clock Gate Control
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTC : Port C Clock Gate Control
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
LPUART0 : LPUART0 Clock Gate Control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
LTC : LTC Clock Gate Control
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
AESA : AESA Clock Gate Control
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
RSIM : RSIM Clock Gate Control
bits : 25 - 25 (1 bit)
access : read-only
DCDC : DCDC Clock Gate Control
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
BTLL : BTLL System Clock Gate Control
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PHYDIG : PHY Digital Clock Gate Control
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
ZigBee : ZigBee Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
System Clock Gating Control Register 6
address_offset : 0x103C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTF : Flash Memory Clock Gate Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
DMAMUX : DMA Mux Clock Gate Control
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
TRNG : TRNG Clock Gate Control
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
SPI0 : SPI0 Clock Gate Control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
SPI1 : SPI1 Clock Gate Control
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PIT : PIT Clock Gate Control
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
TPM0 : TPM0 Clock Gate Control
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
TPM1 : TPM1 Clock Gate Control
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
TPM2 : TPM2 Clock Gate Control
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
ADC0 : ADC0 Clock Gate Control
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
RTC : RTC Access Control
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Access and interrupts disabled
#1 : 1
Access and interrupts enabled
End of enumeration elements list.
DAC0 : DAC0 Clock Gate Control
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
System Clock Gating Control Register 7
address_offset : 0x1040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA : DMA Clock Gate Control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
System Clock Divider Register 1
address_offset : 0x1044 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUTDIV4 : Clock 4 Output Divider value
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 000
Divide-by-1.
#001 : 001
Divide-by-2.
#010 : 010
Divide-by-3.
#011 : 011
Divide-by-4.
#100 : 100
Divide-by-5.
#101 : 101
Divide-by-6.
#110 : 110
Divide-by-7.
#111 : 111
Divide-by-8.
End of enumeration elements list.
OUTDIV1 : Clock 1 Output Divider value
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide-by-1.
#0001 : 0001
Divide-by-2.
#0010 : 0010
Divide-by-3.
#0011 : 0011
Divide-by-4.
#0100 : 0100
Divide-by-5.
#0101 : 0101
Divide-by-6.
#0110 : 0110
Divide-by-7.
#0111 : 0111
Divide-by-8.
#1000 : 1000
Divide-by-9.
#1001 : 1001
Divide-by-10.
#1010 : 1010
Divide-by-11.
#1011 : 1011
Divide-by-12.
#1100 : 1100
Divide-by-13.
#1101 : 1101
Divide-by-14.
#1110 : 1110
Divide-by-15.
#1111 : 1111
Divide-by-16.
End of enumeration elements list.
Flash Configuration Register 1
address_offset : 0x104C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLASHDIS : Flash Disable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash is enabled.
#1 : 1
Flash is disabled.
End of enumeration elements list.
FLASHDOZE : Flash Doze
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash remains enabled during Doze mode.
#1 : 1
Flash is disabled for the duration of Doze mode.
End of enumeration elements list.
PFSIZE : Program Flash Size
bits : 24 - 27 (4 bit)
access : read-only
Flash Configuration Register 2
address_offset : 0x1050 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MAXADDR1 : no description available
bits : 16 - 22 (7 bit)
access : read-only
MAXADDR0 : Max Address lock
bits : 24 - 30 (7 bit)
access : read-only
Unique Identification Register Mid-High
address_offset : 0x1058 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UID : Unique Identification
bits : 0 - 15 (16 bit)
access : read-only
Unique Identification Register Mid Low
address_offset : 0x105C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UID : Unique Identification
bits : 0 - 31 (32 bit)
access : read-only
Unique Identification Register Low
address_offset : 0x1060 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UID : Unique Identification
bits : 0 - 31 (32 bit)
access : read-only
COP Control Register
address_offset : 0x1100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COPW : COP Windowed Mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal mode
#1 : 1
Windowed mode
End of enumeration elements list.
COPCLKS : COP Clock Select
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
COP configured for short timeout
#1 : 1
COP configured for long timeout
End of enumeration elements list.
COPT : COP Watchdog Timeout
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
COP disabled
#01 : 01
COP timeout after 25 cycles for short timeout or 213 cycles for long timeout
#10 : 10
COP timeout after 28 cycles for short timeout or 216 cycles for long timeout
#11 : 11
COP timeout after 210 cycles for short timeout or 218 cycles for long timeout
End of enumeration elements list.
COPSTPEN : COP Stop Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
COP is disabled and the counter is reset in Stop modes
#1 : 1
COP is enabled in Stop modes
End of enumeration elements list.
COPDBGEN : COP Debug Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
COP is disabled and the counter is reset in Debug mode
#1 : 1
COP is enabled in Debug mode
End of enumeration elements list.
COPCLKSEL : COP Clock Select
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
LPO clock (1 kHz)
#01 : 01
MCGIRCLK
#10 : 10
OSCERCLK
#11 : 11
Bus clock
End of enumeration elements list.
Service COP
address_offset : 0x1104 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SRVCOP : Service COP Register
bits : 0 - 7 (8 bit)
access : write-only
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