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RSIM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CONTROL

ANA_TEST

ACTIVE_DELAY

MAC_MSB

MAC_LSB


CONTROL

RSIM Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONTROL CONTROL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLE_RF_OSC_REQ_EN BLE_RF_OSC_REQ_STAT BLE_RF_OSC_REQ_INT_EN BLE_RF_OSC_REQ_INT RF_OSC_EN GASKET_BYPASS_OVRD_EN GASKET_BYPASS_OVRD RF_OSC_BYPASS_EN BLE_ACTIVE_PORT_1_SEL BLE_ACTIVE_PORT_2_SEL BLE_DEEP_SLEEP_EXIT STOP_ACK_OVRD_EN STOP_ACK_OVRD RF_OSC_READY RF_OSC_READY_OVRD_EN RF_OSC_READY_OVRD BLOCK_RADIO_RESETS BLOCK_RADIO_OUTPUTS RADIO_RESET

BLE_RF_OSC_REQ_EN : BLE Ref Osc (Sysclk) Request Enable
bits : 0 - 0 (1 bit)
access : read-write

BLE_RF_OSC_REQ_STAT : BLE Ref Osc (Sysclk) Request Status
bits : 1 - 1 (1 bit)
access : read-only

BLE_RF_OSC_REQ_INT_EN : BLE Ref Osc (Sysclk) Request Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

BLE_RF_OSC_REQ_INT : BLE Ref Osc (Sysclk) Request Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-write

RF_OSC_EN : RF Ref Osc Enable [3:0]
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

RF Ref Osc will be controlled by the SoC or the BLE link layer

#0001 : 0001

RF Ref Osc on in Run/Wait

#0011 : 0011

RF Ref Osc on in Stop

#0111 : 0111

RF Ref Osc on in VLPR/VLPW

#1111 : 1111

RF Ref Osc on in VLPS

End of enumeration elements list.

GASKET_BYPASS_OVRD_EN : Gasket Bypass Override Enable
bits : 12 - 12 (1 bit)
access : read-write

GASKET_BYPASS_OVRD : Gasket Bypass Override
bits : 13 - 13 (1 bit)
access : read-write

RF_OSC_BYPASS_EN : RF Ref Osc Bypass Enable
bits : 14 - 14 (1 bit)
access : read-write

BLE_ACTIVE_PORT_1_SEL : BLE Active port 1 select
bits : 16 - 16 (1 bit)
access : read-write

BLE_ACTIVE_PORT_2_SEL : BLE Active port 2 select
bits : 17 - 17 (1 bit)
access : read-write

BLE_DEEP_SLEEP_EXIT : BLE Deep Sleep Exit
bits : 20 - 20 (1 bit)
access : read-write

STOP_ACK_OVRD_EN : Stop Acknowledge Override Enable
bits : 22 - 22 (1 bit)
access : read-write

STOP_ACK_OVRD : Stop Acknowledge Override
bits : 23 - 23 (1 bit)
access : read-write

RF_OSC_READY : RF Ref Osc Ready
bits : 24 - 24 (1 bit)
access : read-only

RF_OSC_READY_OVRD_EN : RF Ref Osc Ready Override Enable
bits : 25 - 25 (1 bit)
access : read-write

RF_OSC_READY_OVRD : RF Ref Osc Ready Override
bits : 26 - 26 (1 bit)
access : read-write

BLOCK_RADIO_RESETS : Block Radio Resets
bits : 28 - 28 (1 bit)
access : read-write

BLOCK_RADIO_OUTPUTS : Block Radio Outputs
bits : 29 - 29 (1 bit)
access : read-write

RADIO_RESET : Software Reset for the Radio
bits : 31 - 31 (1 bit)
access : read-write


ANA_TEST

RSIM Analog Test
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ANA_TEST ANA_TEST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATST_GATE_EN RADIO_ID

ATST_GATE_EN : ATST Transmission Gate Enables
bits : 0 - 3 (4 bit)
access : read-write

RADIO_ID : Radio Version ID number
bits : 24 - 27 (4 bit)
access : read-only

Enumeration:

#0001 : 0001

Apache 1.0

#0010 : 0010

Apache 1.1

#0011 : 0011

Apache 2.0

End of enumeration elements list.


ACTIVE_DELAY

RSIM BLE Active Delay
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACTIVE_DELAY ACTIVE_DELAY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLE_ACTIVE_FINE_DELAY BLE_ACTIVE_COARSE_DELAY

BLE_ACTIVE_FINE_DELAY : no description available
bits : 0 - 5 (6 bit)
access : read-write

BLE_ACTIVE_COARSE_DELAY : no description available
bits : 16 - 19 (4 bit)
access : read-write


MAC_MSB

RSIM MAC MSB
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MAC_MSB MAC_MSB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_ADDR_MSB

MAC_ADDR_MSB : MAC Address MSB
bits : 0 - 7 (8 bit)
access : read-only


MAC_LSB

RSIM MAC LSB
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MAC_LSB MAC_LSB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_ADDR_LSB

MAC_ADDR_LSB : MAC Address LSB
bits : 0 - 31 (32 bit)
access : read-only



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