\n
address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
TX Digital Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RADIO_DFT_MODE : Radio DFT Modes
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Normal Radio Operation, DFT not engaged.
#0001 : 0001
Carrier Frequency Only
#0010 : 0010
Pattern Register GFSK
#0011 : 0011
LFSR GFSK
#0100 : 0100
Pattern Register FSK
#0101 : 0101
LFSR FSK
#0110 : 0110
Pattern Register O-QPSK
#0111 : 0111
LFSR O-QPSK
#1000 : 1000
LFSR 802.15.4 Symbols
#1001 : 1001
PLL Modulation from RAM
#1010 : 1010
PLL Coarse Tune BIST
#1011 : 1011
PLL Frequency Synthesizer BIST
#1100 : 1100
High Port DAC BIST
#1101 : 1101
VCO Frequency Meter
End of enumeration elements list.
LFSR_LENGTH : LFSR Length
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 000
LFSR 9, tap mask 100010000
#001 : 001
LFSR 10, tap mask 1001000000
#010 : 010
LFSR 11, tap mask 11101000000
#011 : 011
LFSR 13, tap mask 1101100000000
#100 : 100
LFSR 15, tap mask 111010000000000
#101 : 101
LFSR 17, tap mask 11110000000000000
End of enumeration elements list.
LFSR_EN : LFSR Enable
bits : 7 - 7 (1 bit)
access : read-write
DFT_CLK_SEL : DFT Clock Selection
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
62.5 kHz
#001 : 001
125 kHz
#010 : 010
250 kHz
#011 : 011
500 kHz
#100 : 100
1 MHz
#101 : 101
2 MHz
#110 : 110
4 MHz
#111 : 111
RF OSC Clock
End of enumeration elements list.
TX_DFT_EN : DFT Modulation Enable
bits : 11 - 11 (1 bit)
access : read-write
SOC_TEST_SEL : Radio Clock Selector for SoC RF Clock Tests
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 00
No Clock Selected
#01 : 01
PLL Sigma Delta Clock, divided by 2
#10 : 10
Auxiliary PLL Clock, divided by 2
#11 : 11
RF Ref Osc clock, divided by 2
End of enumeration elements list.
TX_CAPTURE_POL : Polarity of the Input Data for the Transmitter
bits : 16 - 16 (1 bit)
access : read-write
FREQ_WORD_ADJ : Frequency Word Adjustment
bits : 22 - 31 (10 bit)
access : read-write
TX GFSK Filter Coefficients 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GFSK_FILTER_COEFF_MANUAL1 : GFSK Manual Filter Coefficient [31:0]
bits : 0 - 31 (32 bit)
access : read-write
TX FSK Modulation Levels
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSK_MODULATION_SCALE_0 : FSK Modulation Scale for a data 0
bits : 0 - 12 (13 bit)
access : read-write
FSK_MODULATION_SCALE_1 : FSK Modulation Scale for a data 1
bits : 16 - 28 (13 bit)
access : read-write
TX DFT Modulation Pattern
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFT_MOD_PATTERN : DFT Modulation Pattern
bits : 0 - 31 (32 bit)
access : read-write
TX DFT Control 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTUNE_BIST_GO : Start the Coarse Tune BIST
bits : 0 - 0 (1 bit)
access : read-write
CTUNE_BIST_FINISHED : Coarse Tune BIST has finished Tuning all Channels
bits : 1 - 1 (1 bit)
access : read-only
CTUNE_BIST_RESULT : Coarse Tune BIST Result
bits : 2 - 2 (1 bit)
access : read-only
CTUNE_BIST_THRSHLD : Maximum Difference Threshold for Coarse Tune BIST
bits : 4 - 7 (4 bit)
access : read-write
CTUNE_MAX_DIFF : Maximum Frequency Count Difference found by the Coarse Tune BIST
bits : 8 - 15 (8 bit)
access : read-only
CTUNE_MAX_DIFF_CH : Maximum Frequency Count Difference Radio Channel
bits : 16 - 22 (7 bit)
access : read-only
PA_AM_MOD_FREQ : RF Power Amplifier Amplitude Modulation Frequency
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
4 MHz
#001 : 001
2 MHz
#010 : 010
1 MHz
#011 : 011
500 kHz
#100 : 100
250 kHz
#101 : 101
125 kHz
#110 : 110
62.5 kHz
End of enumeration elements list.
PA_AM_MOD_ENTRIES : RF Power Amplifier Amplitude Modulation Table Entries
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
#001 : 001
2 entries
#010 : 010
3 entries
#011 : 011
4 entries
#100 : 100
5 entries
#101 : 101
6 entries
#110 : 110
7 entries
#111 : 111
8 entries
End of enumeration elements list.
PA_AM_MOD_EN : RF Power Amplifier Amplitude Modulation Enable
bits : 31 - 31 (1 bit)
access : read-write
TX DFT Control 2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYN_BIST_GO : Start the PLL Frequency Synthesizer BIST
bits : 0 - 0 (1 bit)
access : read-write
SYN_BIST_FINISHED : PLL Frequency Synthesizer BIST has finished trying to lock to Radio Channels
bits : 1 - 1 (1 bit)
access : read-only
SYN_BIST_RESULT : PLL Frequency Synthesizer BIST Result
bits : 2 - 2 (1 bit)
access : read-only
SYN_BIST_ALL_CHANNELS : PLL Frequency Synthesizer BIST All Channels
bits : 3 - 3 (1 bit)
access : read-write
FREQ_COUNT_THRESHOLD : Frequency Meter Count Difference Threshold
bits : 4 - 11 (8 bit)
access : read-write
HPM_INL_BIST_GO : Start the High Port Modulator DAC INL BIST
bits : 12 - 12 (1 bit)
access : read-write
HPM_INL_BIST_FINISHED : High Port Modulator DAC INL BIST has finished measuring the INL of the HPM DAC
bits : 13 - 13 (1 bit)
access : read-only
HPM_INL_BIST_RESULT : High Port Modulator DAC INL BIST Result
bits : 14 - 14 (1 bit)
access : read-only
HPM_DNL_BIST_GO : Start the High Port Modulator DAC DNL BIST
bits : 16 - 16 (1 bit)
access : read-write
HPM_DNL_BIST_FINISHED : High Port Modulator DAC DNL BIST has finished measuring the DNL of the HPM DAC
bits : 17 - 17 (1 bit)
access : read-only
HPM_DNL_BIST_RESULT : High Port Modulator DAC DNL BIST Result
bits : 18 - 18 (1 bit)
access : read-only
DFT_MAX_RAM_SIZE : Maximum RAM Address to use as Modulation
bits : 20 - 28 (9 bit)
access : read-write
TX Data Padding
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_PADDING_PAT_0 : Data Padding Pattern 0
bits : 0 - 7 (8 bit)
access : read-write
DATA_PADDING_PAT_1 : Data Padding Pattern 1
bits : 8 - 15 (8 bit)
access : read-write
DFT_LFSR_OUT : LFSR Output
bits : 16 - 30 (15 bit)
access : read-only
LRM : LFSR Reset Mask
bits : 31 - 31 (1 bit)
access : read-write
TX GFSK Modulator Control
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GFSK_MULTIPLY_TABLE_MANUAL : Manual GFSK Multiply Lookup Table Value
bits : 0 - 15 (16 bit)
access : read-write
GFSK_MI : GFSK Modulation Index
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
0.32
#01 : 01
0.50
#10 : 10
0.70
#11 : 11
1.00
End of enumeration elements list.
GFSK_MLD : Disable GFSK Multiply Lookup Table
bits : 20 - 20 (1 bit)
access : read-write
GFSK_FLD : Disable GFSK Filter Lookup Table
bits : 21 - 21 (1 bit)
access : read-write
GFSK_MOD_INDEX_SCALING : GFSK Modulation Index Scaling Factor
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
1
#001 : 001
1 + 1/32
#010 : 010
1 + 1/16
#011 : 011
1 + 1/8
#100 : 100
1 - 1/32
#101 : 101
1 - 1/16
#110 : 110
1 - 1/8
End of enumeration elements list.
TX_IMAGE_FILTER_OVRD_EN : TX Image Filter Override Enable
bits : 28 - 28 (1 bit)
access : read-write
TX_IMAGE_FILTER_0_OVRD : TX Image Filter 0 Override Control
bits : 29 - 29 (1 bit)
access : read-write
TX_IMAGE_FILTER_1_OVRD : TX Image Filter 1 Override Control
bits : 30 - 30 (1 bit)
access : read-write
TX_IMAGE_FILTER_2_OVRD : TX Image Filter 2 Override Control
bits : 31 - 31 (1 bit)
access : read-write
TX GFSK Filter Coefficients 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GFSK_FILTER_COEFF_MANUAL2 : GFSK Manual Filter Coefficients[63:32]
bits : 0 - 31 (32 bit)
access : read-write
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