\n
address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
Channel Configuration register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable_Signal
#10 : 2
LPUART0_Rx_Signal
#11 : 3
LPUART0_Tx_Signal
#10000 : 16
SPI0_Rx_Signal
#10001 : 17
SPI0_Tx_Signal
#10010 : 18
SPI1_Rx_Signal
#10011 : 19
SPI1_Tx_Signal
#10100 : 20
AESA_Input_FIFO_Signal
#10101 : 21
AESA_Output_FIFO_Signal
#10110 : 22
I2C0_Signal
#10111 : 23
I2C1_Signal
#11000 : 24
TPM0_Channel0_Signal
#11001 : 25
TPM0_Channel1_Signal
#11010 : 26
TPM0_Channel2_Signal
#11011 : 27
TPM0_Channel3_Signal
#100000 : 32
TPM1_Channel0_Signal
#100001 : 33
TPM1_Channel1_Signal
#100010 : 34
TPM2_Channel0_Signal
#100011 : 35
TPM2_Channel1_Signal
#101000 : 40
ADC0_Signal
#101010 : 42
CMP0_Signal
#101101 : 45
DAC0_Signal
#101111 : 47
CMT_Signal
#110001 : 49
PortA_Signal
#110010 : 50
PortB_Signal
#110011 : 51
PortC_Signal
#110110 : 54
TPM0_Overflow_Signal
#110111 : 55
TPM1_Overflow_Signal
#111000 : 56
TPM2_Overflow_Signal
#111001 : 57
TSI0_Signal
#111100 : 60
AlwaysOn60_Signal
#111101 : 61
AlwaysOn61_Signal
#111110 : 62
AlwaysOn62_Signal
#111111 : 63
AlwaysOn63_Signal
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
#1 : 1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
#1 : 1
DMA channel is enabled
End of enumeration elements list.
Channel Configuration register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable_Signal
#10 : 2
LPUART0_Rx_Signal
#11 : 3
LPUART0_Tx_Signal
#10000 : 16
SPI0_Rx_Signal
#10001 : 17
SPI0_Tx_Signal
#10010 : 18
SPI1_Rx_Signal
#10011 : 19
SPI1_Tx_Signal
#10100 : 20
AESA_Input_FIFO_Signal
#10101 : 21
AESA_Output_FIFO_Signal
#10110 : 22
I2C0_Signal
#10111 : 23
I2C1_Signal
#11000 : 24
TPM0_Channel0_Signal
#11001 : 25
TPM0_Channel1_Signal
#11010 : 26
TPM0_Channel2_Signal
#11011 : 27
TPM0_Channel3_Signal
#100000 : 32
TPM1_Channel0_Signal
#100001 : 33
TPM1_Channel1_Signal
#100010 : 34
TPM2_Channel0_Signal
#100011 : 35
TPM2_Channel1_Signal
#101000 : 40
ADC0_Signal
#101010 : 42
CMP0_Signal
#101101 : 45
DAC0_Signal
#101111 : 47
CMT_Signal
#110001 : 49
PortA_Signal
#110010 : 50
PortB_Signal
#110011 : 51
PortC_Signal
#110110 : 54
TPM0_Overflow_Signal
#110111 : 55
TPM1_Overflow_Signal
#111000 : 56
TPM2_Overflow_Signal
#111001 : 57
TSI0_Signal
#111100 : 60
AlwaysOn60_Signal
#111101 : 61
AlwaysOn61_Signal
#111110 : 62
AlwaysOn62_Signal
#111111 : 63
AlwaysOn63_Signal
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
#1 : 1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
#1 : 1
DMA channel is enabled
End of enumeration elements list.
Channel Configuration register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable_Signal
#10 : 2
LPUART0_Rx_Signal
#11 : 3
LPUART0_Tx_Signal
#10000 : 16
SPI0_Rx_Signal
#10001 : 17
SPI0_Tx_Signal
#10010 : 18
SPI1_Rx_Signal
#10011 : 19
SPI1_Tx_Signal
#10100 : 20
AESA_Input_FIFO_Signal
#10101 : 21
AESA_Output_FIFO_Signal
#10110 : 22
I2C0_Signal
#10111 : 23
I2C1_Signal
#11000 : 24
TPM0_Channel0_Signal
#11001 : 25
TPM0_Channel1_Signal
#11010 : 26
TPM0_Channel2_Signal
#11011 : 27
TPM0_Channel3_Signal
#100000 : 32
TPM1_Channel0_Signal
#100001 : 33
TPM1_Channel1_Signal
#100010 : 34
TPM2_Channel0_Signal
#100011 : 35
TPM2_Channel1_Signal
#101000 : 40
ADC0_Signal
#101010 : 42
CMP0_Signal
#101101 : 45
DAC0_Signal
#101111 : 47
CMT_Signal
#110001 : 49
PortA_Signal
#110010 : 50
PortB_Signal
#110011 : 51
PortC_Signal
#110110 : 54
TPM0_Overflow_Signal
#110111 : 55
TPM1_Overflow_Signal
#111000 : 56
TPM2_Overflow_Signal
#111001 : 57
TSI0_Signal
#111100 : 60
AlwaysOn60_Signal
#111101 : 61
AlwaysOn61_Signal
#111110 : 62
AlwaysOn62_Signal
#111111 : 63
AlwaysOn63_Signal
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
#1 : 1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
#1 : 1
DMA channel is enabled
End of enumeration elements list.
Channel Configuration register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable_Signal
#10 : 2
LPUART0_Rx_Signal
#11 : 3
LPUART0_Tx_Signal
#10000 : 16
SPI0_Rx_Signal
#10001 : 17
SPI0_Tx_Signal
#10010 : 18
SPI1_Rx_Signal
#10011 : 19
SPI1_Tx_Signal
#10100 : 20
AESA_Input_FIFO_Signal
#10101 : 21
AESA_Output_FIFO_Signal
#10110 : 22
I2C0_Signal
#10111 : 23
I2C1_Signal
#11000 : 24
TPM0_Channel0_Signal
#11001 : 25
TPM0_Channel1_Signal
#11010 : 26
TPM0_Channel2_Signal
#11011 : 27
TPM0_Channel3_Signal
#100000 : 32
TPM1_Channel0_Signal
#100001 : 33
TPM1_Channel1_Signal
#100010 : 34
TPM2_Channel0_Signal
#100011 : 35
TPM2_Channel1_Signal
#101000 : 40
ADC0_Signal
#101010 : 42
CMP0_Signal
#101101 : 45
DAC0_Signal
#101111 : 47
CMT_Signal
#110001 : 49
PortA_Signal
#110010 : 50
PortB_Signal
#110011 : 51
PortC_Signal
#110110 : 54
TPM0_Overflow_Signal
#110111 : 55
TPM1_Overflow_Signal
#111000 : 56
TPM2_Overflow_Signal
#111001 : 57
TSI0_Signal
#111100 : 60
AlwaysOn60_Signal
#111101 : 61
AlwaysOn61_Signal
#111110 : 62
AlwaysOn62_Signal
#111111 : 63
AlwaysOn63_Signal
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
#1 : 1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
#1 : 1
DMA channel is enabled
End of enumeration elements list.
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