Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x480 byte (0x0)
mem_usage : registers
protection : not protected
RX Digital Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_ADC_NEGEDGE : Receive ADC Negative Edge Selection
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Register ADC data on positive edge of clock
#1 : 1
Register ADC data on negative edge of clock
End of enumeration elements list.
RX_CH_FILT_BYPASS : Receive Channel Filter Bypass
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel filter is enabled.
#1 : 1
Disable and bypass channel filter.
End of enumeration elements list.
RX_ADC_RAW_EN : ADC Raw Mode selection
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
The decimation filter's 12bit output consists of two unfiltered 5-bit ADC samples. This is for test purposes only to observe ADC output via XCVR DMA or DTEST.
End of enumeration elements list.
RX_DEC_FILT_OSR : Decimation Filter Oversampling
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#0 : 0
OSR 2
#1 : 1
OSR 4
#010 : 10
OSR 8
#011 : 11
OSR 9
#100 : 100
OSR 16
#101 : 101
OSR 18
End of enumeration elements list.
RX_INTERP_EN : Interpolator Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interpolator is disabled.
#1 : 1
Interpolator is enabled.
End of enumeration elements list.
RX_NORM_EN : Normalizer Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normalizer is disabled.
#1 : 1
Normalizer is enabled.
End of enumeration elements list.
RX_RSSI_EN : RSSI Measurement Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
RSSI measurement is disabled.
#1 : 1
RSSI measurement is enabled.
End of enumeration elements list.
RX_AGC_EN : AGC Global Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
AGC is disabled.
#1 : 1
AGC is enabled.
End of enumeration elements list.
RX_DCOC_EN : DCOC Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
DCOC is disabled.
#1 : 1
DCOC is enabled.
End of enumeration elements list.
RX_DCOC_CAL_EN : DCOC Calibration Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
DCOC calibration is disabled.
#1 : 1
DCOC calibration is enabled.
End of enumeration elements list.
RX_IQ_SWAP : RX IQ Swap
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
IQ swap is disabled.
#1 : 1
IQ swap is enabled.
End of enumeration elements list.
AGC Control 3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AGC_UNFREEZE_TIME : AGC Unfreeze Time
bits : 0 - 12 (13 bit)
access : read-write
AGC_PDET_LO_DLY : AGC Peak Detect Low Delay
bits : 13 - 15 (3 bit)
access : read-write
AGC_RSSI_DELT_H2S : AGC_RSSI_DELT_H2S
bits : 16 - 22 (7 bit)
access : read-write
AGC_H2S_STEP_SZ : AGC_H2S_STEP_SZ
bits : 23 - 27 (5 bit)
access : read-write
AGC_UP_STEP_SZ : AGC Up Step Size
bits : 28 - 31 (4 bit)
access : read-write
DCOC Offset
address_offset : 0x1018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBF_OFFSET_I : DCOC BBF I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBF_OFFSET_Q : DCOC BBF Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0x1108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBF_OFFSET_I : DCOC BBF I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBF_OFFSET_Q : DCOC BBF Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0x11FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBF_OFFSET_I : DCOC BBF I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBF_OFFSET_Q : DCOC BBF Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0x12F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBF_OFFSET_I : DCOC BBF I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBF_OFFSET_Q : DCOC BBF Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0x13F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBF_OFFSET_I : DCOC BBF I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBF_OFFSET_Q : DCOC BBF Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
AGC Status
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BBF_PDET_LO_STAT : BBF Peak Detector Low Status
bits : 0 - 0 (1 bit)
access : read-only
BBF_PDET_HI_STAT : BBF Peak Detector High Status
bits : 1 - 1 (1 bit)
access : read-only
TZA_PDET_LO_STAT : TZA Peak Detector Low Status
bits : 2 - 2 (1 bit)
access : read-only
TZA_PDET_HI_STAT : TZA Peak Detector High Status
bits : 3 - 3 (1 bit)
access : read-only
CURR_AGC_IDX : Current AGC Gain Index
bits : 4 - 8 (5 bit)
access : read-only
AGC_FROZEN : AGC Frozen Status
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
AGC is not frozen.
#1 : 1
AGC is frozen.
End of enumeration elements list.
RSSI_ADC_RAW : ADC RAW RSSI Reading
bits : 16 - 23 (8 bit)
access : read-only
DCOC Offset
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBF_OFFSET_I : DCOC BBF I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBF_OFFSET_Q : DCOC BBF Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0x14F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBF_OFFSET_I : DCOC BBF I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBF_OFFSET_Q : DCOC BBF Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0x15F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBF_OFFSET_I : DCOC BBF I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBF_OFFSET_Q : DCOC BBF Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Calibration Alpha
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCOC_CAL_ALPHA_I : DCOC Calibration I-channel ALPHA constant
bits : 0 - 15 (16 bit)
access : read-only
DCOC_CAL_ALPHA_Q : DCOC_CAL_ALPHA_Q
bits : 16 - 31 (16 bit)
access : read-only
DCOC Offset
address_offset : 0x16FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBF_OFFSET_I : DCOC BBF I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBF_OFFSET_Q : DCOC BBF Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Calibration Beta
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCOC_CAL_BETA_I : DCOC_CAL_BETA_I
bits : 0 - 15 (16 bit)
access : read-only
DCOC_CAL_BETA_Q : DCOC_CAL_BETA_Q
bits : 16 - 31 (16 bit)
access : read-only
DCOC Calibration Gamma
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCOC_CAL_GAMMA_I : DCOC_CAL_GAMMA_I
bits : 0 - 15 (16 bit)
access : read-only
DCOC_CAL_GAMMA_Q : DCOC_CAL_GAMMA_Q
bits : 16 - 31 (16 bit)
access : read-only
DCOC Calibration IIR
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_CAL_IIR1A_IDX : DCOC Calibration IIR 1A Index
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#0 : 0
1/1
#1 : 1
1/4
#10 : 10
1/8
#11 : 11
1/16
End of enumeration elements list.
DCOC_CAL_IIR2A_IDX : DCOC Calibration IIR 2A Index
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#0 : 0
1/1
#1 : 1
1/4
#10 : 10
1/8
#11 : 11
1/16
End of enumeration elements list.
DCOC_CAL_IIR3A_IDX : DCOC Calibration IIR 3A Index
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#0 : 0
1/4
#1 : 1
1/8
#10 : 10
1/16
#11 : 11
1/32
End of enumeration elements list.
RSSI Control 0
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSSI_USE_VALS : RSSI Values Selection
bits : 0 - 0 (1 bit)
access : read-write
RSSI_HOLD_SRC : Hold RSSI Source Selection
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
#0 : 0
BTLE Preamble Detect
#1 : 1
Zigbee Preamble Detect
#10 : 10
BTLE access match (orf_access_match freeze)
#11 : 11
Zigbee LQI done (1=freeze, 0=run AGC)
End of enumeration elements list.
RSSI_HOLD_EN : RSSI Hold Enable
bits : 3 - 3 (1 bit)
access : read-write
RSSI_DEC_EN : RSSI Decimation Enable
bits : 4 - 4 (1 bit)
access : read-write
RSSI_IIR_CW_WEIGHT : RSSI IIR CW Weighting
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
#0 : 0
Bypass
#1 : 1
1/8
#10 : 10
1/16
#11 : 11
1/32
End of enumeration elements list.
RSSI_IIR_WEIGHT : RSSI IIR Weighting
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0 : 0
Bypass
#1 : 1
1/2
#0010 : 10
1/4
#0011 : 11
1/8
#0100 : 100
1/16
#0101 : 101
1/32
End of enumeration elements list.
RSSI_ADJ : RSSI Adjustment
bits : 24 - 31 (8 bit)
access : read-write
RSSI Control 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSSI_ED_THRESH0 : RSSI Energy Detect 0 Threshold
bits : 0 - 7 (8 bit)
access : read-write
RSSI_ED_THRESH1 : RSSI Energy Detect 1 Threshold
bits : 8 - 15 (8 bit)
access : read-write
RSSI_ED_THRESH0_H : RSSI Energy Detect 0 Hysteresis
bits : 16 - 19 (4 bit)
access : read-write
RSSI_ED_THRESH1_H : RSSI Energy Detect 1 Hysteresis
bits : 20 - 23 (4 bit)
access : read-write
RSSI_OUT : RSSI Reading
bits : 24 - 31 (8 bit)
access : read-only
DCOC Offset
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBF_OFFSET_I : DCOC BBF I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBF_OFFSET_Q : DCOC BBF Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Control 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_MAN : DCOC Manual Override
bits : 1 - 1 (1 bit)
access : read-write
DCOC_TRACK_EN : DCOC Tracking Enable
bits : 3 - 3 (1 bit)
access : read-write
DCOC_CORRECT_EN : DCOC Correction Enable
bits : 4 - 4 (1 bit)
access : read-write
DCOC_SIGN_SCALE_IDX : DCOC Sign Scaling
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
#00 : 00
1/4
#01 : 01
1/8
#10 : 10
1/16
#11 : 11
1/32
End of enumeration elements list.
DCOC_ALPHAC_SCALE_IDX : DCOC Alpha-C Scaling
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1/2
#01 : 01
1/4
#10 : 10
1/8
#11 : 11
1/16
End of enumeration elements list.
DCOC_ALPHA_RADIUS_IDX : Alpha-R Scaling
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 000
1
#001 : 001
1/2
#010 : 010
1/4
#011 : 011
1/8
#100 : 100
1/16
#101 : 101
1/32
#110 : 110
1/64
End of enumeration elements list.
DCOC_CAL_DURATION : DCOC Calibration Duration
bits : 15 - 19 (5 bit)
access : read-write
DCOC_CORR_DLY : DCOC Correction Delay
bits : 20 - 24 (5 bit)
access : read-write
DCOC_CORR_HOLD_TIME : DCOC Correction Hold Time
bits : 25 - 31 (7 bit)
access : read-write
TX Digital Control
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFT_MODE : Radio DFT Modes
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 000
Normal Radio Operation. DFT not engaged.
#001 : 001
Pattern Register Mode. TX DFT Modulation Pattern Register is shifted out as the transmission data stream. Note that the DFT_EN bit must be set.
#010 : 010
LFSR Data Mode. TX LFSR is used as the transmission data stream. Note that the LFSR_EN bit must be set.
#011 : 011
LFSR Symbol Mode. TX LFSR is used to create 802.15.4 symbols which are then converted to Chips and transmitted. Note that the LFSR_EN bit must be set.
#100 : 100
Not implemented on Apache 1.0, future use will allow a package pin to be used as the source of the TX data stream. Note that the DFT_EN bit must be set.
#101 : 101
Constant Frequency Mode. No data modulation is done, Radio transmits at the channel frequency selected.
#110 : 110
LFSR Tone Mode. TX LFSR is used to select the DFT Tone register to transmit, LFSR_EN bit must be set.
#111 : 111
Manual Tone Mode. TONE_SEL is used to select the DFT Tone register to transmit.
End of enumeration elements list.
DFT_EN : Radio DFT Mode Enable
bits : 3 - 3 (1 bit)
access : read-write
DFT_LFSR_LEN : DFT LFSR Length
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 000
LFSR 9, tap mask 100010000
#001 : 001
LFSR 10, tap mask 1001000000
#010 : 010
LFSR 11, tap mask 11101000000
#011 : 011
LFSR 13, tap mask 1101100000000
#100 : 100
LFSR 15, tap mask 111010000000000
#101 : 101
LFSR 17, tap mask 11110000000000000
End of enumeration elements list.
LFSR_EN : DFT LFSR Enable
bits : 7 - 7 (1 bit)
access : read-write
DFT_CLK_SEL : DFT Clock Selection
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
62.5 kHz
#001 : 001
125 kHz
#010 : 010
250 kHz
#011 : 011
500 kHz
#100 : 100
1 MHz
#101 : 101
2 MHz
#110 : 110
4 MHz
#111 : 111
Clock is off
End of enumeration elements list.
TONE_SEL : DFT Tone Selection
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 00
DFT Tone 0
#01 : 01
DFT Tone 1
#10 : 10
DFT Tone 2
#11 : 11
DFT Tone 3
End of enumeration elements list.
POL : Oversample Clock Capture Polarity
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Selects Even clock cycle
#1 : 1
Selects Odd clock cycle, a one cycle delay
End of enumeration elements list.
DP_SEL : Data Padding Pattern Select
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Selects DATA_PADDING_PATTERN_0 as the source for data padding
#1 : 1
Selects DATA_PADDING_PATTERN_1 as the source for data padding
End of enumeration elements list.
FREQ_WORD_ADJ : GFSK Frequency Word Adjustment
bits : 22 - 31 (10 bit)
access : read-write
TX Data Padding Pattern
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_PADDING_PAT_0 : Data Padding Pattern 0
bits : 0 - 7 (8 bit)
access : read-write
DATA_PADDING_PAT_1 : Data Padding Pattern 1
bits : 8 - 15 (8 bit)
access : read-write
DFT_LFSR_OUT : Transmit DFT LFSR Output
bits : 16 - 30 (15 bit)
access : read-only
LRM : LFSR Reset Mask
bits : 31 - 31 (1 bit)
access : read-write
TX GFSK Modulation Control
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GFSK_MULTIPLY_TABLE_MANUAL : GFSK Multiply Lookup Table Override Value
bits : 0 - 15 (16 bit)
access : read-write
GFSK_MI : GFSK Modulation Index
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
0.32
#01 : 01
0.50
#10 : 10
0.80
#11 : 11
1.00
End of enumeration elements list.
GFSK_MLD : GFSK Multiply Lookup Table Disable
bits : 20 - 20 (1 bit)
access : read-write
GFSK_SYMBOL_RATE : GFSK Symbol Rate
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
50 kHz
#001 : 001
100 kHz
#010 : 010
200 kHz
#011 : 011
1 MHz
#100 : 100
2 MHz
End of enumeration elements list.
GFSK_FLD : GFSK Filter Lookup Table Disable
bits : 28 - 28 (1 bit)
access : read-write
TX GFSK Filter Coefficients 2
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GFSK_FILTER_COEFF_MANUAL2 : GFSK Manual Filter Coefficients[63:32]
bits : 0 - 31 (32 bit)
access : read-write
TX GFSK Filter Coefficients 1
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GFSK_FILTER_COEFF_MANUAL1 : GFSK Manual Filter Coefficient [31:0]
bits : 0 - 31 (32 bit)
access : read-write
TX FSK Modulation Scale
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSK_MODULATION_SCALE_0 : FSK Modulation Scale for a data 0
bits : 0 - 12 (13 bit)
access : read-write
FSK_MODULATION_SCALE_1 : FSK Modulation Scale for a data 1
bits : 16 - 28 (13 bit)
access : read-write
TX DFT Modulation Pattern
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFT_MOD_PATTERN : DFT Modulation Pattern
bits : 0 - 31 (32 bit)
access : read-write
TX DFT Tones 0 and 1
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFT_TONE_1 : DFT Tone 1
bits : 0 - 12 (13 bit)
access : read-write
DFT_TONE_0 : DFT Tone 0
bits : 16 - 28 (13 bit)
access : read-write
DCOC TZA DC step
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_TZA_STEP_RCP : DCOC_TZA_STEP_RCP
bits : 0 - 12 (13 bit)
access : read-write
DCOC_TZA_STEP_GAIN : DCOC_TZA_STEP_GAIN
bits : 16 - 27 (12 bit)
access : read-write
TX DFT Tones 2 and 3
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFT_TONE_3 : DFT Tone 3
bits : 0 - 12 (13 bit)
access : read-write
DFT_TONE_2 : DFT Tone 2
bits : 16 - 28 (13 bit)
access : read-write
PLL Modulation Overrides
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODULATION_WORD_MANUAL : Manual Modulation Word
bits : 0 - 12 (13 bit)
access : read-write
MOD_DIS : Disable Modulation Word
bits : 15 - 15 (1 bit)
access : read-write
HPM_BANK_MANUAL : Manual HPM bank
bits : 16 - 23 (8 bit)
access : read-write
HPM_BANK_DIS : Disable HPM Bank
bits : 27 - 27 (1 bit)
access : read-write
HPM_LSB_MANUAL : Manual HPM LSB
bits : 28 - 29 (2 bit)
access : read-write
HPM_LSB_DIS : Disable HPM LSB
bits : 31 - 31 (1 bit)
access : read-write
PLL Channel Mapping
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL_NUM : Protocol specific Channel Number for PLL Frequency Mapping
bits : 0 - 6 (7 bit)
access : read-write
BOC : BLE Channel Number Override
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
BLE channel number comes from the BLE Link Layer
#1 : 1
BLE channel number comes from the CHANNEL_NUM register
End of enumeration elements list.
BMR : BLE MBAN Channel Remap
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
BLE channel 39 is mapped to BLE channel 39, 2.480 GHz
#1 : 1
BLE channel 39 is mapped to MBAN channel 39, 2.399 GHz
End of enumeration elements list.
ZOC : Zigbee Channel Number Override
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Zigbee channel number comes from the 802.15.4 Link Layer.
#1 : 1
Zigbee channel number comes from the CHANNEL_NUM register
End of enumeration elements list.
PLL Lock Detect
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CT_FAIL : Real time status of Coarse Tune Fail signal
bits : 0 - 0 (1 bit)
access : read-only
CTFF : CTUNE Failure Flag, held until cleared
bits : 1 - 1 (1 bit)
access : read-write
CS_FAIL : Real time status of Cycle Slip circuit
bits : 2 - 2 (1 bit)
access : read-only
CSFF : Cycle Slip Failure Flag, held until cleared
bits : 3 - 3 (1 bit)
access : read-write
FT_FAIL : Real time status of Frequency Target Failure
bits : 4 - 4 (1 bit)
access : read-only
FTFF : Frequency Target Failure Flag
bits : 5 - 5 (1 bit)
access : read-write
TAFF : TSM Abort Failure Flag
bits : 7 - 7 (1 bit)
access : read-write
CTUNE_LDF_LEV : CTUNE Lock Detect Fail Level
bits : 8 - 11 (4 bit)
access : read-write
FTF_RX_THRSH : RX Frequency Target Fail Threshold
bits : 12 - 17 (6 bit)
access : read-write
FTW_RX : RX Frequency Target Window time select
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
4 us
#1 : 1
8 us
End of enumeration elements list.
FTF_TX_THRSH : TX Frequency Target Fail Threshold
bits : 20 - 25 (6 bit)
access : read-write
FTW_TX : TX Frequency Target Window time select
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
4 us
#1 : 1
8 us
End of enumeration elements list.
PLL High Port Modulation Control
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HPM_SDM_MANUAL : PLL HPM SDM MANUAL
bits : 0 - 9 (10 bit)
access : read-write
HPFF : HPM SDM Invalid Flag
bits : 13 - 13 (1 bit)
access : read-write
HP_SDM_INV : Invert HPM SDM
bits : 14 - 14 (1 bit)
access : read-write
HP_SDM_DIS : Disable HPM SDM
bits : 15 - 15 (1 bit)
access : read-write
HPM_LFSR_LEN : HPM LFSR Length
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 000
LFSR 9, tap mask 100010000
#001 : 001
LFSR 10, tap mask 1001000000
#010 : 010
LFSR 11, tap mask 11101000000
#011 : 011
LFSR 13, tap mask 1101100000000
#100 : 100
LFSR 15, tap mask 111010000000000
#101 : 101
LFSR 17, tap mask 11110000000000000
End of enumeration elements list.
HP_DTH_SCL : HPM Dither Scale
bits : 20 - 20 (1 bit)
access : read-write
HPM_DTH_EN : Dither Enable for HPM LFSR
bits : 23 - 23 (1 bit)
access : read-write
HPM_SCALE : HPM Scale Factor
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
No Scaling
#01 : 01
Multiply by 2
#10 : 10
Divide by 2
End of enumeration elements list.
HP_MOD_INV : HPM Invert
bits : 31 - 31 (1 bit)
access : read-write
PLL HPM Calibration Control
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HPM_CAL_FACTOR : High Port Modulation Calibration Factor
bits : 0 - 12 (13 bit)
access : read-only
HP_CAL_DIS : no description available
bits : 15 - 15 (1 bit)
access : read-write
HPM_CAL_FACTOR_MANUAL : HPM Manual Calibration Factor
bits : 16 - 28 (13 bit)
access : read-write
HP_CAL_ARY : High Port Modulation Calibration Array Size
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
128
#1 : 1
256
End of enumeration elements list.
HP_CAL_TIME : High Port Modulation Calibration Time
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
25 us
#1 : 1
50 us
End of enumeration elements list.
PLL Cycle Slip Lock Detect Configuration and HPM Calibration 1
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_1 : High Port Modulation Counter Value 1
bits : 0 - 16 (17 bit)
access : read-only
CS_WT : Cycle Slip Wait Time
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 000
128 us
#001 : 001
256 us
#010 : 010
384 us
#011 : 011
512 us
#100 : 100
640 us
#101 : 101
768 us
#110 : 110
896 us
#111 : 111
1024 us
End of enumeration elements list.
CS_FW : Cycle Slip Flag Window
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
8 us
#001 : 001
16 us
#010 : 010
24 us
#011 : 011
32 us
#100 : 100
64 us
#101 : 101
96 us
#110 : 110
128 us
#111 : 111
256 us
End of enumeration elements list.
CS_FCNT : Cycle Slip Flag Count
bits : 28 - 31 (4 bit)
access : read-write
DCOC Control 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBF_DCOC_STEP : DCOC BBF Step Size
bits : 0 - 8 (9 bit)
access : read-write
TRACK_FROM_ZERO : Track from Zero
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Track from current I/Q sample.
#1 : 1
Track from zero.
End of enumeration elements list.
BBA_CORR_POL : BBA Correction Polarity
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal polarity.
#1 : 1
Negative polarity. This should be set if the ADC output is inverted, or if the BBA DACs were implemented with negative polarity.
End of enumeration elements list.
TZA_CORR_POL : TZA Correction Polarity
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal polarity.
#1 : 1
Negative polarity. This should be set if the ADC output is inverted, or if the TZA DACs were implemented with negative polarity.
End of enumeration elements list.
PLL Cycle Slip Lock Detect Configuration and HPM Calibration 2
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_2 : High Port Modulation Counter Value 2
bits : 0 - 16 (17 bit)
access : read-only
CS_RC : Cycle Slip Recycle
bits : 20 - 20 (1 bit)
access : read-write
CS_FT : Cycle Slip Flag Timeout
bits : 24 - 28 (5 bit)
access : read-write
PLL HPM SDM Fraction
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HPM_NUM_SELECTED : HPM_NUM_SELECTED
bits : 0 - 9 (10 bit)
access : read-only
HPM_DENOM : High Port Modulation Denominator
bits : 16 - 25 (10 bit)
access : read-write
PLL Low Port Modulation Control
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_LOOP_DIVIDER_MANUAL : PLL Loop Divider Manual
bits : 0 - 5 (6 bit)
access : read-write
PLL_LD_DIS : PLL Loop Divider Disable
bits : 11 - 11 (1 bit)
access : read-write
LPFF : LPM SDM Invalid Flag
bits : 13 - 13 (1 bit)
access : read-write
LPM_SDM_INV : Invert LPM SDM
bits : 14 - 14 (1 bit)
access : read-write
LPM_SDM_DIS : Disable LPM SDM
bits : 15 - 15 (1 bit)
access : read-write
LPM_DTH_SCL : LPM Dither Scale
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0101 : 0101
-128 to 96
#0110 : 0110
-256 to 192
#0111 : 0111
-512 to 384
#1000 : 1000
-1024 to 768
#1001 : 1001
-2048 to 1536
#1010 : 1010
-4096 to 3072
#1011 : 1011
-8192 to 6144
End of enumeration elements list.
LPM_D_CTRL : LPM Dither Control in Override Mode
bits : 22 - 22 (1 bit)
access : read-write
LPM_D_OVRD : LPM Dither Override Mode Select
bits : 23 - 23 (1 bit)
access : read-write
LPM_SCALE : LPM Scale Factor
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
No Scaling
#0001 : 0001
Multiply by 2
#0010 : 0010
Multiply by 4
#0011 : 0011
Multiply by 8
#0100 : 0100
Multiply by 16
#0101 : 0101
Multiply by 32
#0110 : 0110
Multiply by 64
#0111 : 0111
Multiply by 128
#1000 : 1000
Multiply by 256
#1001 : 1001
Multiply by 512
#1010 : 1010
Multiply by 1024
#1011 : 1011
Multiply by 2048
End of enumeration elements list.
PLL Low Port SDM Control 1
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPM_INTG_SELECTED : Low Port Modulation Integer Value Selected
bits : 0 - 6 (7 bit)
access : read-only
LPM_INTG : Low Port Modulation Integer Manual Value
bits : 16 - 22 (7 bit)
access : read-write
SDM_MAP_DIS : SDM Mapping Disable
bits : 31 - 31 (1 bit)
access : read-write
PLL Low Port SDM Control 2
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPM_NUM : Low Port Modulation Numerator
bits : 0 - 27 (28 bit)
access : read-write
PLL Low Port SDM Control 3
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPM_DENOM : Low Port Modulation Denominator
bits : 0 - 27 (28 bit)
access : read-write
PLL Low Port SDM Numerator Applied
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LPM_NUM_SELECTED : Low Port Modulation Numerator Applied
bits : 0 - 27 (28 bit)
access : read-only
PLL Low Port SDM Denominator Applied
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LPM_DENOM_SELECTED : Low Port Modulation Denominator Selected
bits : 0 - 27 (28 bit)
access : read-only
PLL Delay Matching
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LP_SDM_DELAY : LP_SDM_DELAY
bits : 0 - 3 (4 bit)
access : read-write
HPM_SDM_DELAY : HPM_SDM_DELAY
bits : 8 - 11 (4 bit)
access : read-write
HPM_BANK_DELAY : HPM Bank Delay
bits : 16 - 19 (4 bit)
access : read-write
PLL Coarse Tune Control
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTUNE_TARGET_MANUAL : CTUNE Target Manual
bits : 0 - 11 (12 bit)
access : read-write
CTUNE_TD : CTUNE Target Disable
bits : 15 - 15 (1 bit)
access : read-write
CTUNE_ADJUST : CTUNE Count Adjustment
bits : 16 - 19 (4 bit)
access : read-write
CTUNE_MANUAL : CTUNE Manual
bits : 24 - 30 (7 bit)
access : read-write
CTUNE_DIS : CTUNE Disable
bits : 31 - 31 (1 bit)
access : read-write
PLL Coarse Tune Count 6
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CTUNE_COUNT_6 : CTUNE Count 6
bits : 0 - 11 (12 bit)
access : read-only
PLL Coarse Tune Counts 5 and 4
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CTUNE_COUNT_4 : CTUNE Count 4
bits : 0 - 11 (12 bit)
access : read-only
CTUNE_COUNT_5 : CTUNE Count 5
bits : 16 - 27 (12 bit)
access : read-only
PLL Coarse Tune Counts 3 and 2
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CTUNE_COUNT_2 : CTUNE Count 2
bits : 0 - 11 (12 bit)
access : read-only
CTUNE_COUNT_3 : CTUNE Count 3
bits : 16 - 27 (12 bit)
access : read-only
PLL Coarse Tune Counts 1 and 0
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CTUNE_COUNT_0 : CTUNE Count 0
bits : 0 - 11 (12 bit)
access : read-only
CTUNE_COUNT_1 : CTUNE Count 1
bits : 16 - 27 (12 bit)
access : read-only
PLL Coarse Tune Results
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CTUNE_SELECTED : Coarse Tune Band to VCO
bits : 0 - 6 (7 bit)
access : read-only
CTUNE_BEST_DIFF : Coarse Tune Absolute Best Difference
bits : 8 - 15 (8 bit)
access : read-only
CTUNE_FREQ_TARGET : Coarse Tune Frequency Target
bits : 16 - 27 (12 bit)
access : read-only
DCOC Control 2
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBF_DCOC_STEP_RECIP : DCOC BBF Reciprocal of Step Size
bits : 0 - 12 (13 bit)
access : read-write
Transceiver Control
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PROTOCOL : Radio Protocol Selection
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 000
BLE
#001 : 001
BLE in MBAN
#010 : 010
BLE overlap MBAN
#100 : 100
Zigbee
#101 : 101
802.15.4j
#110 : 110
128 Channel FSK
#111 : 111
128 Channel GFSK
End of enumeration elements list.
TGT_PWR_SRC : Target Power Source
bits : 4 - 5 (2 bit)
access : read-write
REF_CLK_FREQ : Radio Reference Clock Frequency
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
32 MHz
End of enumeration elements list.
Transceiver Status
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TSM_COUNT : TSM Count
bits : 0 - 7 (8 bit)
access : read-only
PLL_SEQ_STATE : PLL Sequence State
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
#0 : 0
PLL OFF
#10 : 10
HPMCAL2
#0011 : 11
CTUNE_SETTLE
#0110 : 110
HPMCAL1
#1000 : 1000
HPMCAL1_SETTLE
#1100 : 1100
HPMCAL2_SETTLE
#1111 : 1111
PLLREADY
End of enumeration elements list.
RX_MODE : Receive Mode
bits : 12 - 12 (1 bit)
access : read-only
TX_MODE : Transmit Mode
bits : 13 - 13 (1 bit)
access : read-only
BTLE_SYSCLK_REQ : BTLE System Clock Request
bits : 16 - 16 (1 bit)
access : read-only
RIF_LL_ACTIVE : Link Layer Active Indication
bits : 17 - 17 (1 bit)
access : read-only
XTAL_READY : RF Osciallator Xtal Ready
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
Indicates that the RF Oscillator is disabled or has not completed its warmup.
#1 : 1
Indicates that the RF Oscillator has completed its warmup count and is ready for use.
End of enumeration elements list.
SOC_USING_RF_OSC_CLK : SOC Using RF Clock Indication
bits : 19 - 19 (1 bit)
access : read-only
Soft Reset
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCOC Offset
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBF_OFFSET_I : DCOC BBF I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBF_OFFSET_Q : DCOC BBF Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
Overwrite Version
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVERWRITE_VER : Overwrite Version Number.
bits : 0 - 7 (8 bit)
access : read-write
DMA Control
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_I_EN : DMA I Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transceiver I channel DMA disabled.
#1 : 1
Enable the transceiver DMA engine to store RX_DIG I channel outputs to system memory.
End of enumeration elements list.
DMA_Q_EN : DMA Q Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transceiver Q channel DMA disabled.
#1 : 1
Enable the transceiver DMA engine to store RX_DIG Q channel outputs to system memory.
End of enumeration elements list.
DMA Data
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DMA_DATA_11_0 : DMA_DATA_11_0
bits : 0 - 11 (12 bit)
access : read-only
DMA_DATA_27_16 : DMA_DATA_27_16
bits : 16 - 27 (12 bit)
access : read-only
Digital Test Control
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTEST_PAGE : DTEST Page Selector
bits : 0 - 5 (6 bit)
access : read-write
DTEST_EN : DTEST Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables DTEST. The IC's DTEST pins assume their mission function.
#1 : 1
Enables DTEST. The contents of the selected page (DTEST_PAGE) will appear on the IC's DTEST output pins.
End of enumeration elements list.
GPIO0_OVLAY_PIN : GPIO 0 Overlay Pin
bits : 8 - 11 (4 bit)
access : read-write
GPIO1_OVLAY_PIN : GPIO 1 Overlay Pin
bits : 12 - 15 (4 bit)
access : read-write
TSM_GPIO_OVLAY_0 : TSM GPIO 0 Overlay Pin
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
there is no overlay, and the DTEST Page Table dictates the node that appears on each DTEST pin.
#1 : 1
the register GPIO0_OVLAY_PIN[3:0] selects the DTEST pin on which GPIO0_TRIG_EN will appear.
End of enumeration elements list.
TSM_GPIO_OVLAY_1 : TSM GPIO 1 Overlay Pin
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
there is no overlay, and the DTEST Page Table dictates the node that appears on each DTEST pin.
#1 : 1
the register GPIO1_OVLAY_PIN[3:0] selects the DTEST pin on which GPIO1_TRIG_EN will appear.
End of enumeration elements list.
DTEST_SHFT : DTEST Shift Control
bits : 24 - 26 (3 bit)
access : read-write
RAW_MODE_I : DTEST Raw Mode Enable for I Channel
bits : 28 - 28 (1 bit)
access : read-write
RAW_MODE_Q : DTEST Raw Mode Enable for Q Channel
bits : 29 - 29 (1 bit)
access : read-write
Packet Buffer Control Register
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB_PROTECT : PB Protect
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Incoming received packets overwrite Packet Buffer contents (default)
#1 : 1
Incoming received packets are blocked from overwriting Packet Buffer contents
End of enumeration elements list.
DCOC Control 3
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBF_DCOC_INIT_I : DCOC BBF Init I
bits : 0 - 5 (6 bit)
access : read-write
BBF_DCOC_INIT_Q : DCOC BBF Init Q
bits : 8 - 13 (6 bit)
access : read-write
TZA_DCOC_INIT_I : DCOC TZA Init I
bits : 16 - 23 (8 bit)
access : read-write
TZA_DCOC_INIT_Q : DCOC TZA Init Q
bits : 24 - 31 (8 bit)
access : read-write
Transceiver Sequence Manager Control
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FORCE_TX_EN : Force Transmit Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
TSM Idle
#1 : 1
TSM executes a TX sequence
End of enumeration elements list.
FORCE_RX_EN : Force Receive Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
TSM Idle
#1 : 1
TSM executes a RX sequence
End of enumeration elements list.
PA_RAMP_SEL : PA Ramp Selection
bits : 4 - 5 (2 bit)
access : read-write
DATA_PADDING_EN : Data Padding Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable TX Data Padding
#1 : 1
Enable TX Data Padding
End of enumeration elements list.
TX_ABORT_DIS : Transmit Abort Disable
bits : 16 - 16 (1 bit)
access : read-write
RX_ABORT_DIS : Receive Abort Disable
bits : 17 - 17 (1 bit)
access : read-write
ABORT_ON_CTUNE : Abort On Coarse Tune Lock Detect Failure
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
don't allow TSM abort on Coarse Tune Unlock Detect
#1 : 1
allow TSM abort on Coarse Tune Unlock Detect
End of enumeration elements list.
ABORT_ON_CYCLE_SLIP : Abort On Cycle Slip Lock Detect Failure
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
don't allow TSM abort on Cycle Slip Unlock Detect
#1 : 1
allow TSM abort on Cycle Slip Unlock Detect
End of enumeration elements list.
ABORT_ON_FREQ_TARG : Abort On Frequency Target Lock Detect Failure
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
don't allow TSM abort on Frequency Target Unlock Detect
#1 : 1
allow TSM abort on Frequency Target Unlock Detect
End of enumeration elements list.
BKPT : TSM Breakpoint
bits : 24 - 31 (8 bit)
access : read-write
End of Sequence Control
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
END_OF_TX_WU : End of TX Warmup
bits : 0 - 7 (8 bit)
access : read-write
END_OF_TX_WD : End of TX Warmdown
bits : 8 - 15 (8 bit)
access : read-write
END_OF_RX_WU : End of RX Warmup
bits : 16 - 23 (8 bit)
access : read-write
END_OF_RX_WD : End of RX Warmdown
bits : 24 - 31 (8 bit)
access : read-write
TSM Override 0
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_REG_EN_OVRD_EN : Override control for PLL_REG_EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of PLL_REG_EN_OVRD to override the signal "pll_reg_en".
End of enumeration elements list.
PLL_REG_EN_OVRD : Override value for PLL_REG_EN
bits : 1 - 1 (1 bit)
access : read-write
PLL_VCO_REG_EN_OVRD_EN : Override control for PLL_VCO_REG_EN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of PLL_VCO_REG_EN_OVRD to override the signal "pll_vco_reg_en".
End of enumeration elements list.
PLL_VCO_REG_EN_OVRD : Override value for PLL_VCO_REG_EN
bits : 3 - 3 (1 bit)
access : read-write
QGEN_REG_EN_OVRD_EN : Override control for QGEN_REG_EN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of QGEN_REG_EN_OVRD to override the signal "qgen_reg_en".
End of enumeration elements list.
QGEN_REG_EN_OVRD : Override value for QGEN_REG_EN
bits : 5 - 5 (1 bit)
access : read-write
TCA_TX_REG_EN_OVRD_EN : Override control for TCA_TX_REG_EN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of TCA_TX_REG_EN_OVRD to override the signal "tca_tx_reg_en".
End of enumeration elements list.
TCA_TX_REG_EN_OVRD : Override value for TCA_TX_REG_EN
bits : 7 - 7 (1 bit)
access : read-write
ADC_ANA_REG_EN_OVRD_EN : Override control for ADC_ANA_REG_EN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of ADC_ANA_REG_EN_OVRD to override the signal "adc_ana_reg_en".
End of enumeration elements list.
ADC_ANA_REG_EN_OVRD : Override value for ADC_ANA_REG_EN
bits : 9 - 9 (1 bit)
access : read-write
ADC_DIG_REG_EN_OVRD_EN : Override control for ADC_DIG_REG_EN
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of ADC_DIG_REG_EN_OVRD to override the signal "adc_dig_reg_en".
End of enumeration elements list.
ADC_DIG_REG_EN_OVRD : Override value for ADC_DIG_REG_EN
bits : 11 - 11 (1 bit)
access : read-write
XTAL_PLL_REF_CLK_EN_OVRD_EN : Override control for XTAL_PLL_REF_CLK_EN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of XTAL_PLL_REF_CLK_EN_OVRD to override the signal "xtal_pll_ref_clk_en".
End of enumeration elements list.
XTAL_PLL_REF_CLK_EN_OVRD : Override value for XTAL_PLL_REF_CLK_EN
bits : 13 - 13 (1 bit)
access : read-write
XTAL_ADC_REF_CLK_EN_OVRD_EN : Override control for XTAL_ADC_REF_CLK_EN
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of XTAL_ADC_REF_CLK_EN_OVRD to override the signal "xtal_adc_ref_clk_en".
End of enumeration elements list.
XTAL_ADC_REF_CLK_EN_OVRD : Override value for XTAL_ADC_REF_CLK_EN
bits : 15 - 15 (1 bit)
access : read-write
PLL_VCO_AUTOTUNE_EN_OVRD_EN : Override control for PLL_VCO_AUTOTUNE_EN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of PLL_VCO_AUTOTUNE_EN_OVRD to override the signal "pll_vco_autotune_en".
End of enumeration elements list.
PLL_VCO_AUTOTUNE_EN_OVRD : Override value for PLL_VCO_AUTOTUNE_EN
bits : 17 - 17 (1 bit)
access : read-write
PLL_CYCLE_SLIP_LD_EN_OVRD_EN : Override control for PLL_CYCLE_SLIP_LD_EN
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of PLL_CYCLE_SLIP_LD_EN_OVRD to override the signal "pll_cycle_slip_ld_en".
End of enumeration elements list.
PLL_CYCLE_SLIP_LD_EN_OVRD : Override value for PLL_CYCLE_SLIP_LD_EN
bits : 19 - 19 (1 bit)
access : read-write
PLL_VCO_EN_OVRD_EN : Override control for PLL_VCO_EN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of PLL_VCO_EN_OVRD to override the signal "pll_vco_en".
End of enumeration elements list.
PLL_VCO_EN_OVRD : Override value for PLL_VCO_EN
bits : 21 - 21 (1 bit)
access : read-write
PLL_VCO_BUF_RX_EN_OVRD_EN : Override control for PLL_VCO_BUF_RX_EN
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of PLL_VCO_BUF_RX_EN_OVRD to override the signal "pll_vco_buf_rx_en".
End of enumeration elements list.
PLL_VCO_BUF_RX_EN_OVRD : Override value for PLL_VCO_BUF_RX_EN
bits : 23 - 23 (1 bit)
access : read-write
PLL_VCO_BUF_TX_EN_OVRD_EN : Override control for PLL_VCO_BUF_TX_EN
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of PLL_VCO_BUF_TX_EN_OVRD to override the signal "pll_vco_buf_tx_en".
End of enumeration elements list.
PLL_VCO_BUF_TX_EN_OVRD : Override value for PLL_VCO_BUF_TX_EN
bits : 25 - 25 (1 bit)
access : read-write
PLL_PA_BUF_EN_OVRD_EN : Override control for PLL_PA_BUF_EN
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of PLL_PA_BUF_EN_OVRD to override the signal "pll_pa_buf_en".
End of enumeration elements list.
PLL_PA_BUF_EN_OVRD : Override value for PLL_PA_BUF_EN
bits : 27 - 27 (1 bit)
access : read-write
PLL_LDV_EN_OVRD_EN : Override control for PLL_LDV_EN
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of PLL_LDV_EN_OVRD to override the signal "pll_ldv_en".
End of enumeration elements list.
PLL_LDV_EN_OVRD : Override value for PLL_LDV_EN
bits : 29 - 29 (1 bit)
access : read-write
PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_EN : Override control for PLL_RX_LDV_RIPPLE_MUX_EN
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of PLL_RX_LDV_RIPPLE_MUX_EN_OVRD to override the signal "pll_rx_ldv_ripple_mux_en".
End of enumeration elements list.
PLL_RX_LDV_RIPPLE_MUX_EN_OVRD : Override value for PLL_RX_LDV_RIPPLE_MUX_EN
bits : 31 - 31 (1 bit)
access : read-write
TSM Override 1
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_EN : Override control for PLL_TX_LDV_RIPPLE_MUX_EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of PLL_TX_LDV_RIPPLE_MUX_EN_OVRD to override the signal "pll_tx_ldv_ripple_mux_en".
End of enumeration elements list.
PLL_TX_LDV_RIPPLE_MUX_EN_OVRD : Override value for PLL_TX_LDV_RIPPLE_MUX_EN
bits : 1 - 1 (1 bit)
access : read-write
PLL_FILTER_CHARGE_EN_OVRD_EN : Override control for PLL_FILTER_CHARGE_EN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of PLL_FILTER_CHARGE_EN_OVRD to override the signal "pll_filter_charge_en".
End of enumeration elements list.
PLL_FILTER_CHARGE_EN_OVRD : Override value for PLL_FILTER_CHARGE_EN
bits : 3 - 3 (1 bit)
access : read-write
PLL_PHDET_EN_OVRD_EN : Override control for PLL_PHDET_EN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of PLL_PHDET_EN_OVRD to override the signal "pll_phdet_en".
End of enumeration elements list.
PLL_PHDET_EN_OVRD : Override value for PLL_PHDET_EN
bits : 5 - 5 (1 bit)
access : read-write
QGEN25_EN_OVRD_EN : Override control for QGEN25_EN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of QGEN25_EN_OVRD to override the signal "qgen25_en".
End of enumeration elements list.
QGEN25_EN_OVRD : Override value for QGEN25_EN
bits : 7 - 7 (1 bit)
access : read-write
TX_EN_OVRD_EN : Override control for TX_EN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of TX_EN_OVRD to override the signal "tx_en".
End of enumeration elements list.
TX_EN_OVRD : Override value for TX_EN
bits : 9 - 9 (1 bit)
access : read-write
ADC_EN_OVRD_EN : Override control for ADC_EN
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of ADC_EN_OVRD to override the signal "adc_en".
End of enumeration elements list.
ADC_EN_OVRD : Override value for ADC_EN
bits : 11 - 11 (1 bit)
access : read-write
ADC_BIAS_EN_OVRD_EN : Override control for ADC_BIAS_EN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of ADC_BIAS_EN_OVRD to override the signal "adc_bias_en".
End of enumeration elements list.
ADC_BIAS_EN_OVRD : Override value for ADC_BIAS_EN
bits : 13 - 13 (1 bit)
access : read-write
ADC_CLK_EN_OVRD_EN : Override control for ADC_CLK_EN
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of ADC_CLK_EN_OVRD to override the signal "adc_clk_en".
End of enumeration elements list.
ADC_CLK_EN_OVRD : Override value for ADC_CLK_EN
bits : 15 - 15 (1 bit)
access : read-write
ADC_I_ADC_EN_OVRD_EN : Override control for ADC_I_ADC_EN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of ADC_I_ADC_EN_OVRD to override the signal "adc_i_adc_en".
End of enumeration elements list.
ADC_I_ADC_EN_OVRD : Override value for ADC_I_ADC_EN
bits : 17 - 17 (1 bit)
access : read-write
ADC_Q_ADC_EN_OVRD_EN : Override control for ADC_Q_ADC_EN
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of ADC_Q_ADC_EN_OVRD to override the signal "adc_q_adc_en".
End of enumeration elements list.
ADC_Q_ADC_EN_OVRD : Override value for ADC_Q_ADC_EN
bits : 19 - 19 (1 bit)
access : read-write
ADC_DAC1_EN_OVRD_EN : Override control for ADC_DAC1_EN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of ADC_DAC1_EN_OVRD to override the signal "adc_dac1_en".
End of enumeration elements list.
ADC_DAC1_EN_OVRD : Override value for ADC_DAC1_EN
bits : 21 - 21 (1 bit)
access : read-write
ADC_DAC2_EN_OVRD_EN : Override control for ADC_DAC2_EN
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of ADC_DAC2_EN_OVRD to override the signal "adc_dac2_en".
End of enumeration elements list.
ADC_DAC2_EN_OVRD : Override value for ADC_DAC2_EN
bits : 23 - 23 (1 bit)
access : read-write
ADC_RST_EN_OVRD_EN : Override control for ADC_RST_EN
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of ADC_RST_EN_OVRD to override the signal "adc_rst_en".
End of enumeration elements list.
ADC_RST_EN_OVRD : Override value for ADC_RST_EN
bits : 25 - 25 (1 bit)
access : read-write
BBF_I_EN_OVRD_EN : Override control for BBF_I_EN
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of BBF_I_EN_OVRD to override the signal "bbf_i_en".
End of enumeration elements list.
BBF_I_EN_OVRD : Override value for BBF_I_EN
bits : 27 - 27 (1 bit)
access : read-write
BBF_Q_EN_OVRD_EN : Override control for BBF_Q_EN
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of BBF_Q_EN_OVRD to override the signal "bbf_q_en".
End of enumeration elements list.
BBF_Q_EN_OVRD : Override value for BBF_Q_EN
bits : 29 - 29 (1 bit)
access : read-write
BBF_PDET_EN_OVRD_EN : Override control for BBF_PDET_EN
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of BBF_PDET_EN_OVRD to override the signal "bbf_pdet_en".
End of enumeration elements list.
BBF_PDET_EN_OVRD : Override value for BBF_PDET_EN
bits : 31 - 31 (1 bit)
access : read-write
TSM Override 2
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBF_DCOC_EN_OVRD_EN : Override control for BBF_DCOC_EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of BBF_DCOC_EN_OVRD to override the signal "bbf_dcoc_en".
End of enumeration elements list.
BBF_DCOC_EN_OVRD : Override value for BBF_DCOC_EN
bits : 1 - 1 (1 bit)
access : read-write
TCA_EN_OVRD_EN : Override control for TCA_EN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of TCA_EN_OVRD to override the signal "tca_en".
End of enumeration elements list.
TCA_EN_OVRD : Override value for TCA_EN
bits : 3 - 3 (1 bit)
access : read-write
TZA_I_EN_OVRD_EN : Override control for TZA_I_EN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of TZA_I_EN_OVRD to override the signal "tza_i_en".
End of enumeration elements list.
TZA_I_EN_OVRD : Override value for TZA_I_EN
bits : 5 - 5 (1 bit)
access : read-write
TZA_Q_EN_OVRD_EN : Override control for TZA_Q_EN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of TZA_Q_EN_OVRD to override the signal "tza_q_en".
End of enumeration elements list.
TZA_Q_EN_OVRD : Override value for TZA_Q_EN
bits : 7 - 7 (1 bit)
access : read-write
TZA_PDET_EN_OVRD_EN : Override control for TZA_PDET_EN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of TZA_PDET_EN_OVRD to override the signal "tza_pdet_en".
End of enumeration elements list.
TZA_PDET_EN_OVRD : Override value for TZA_PDET_EN
bits : 9 - 9 (1 bit)
access : read-write
TZA_DCOC_EN_OVRD_EN : Override control for TZA_DCOC_EN
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of TZA_DCOC_EN_OVRD to override the signal "tza_dcoc_en".
End of enumeration elements list.
TZA_DCOC_EN_OVRD : Override value for TZA_DCOC_EN
bits : 11 - 11 (1 bit)
access : read-write
PLL_DIG_EN_OVRD_EN : Override control for PLL_DIG_EN
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of PLL_DIG_EN_OVRD to override the signal "pll_dig_en".
End of enumeration elements list.
PLL_DIG_EN_OVRD : Override value for PLL_DIG_EN
bits : 13 - 13 (1 bit)
access : read-write
TX_DIG_EN_OVRD_EN : Override control for TX_DIG_EN
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of TX_DIG_EN_OVRD to override the signal "tx_dig_en".
End of enumeration elements list.
TX_DIG_EN_OVRD : Override value for TX_DIG_EN
bits : 15 - 15 (1 bit)
access : read-write
RX_DIG_EN_OVRD_EN : Override control for RX_DIG_EN
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of RX_DIG_EN_OVRD to override the signal "rx_dig_en".
End of enumeration elements list.
RX_DIG_EN_OVRD : Override value for RX_DIG_EN
bits : 17 - 17 (1 bit)
access : read-write
RX_INIT_OVRD_EN : Override control for RX_INIT
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of RX_INIT_OVRD to override the signal "rx_init".
End of enumeration elements list.
RX_INIT_OVRD : Override value for RX_INIT
bits : 19 - 19 (1 bit)
access : read-write
SIGMA_DELTA_EN_OVRD_EN : Override control for SIGMA_DELTA_EN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of SIGMA_DELTA_EN_OVRD to override the signal "sigma_delta_en".
End of enumeration elements list.
SIGMA_DELTA_EN_OVRD : Override value for SIGMA_DELTA_EN
bits : 21 - 21 (1 bit)
access : read-write
ZBDEM_RX_EN_OVRD_EN : Override control for ZBDEM_RX_EN
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of ZBDEM_RX_EN_OVRD to override the signal "zbdem_rx_en".
End of enumeration elements list.
ZBDEM_RX_EN_OVRD : Override value for ZBDEM_RX_EN
bits : 23 - 23 (1 bit)
access : read-write
DCOC_EN_OVRD_EN : Override control for DCOC_EN
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of DCOC_EN_OVRD to override the signal "dcoc_en".
End of enumeration elements list.
DCOC_EN_OVRD : Override value for DCOC_EN
bits : 25 - 25 (1 bit)
access : read-write
DCOC_INIT_OVRD_EN : Override control for DCOC_INIT
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of DCOC_INIT_OVRD to override the signal "dcoc_init".
End of enumeration elements list.
DCOC_INIT_OVRD : Override value for DCOC_INIT
bits : 27 - 27 (1 bit)
access : read-write
FREQ_TARG_LD_EN_OVRD_EN : Override control for FREQ_TARG_LD_EN
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of FREQ_TARG_LD_EN_OVRD to override the signal "freq_targ_ld_en".
End of enumeration elements list.
FREQ_TARG_LD_EN_OVRD : Override value for FREQ_TARG_LD_EN
bits : 29 - 29 (1 bit)
access : read-write
SAR_ADC_TRIG_EN_OVRD_EN : Override control for SAR_ADC_TRIG_EN
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of SAR_ADC_TRIG_EN_OVRD to override the signal "sar_adc_trig_en".
End of enumeration elements list.
SAR_ADC_TRIG_EN_OVRD : Override value for SAR_ADC_TRIG_EN
bits : 31 - 31 (1 bit)
access : read-write
TSM Override 3
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSM_SPARE0_EN_OVRD_EN : Override control for TSM_SPARE0_EN
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of TSM_SPARE0_EN_OVRD to override the signal "tsm_spare0_en".
End of enumeration elements list.
TSM_SPARE0_EN_OVRD : Override value for TSM_SPARE0_EN
bits : 1 - 1 (1 bit)
access : read-write
TSM_SPARE1_EN_OVRD_EN : Override control for TSM_SPARE1_EN
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of TSM_SPARE1_EN_OVRD to override the signal "tsm_spare1_en".
End of enumeration elements list.
TSM_SPARE1_EN_OVRD : Override value for TSM_SPARE1_EN
bits : 3 - 3 (1 bit)
access : read-write
TSM_SPARE2_EN_OVRD_EN : Override control for TSM_SPARE2_EN
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of TSM_SPARE2_EN_OVRD to override the signal "tsm_spare2_en".
End of enumeration elements list.
TSM_SPARE2_EN_OVRD : Override value for TSM_SPARE2_EN
bits : 5 - 5 (1 bit)
access : read-write
TSM_SPARE3_EN_OVRD_EN : Override control for TSM_SPARE3_EN
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of TSM_SPARE3_EN_OVRD to override the signal "tsm_spare3_en".
End of enumeration elements list.
TSM_SPARE3_EN_OVRD : Override value for TSM_SPARE3_EN
bits : 7 - 7 (1 bit)
access : read-write
TX_MODE_OVRD_EN : Override control for TX_MODE
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of TX_MODE_OVRD to override the signal "tx_mode".
End of enumeration elements list.
TX_MODE_OVRD : Override value for TX_MODE
bits : 9 - 9 (1 bit)
access : read-write
RX_MODE_OVRD_EN : Override control for RX_MODE
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of RX_MODE_OVRD to override the signal "rx_mode".
End of enumeration elements list.
RX_MODE_OVRD : Override value for RX_MODE
bits : 11 - 11 (1 bit)
access : read-write
PA Power
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA_POWER : PA Power
bits : 0 - 3 (4 bit)
access : read-write
PA Bias Table 0
address_offset : 0x2DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA_BIAS0 : PA_BIAS0
bits : 0 - 3 (4 bit)
access : read-write
PA_BIAS1 : PA_BIAS1
bits : 8 - 11 (4 bit)
access : read-write
PA_BIAS2 : PA_BIAS2
bits : 16 - 19 (4 bit)
access : read-write
PA_BIAS3 : PA_BIAS3
bits : 24 - 27 (4 bit)
access : read-write
PA Bias Table 1
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA_BIAS4 : PA_BIAS4
bits : 0 - 3 (4 bit)
access : read-write
PA_BIAS5 : PA_BIAS5
bits : 8 - 11 (4 bit)
access : read-write
PA_BIAS6 : PA_BIAS6
bits : 16 - 19 (4 bit)
access : read-write
PA_BIAS7 : PA_BIAS7
bits : 24 - 27 (4 bit)
access : read-write
Recycle Count Register
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RECYCLE_COUNT0 : TSM RX Recycle Count 0
bits : 0 - 7 (8 bit)
access : read-write
RECYCLE_COUNT1 : TSM RX Recycle Count 1
bits : 8 - 15 (8 bit)
access : read-write
TSM_TIMING00
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_REG_EN_TX_HI : Assertion time setting for PLL_REG_EN TX sequence.
bits : 0 - 7 (8 bit)
access : read-write
PLL_REG_EN_TX_LO : Deassertion time setting for PLL_REG_EN signal or group TX sequence.
bits : 8 - 15 (8 bit)
access : read-write
PLL_REG_EN_RX_HI : Assertion time setting for PLL_REG_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
PLL_REG_EN_RX_LO : Deassertion time setting for PLL_REG_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING01
address_offset : 0x2EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_VCO_REG_EN_TX_HI : Assertion time setting for PLL_VCO_REG_EN TX sequence.
bits : 0 - 7 (8 bit)
access : read-write
PLL_VCO_REG_EN_TX_LO : Deassertion time setting for PLL_VCO_REG_EN signal or group TX sequence.
bits : 8 - 15 (8 bit)
access : read-write
PLL_VCO_REG_EN_RX_HI : Assertion time setting for PLL_VCO_REG_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
PLL_VCO_REG_EN_RX_LO : Deassertion time setting for PLL_VCO_REG_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING02
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QGEN_REG_EN_TX_HI : Assertion time setting for QGEN_REG_EN TX sequence.
bits : 0 - 7 (8 bit)
access : read-write
QGEN_REG_EN_TX_LO : Deassertion time setting for QGEN_REG_EN signal or group TX sequence.
bits : 8 - 15 (8 bit)
access : read-write
QGEN_REG_EN_RX_HI : Assertion time setting for QGEN_REG_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
QGEN_REG_EN_RX_LO : Deassertion time setting for QGEN_REG_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING03
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCA_TX_REG_EN_TX_HI : Assertion time setting for TCA_TX_REG_EN TX sequence.
bits : 0 - 7 (8 bit)
access : read-write
TCA_TX_REG_EN_TX_LO : Deassertion time setting for TCA_TX_REG_EN signal or group TX sequence.
bits : 8 - 15 (8 bit)
access : read-write
TCA_TX_REG_EN_RX_HI : Assertion time setting for TCA_TX_REG_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
TCA_TX_REG_EN_RX_LO : Deassertion time setting for TCA_TX_REG_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING04
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_REG_EN_RX_HI : Assertion time setting for ADC_REG_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
ADC_REG_EN_RX_LO : Deassertion time setting for ADC_REG_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING05
address_offset : 0x2FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_REF_CLK_EN_TX_HI : Assertion time setting for PLL_REF_CLK_EN TX sequence.
bits : 0 - 7 (8 bit)
access : read-write
PLL_REF_CLK_EN_TX_LO : Deassertion time setting for PLL_REF_CLK_EN signal or group TX sequence.
bits : 8 - 15 (8 bit)
access : read-write
PLL_REF_CLK_EN_RX_HI : Assertion time setting for PLL_REF_CLK_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
PLL_REF_CLK_EN_RX_LO : Deassertion time setting for PLL_REF_CLK_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
DCOC Control 4
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIG_DCOC_INIT_I : DCOC DIG Init I
bits : 0 - 11 (12 bit)
access : read-write
DIG_DCOC_INIT_Q : DCOC DIG Init Q
bits : 16 - 27 (12 bit)
access : read-write
DCOC Calibration Result
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCOC_CAL_RES_I : DCOC Calibration Result - I Channel
bits : 0 - 11 (12 bit)
access : read-only
DCOC_CAL_RES_Q : DCOC Calibration Result - Q Channel
bits : 16 - 27 (12 bit)
access : read-only
TSM_TIMING06
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_CLK_EN_RX_HI : Assertion time setting for ADC_CLK_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
ADC_CLK_EN_RX_LO : Deassertion time setting for ADC_CLK_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING07
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_VCO_AUTOTUNE_EN_TX_HI : Assertion time setting for PLL_VCO_AUTOTUNE_EN TX sequence.
bits : 0 - 7 (8 bit)
access : read-write
PLL_VCO_AUTOTUNE_EN_TX_LO : Deassertion time setting for PLL_VCO_AUTOTUNE_EN signal or group TX sequence.
bits : 8 - 15 (8 bit)
access : read-write
PLL_VCO_AUTOTUNE_EN_RX_HI : Assertion time setting for PLL_VCO_AUTOTUNE_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
PLL_VCO_AUTOTUNE_EN_RX_LO : Deassertion time setting for PLL_VCO_AUTOTUNE_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING08
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_CYCLE_SLIP_LD_EN_TX_HI : Assertion time setting for PLL_CYCLE_SLIP_LD_EN TX sequence.
bits : 0 - 7 (8 bit)
access : read-write
PLL_CYCLE_SLIP_LD_EN_TX_LO : Deassertion time setting for PLL_CYCLE_SLIP_LD_EN signal or group TX sequence.
bits : 8 - 15 (8 bit)
access : read-write
PLL_CYCLE_SLIP_LD_EN_RX_HI : Assertion time setting for PLL_CYCLE_SLIP_LD_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
PLL_CYCLE_SLIP_LD_EN_RX_LO : Deassertion time setting for PLL_CYCLE_SLIP_LD_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING09
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_VCO_EN_TX_HI : Assertion time setting for PLL_VCO_EN TX sequence.
bits : 0 - 7 (8 bit)
access : read-write
PLL_VCO_EN_TX_LO : Deassertion time setting for PLL_VCO_EN signal or group TX sequence.
bits : 8 - 15 (8 bit)
access : read-write
PLL_VCO_EN_RX_HI : Assertion time setting for PLL_VCO_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
PLL_VCO_EN_RX_LO : Deassertion time setting for PLL_VCO_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING10
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_VCO_BUF_RX_EN_RX_HI : Assertion time setting for PLL_VCO_BUF_RX_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
PLL_VCO_BUF_RX_EN_RX_LO : Deassertion time setting for PLL_VCO_BUF_RX_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING11
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_VCO_BUF_TX_EN_TX_HI : Assertion time setting for PLL_VCO_BUF_TX_EN TX sequence.
bits : 0 - 7 (8 bit)
access : read-write
PLL_VCO_BUF_TX_EN_TX_LO : Deassertion time setting for PLL_VCO_BUF_TX_EN signal or group TX sequence.
bits : 8 - 15 (8 bit)
access : read-write
TSM_TIMING12
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_PA_BUF_EN_TX_HI : Assertion time setting for PLL_PA_BUF_EN TX sequence.
bits : 0 - 7 (8 bit)
access : read-write
PLL_PA_BUF_EN_TX_LO : Deassertion time setting for PLL_PA_BUF_EN signal or group TX sequence.
bits : 8 - 15 (8 bit)
access : read-write
TSM_TIMING13
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_LDV_EN_TX_HI : Assertion time setting for PLL_LDV_EN TX sequence.
bits : 0 - 7 (8 bit)
access : read-write
PLL_LDV_EN_TX_LO : Deassertion time setting for PLL_LDV_EN signal or group TX sequence.
bits : 8 - 15 (8 bit)
access : read-write
PLL_LDV_EN_RX_HI : Assertion time setting for PLL_LDV_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
PLL_LDV_EN_RX_LO : Deassertion time setting for PLL_LDV_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING14
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_RX_LDV_RIPPLE_MUX_EN_RX_HI : Assertion time setting for PLL_RX_LDV_RIPPLE_MUX_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
PLL_RX_LDV_RIPPLE_MUX_EN_RX_LO : Deassertion time setting for PLL_RX_LDV_RIPPLE_MUX_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING15
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_TX_LDV_RIPPLE_MUX_EN_TX_HI : Assertion time setting for PLL_TX_LDV_RIPPLE_MUX_EN TX sequence.
bits : 0 - 7 (8 bit)
access : read-write
PLL_TX_LDV_RIPPLE_MUX_EN_TX_LO : Deassertion time setting for PLL_TX_LDV_RIPPLE_MUX_EN signal or group TX sequence.
bits : 8 - 15 (8 bit)
access : read-write
TSM_TIMING16
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_FILTER_CHARGE_EN_TX_HI : Assertion time setting for PLL_FILTER_CHARGE_EN TX sequence.
bits : 0 - 7 (8 bit)
access : read-write
PLL_FILTER_CHARGE_EN_TX_LO : Deassertion time setting for PLL_FILTER_CHARGE_EN signal or group TX sequence.
bits : 8 - 15 (8 bit)
access : read-write
PLL_FILTER_CHARGE_EN_RX_HI : Assertion time setting for PLL_FILTER_CHARGE_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
PLL_FILTER_CHARGE_EN_RX_LO : Deassertion time setting for PLL_FILTER_CHARGE_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING17
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_PHDET_EN_TX_HI : Assertion time setting for PLL_PHDET_EN TX sequence.
bits : 0 - 7 (8 bit)
access : read-write
PLL_PHDET_EN_TX_LO : Deassertion time setting for PLL_PHDET_EN signal or group TX sequence.
bits : 8 - 15 (8 bit)
access : read-write
PLL_PHDET_EN_RX_HI : Assertion time setting for PLL_PHDET_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
PLL_PHDET_EN_RX_LO : Deassertion time setting for PLL_PHDET_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING18
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QGEN25_EN_RX_HI : Assertion time setting for QGEN25_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
QGEN25_EN_RX_LO : Deassertion time setting for QGEN25_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
DCOC TZA DC step
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_TZA_STEP_RCP : DCOC_TZA_STEP_RCP
bits : 0 - 12 (13 bit)
access : read-write
DCOC_TZA_STEP_GAIN : DCOC_TZA_STEP_GAIN
bits : 16 - 27 (12 bit)
access : read-write
TSM_TIMING19
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_EN_TX_HI : Assertion time setting for TX_EN TX sequence.
bits : 0 - 7 (8 bit)
access : read-write
TX_EN_TX_LO : Deassertion time setting for TX_EN signal or group TX sequence.
bits : 8 - 15 (8 bit)
access : read-write
DCOC Offset
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBF_OFFSET_I : DCOC BBF I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBF_OFFSET_Q : DCOC BBF Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING20
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_EN_RX_HI : Assertion time setting for ADC_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
ADC_EN_RX_LO : Deassertion time setting for ADC_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING21
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_I_Q_EN_RX_HI : Assertion time setting for ADC_I_Q_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
ADC_I_Q_EN_RX_LO : Deassertion time setting for ADC_I_Q_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
DCOC Calibration Gain
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBF_CAL_GAIN1 : DCOC BBF Calibration Gain 1
bits : 8 - 11 (4 bit)
access : read-write
DCOC_TZA_CAL_GAIN1 : DCOC TZA Calibration Gain 1
bits : 12 - 15 (4 bit)
access : read-write
DCOC_BBF_CAL_GAIN2 : DCOC BBF Calibration Gain 2
bits : 16 - 19 (4 bit)
access : read-write
DCOC_TZA_CAL_GAIN2 : DCOC TZA Calibration Gain 2
bits : 20 - 23 (4 bit)
access : read-write
DCOC_BBF_CAL_GAIN3 : DCOC BBF Calibration Gain 3
bits : 24 - 27 (4 bit)
access : read-write
DCOC_TZA_CAL_GAIN3 : DCOC TZA Calibration Gain 3
bits : 28 - 31 (4 bit)
access : read-write
Receive Channel Filter Coefficient
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_CH_FILT_HX : RX Channel Filter Coefficient
bits : 0 - 7 (8 bit)
access : read-write
TSM_TIMING22
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_DAC_EN_RX_HI : Assertion time setting for ADC_DAC_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
ADC_DAC_EN_RX_LO : Deassertion time setting for ADC_DAC_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING23
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_RST_EN_RX_HI : Assertion time setting for ADC_RST_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
ADC_RST_EN_RX_LO : Deassertion time setting for ADC_RST_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING24
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBF_EN_RX_HI : Assertion time setting for BBF_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
BBF_EN_RX_LO : Deassertion time setting for BBF_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING25
address_offset : 0x34C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCA_EN_RX_HI : Assertion time setting for TCA_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
TCA_EN_RX_LO : Deassertion time setting for TCA_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING26
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_DIG_EN_TX_HI : Assertion time setting for PLL_DIG_EN TX sequence.
bits : 0 - 7 (8 bit)
access : read-write
PLL_DIG_EN_TX_LO : Deassertion time setting for PLL_DIG_EN signal or group TX sequence.
bits : 8 - 15 (8 bit)
access : read-write
PLL_DIG_EN_RX_HI : Assertion time setting for PLL_DIG_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
PLL_DIG_EN_RX_LO : Deassertion time setting for PLL_DIG_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING27
address_offset : 0x354 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_DIG_EN_TX_HI : Assertion time setting for TX_DIG_EN TX sequence.
bits : 0 - 7 (8 bit)
access : read-write
TX_DIG_EN_TX_LO : Deassertion time setting for TX_DIG_EN signal or group TX sequence.
bits : 8 - 15 (8 bit)
access : read-write
TSM_TIMING28
address_offset : 0x358 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_DIG_EN_RX_HI : Assertion time setting for RX_DIG_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
RX_DIG_EN_RX_LO : Deassertion time setting for RX_DIG_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING29
address_offset : 0x35C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_INIT_RX_HI : Assertion time setting for RX_INIT signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
RX_INIT_RX_LO : Deassertion time setting for RX_INIT signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING30
address_offset : 0x360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGMA_DELTA_EN_TX_HI : Assertion time setting for SIGMA_DELTA_EN TX sequence.
bits : 0 - 7 (8 bit)
access : read-write
SIGMA_DELTA_EN_TX_LO : Deassertion time setting for SIGMA_DELTA_EN signal or group TX sequence.
bits : 8 - 15 (8 bit)
access : read-write
SIGMA_DELTA_EN_RX_HI : Assertion time setting for SIGMA_DELTA_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
SIGMA_DELTA_EN_RX_LO : Deassertion time setting for SIGMA_DELTA_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING31
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZBDEM_RX_EN_RX_HI : Assertion time setting for ZBDEM_RX_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
ZBDEM_RX_EN_RX_LO : Deassertion time setting for ZBDEM_RX_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING32
address_offset : 0x368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_EN_RX_HI : Assertion time setting for DCOC_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
DCOC_EN_RX_LO : Deassertion time setting for DCOC_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING33
address_offset : 0x36C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_INIT_RX_HI : Assertion time setting for DCOC_INIT signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
DCOC_INIT_RX_LO : Deassertion time setting for DCOC_INIT signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING34
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQ_TARG_LD_EN_TX_HI : Assertion time setting for FREQ_TARG_LD_EN TX sequence.
bits : 0 - 7 (8 bit)
access : read-write
FREQ_TARG_LD_EN_TX_LO : Deassertion time setting for FREQ_TARG_LD_EN signal or group TX sequence.
bits : 8 - 15 (8 bit)
access : read-write
FREQ_TARG_LD_EN_RX_HI : Assertion time setting for FREQ_TARG_LD_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
FREQ_TARG_LD_EN_RX_LO : Deassertion time setting for FREQ_TARG_LD_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING35
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR_ADC_TRIG_EN_TX_HI : Assertion time setting for SAR_ADC_TRIG_EN TX sequence.
bits : 0 - 7 (8 bit)
access : read-write
SAR_ADC_TRIG_EN_TX_LO : Deassertion time setting for SAR_ADC_TRIG_EN signal or group TX sequence.
bits : 8 - 15 (8 bit)
access : read-write
SAR_ADC_TRIG_EN_RX_HI : Assertion time setting for SAR_ADC_TRIG_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
SAR_ADC_TRIG_EN_RX_LO : Deassertion time setting for SAR_ADC_TRIG_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING36
address_offset : 0x378 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSM_SPARE0_EN_TX_HI : Assertion time setting for TSM_SPARE0_EN TX sequence.
bits : 0 - 7 (8 bit)
access : read-write
TSM_SPARE0_EN_TX_LO : Deassertion time setting for TSM_SPARE0_EN signal or group TX sequence.
bits : 8 - 15 (8 bit)
access : read-write
TSM_SPARE0_EN_RX_HI : Assertion time setting for TSM_SPARE0_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
TSM_SPARE0_EN_RX_LO : Deassertion time setting for TSM_SPARE0_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING37
address_offset : 0x37C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSM_SPARE1_EN_TX_HI : Assertion time setting for TSM_SPARE1_EN TX sequence.
bits : 0 - 7 (8 bit)
access : read-write
TSM_SPARE1_EN_TX_LO : Deassertion time setting for TSM_SPARE1_EN signal or group TX sequence.
bits : 8 - 15 (8 bit)
access : read-write
TSM_SPARE1_EN_RX_HI : Assertion time setting for TSM_SPARE1_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
TSM_SPARE1_EN_RX_LO : Deassertion time setting for TSM_SPARE1_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
DCOC Status
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BBF_DCOC_I : DCOC BBF DAC I
bits : 0 - 5 (6 bit)
access : read-only
BBF_DCOC_Q : DCOC BBF DAC Q
bits : 8 - 13 (6 bit)
access : read-only
TZA_DCOC_I : DCOC TZA DAC I
bits : 16 - 23 (8 bit)
access : read-only
TZA_DCOC_Q : DCOC TZA DAC Q
bits : 24 - 31 (8 bit)
access : read-only
TSM_TIMING38
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSM_SPARE2_EN_TX_HI : Assertion time setting for TSM_SPARE2_EN TX sequence.
bits : 0 - 7 (8 bit)
access : read-write
TSM_SPARE2_EN_TX_LO : Deassertion time setting for TSM_SPARE2_EN signal or group TX sequence.
bits : 8 - 15 (8 bit)
access : read-write
TSM_SPARE2_EN_RX_HI : Assertion time setting for TSM_SPARE2_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
TSM_SPARE2_EN_RX_LO : Deassertion time setting for TSM_SPARE2_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING39
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSM_SPARE3_EN_TX_HI : Assertion time setting for TSM_SPARE3_EN TX sequence.
bits : 0 - 7 (8 bit)
access : read-write
TSM_SPARE3_EN_TX_LO : Deassertion time setting for TSM_SPARE3_EN signal or group TX sequence.
bits : 8 - 15 (8 bit)
access : read-write
TSM_SPARE3_EN_RX_HI : Assertion time setting for TSM_SPARE3_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
TSM_SPARE3_EN_RX_LO : Deassertion time setting for TSM_SPARE3_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING40
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO0_TRIG_EN_TX_HI : Assertion time setting for GPIO0_TRIG_EN TX sequence.
bits : 0 - 7 (8 bit)
access : read-write
GPIO0_TRIG_EN_TX_LO : Deassertion time setting for GPIO0_TRIG_EN signal or group TX sequence.
bits : 8 - 15 (8 bit)
access : read-write
GPIO0_TRIG_EN_RX_HI : Assertion time setting for GPIO0_TRIG_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
GPIO0_TRIG_EN_RX_LO : Deassertion time setting for GPIO0_TRIG_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING41
address_offset : 0x38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO1_TRIG_EN_TX_HI : Assertion time setting for GPIO1_TRIG_EN TX sequence.
bits : 0 - 7 (8 bit)
access : read-write
GPIO1_TRIG_EN_TX_LO : Deassertion time setting for GPIO1_TRIG_EN signal or group TX sequence.
bits : 8 - 15 (8 bit)
access : read-write
GPIO1_TRIG_EN_RX_HI : Assertion time setting for GPIO1_TRIG_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
GPIO1_TRIG_EN_RX_LO : Deassertion time setting for GPIO1_TRIG_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING42
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO2_TRIG_EN_TX_HI : Assertion time setting for GPIO2_TRIG_EN TX sequence.
bits : 0 - 7 (8 bit)
access : read-write
GPIO2_TRIG_EN_TX_LO : Deassertion time setting for GPIO2_TRIG_EN signal or group TX sequence.
bits : 8 - 15 (8 bit)
access : read-write
GPIO2_TRIG_EN_RX_HI : Assertion time setting for GPIO2_TRIG_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
GPIO2_TRIG_EN_RX_LO : Deassertion time setting for GPIO2_TRIG_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
TSM_TIMING43
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO3_TRIG_EN_TX_HI : Assertion time setting for GPIO3_TRIG_EN TX sequence.
bits : 0 - 7 (8 bit)
access : read-write
GPIO3_TRIG_EN_TX_LO : Deassertion time setting for GPIO3_TRIG_EN signal or group TX sequence.
bits : 8 - 15 (8 bit)
access : read-write
GPIO3_TRIG_EN_RX_HI : Assertion time setting for GPIO3_TRIG_EN signal or group RX sequence.
bits : 16 - 23 (8 bit)
access : read-write
GPIO3_TRIG_EN_RX_LO : Deassertion time setting for GPIO3_TRIG_EN signal or group RX sequence.
bits : 24 - 31 (8 bit)
access : read-write
DCOC DC Estimate
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DC_EST_I : DCOC DC Estimate I
bits : 0 - 11 (12 bit)
access : read-only
DC_EST_Q : DCOC DC Estimate Q
bits : 16 - 27 (12 bit)
access : read-only
CORR_CTRL
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CORR_VT : CORR_VT
bits : 0 - 7 (8 bit)
access : read-write
CORR_NVAL : CORR_NVAL
bits : 8 - 10 (3 bit)
access : read-write
MAX_CORR_EN : MAX_CORR_EN
bits : 11 - 11 (1 bit)
access : read-write
RX_MAX_CORR : RX_MAX_CORR
bits : 16 - 23 (8 bit)
access : read-only
RX_MAX_PREAMBLE : RX_MAX_PREAMBLE
bits : 24 - 31 (8 bit)
access : read-only
PN_TYPE
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PN_TYPE : PN_TYPE
bits : 0 - 0 (1 bit)
access : read-write
TX_INV : TX_INV
bits : 1 - 1 (1 bit)
access : read-write
PN_CODE
address_offset : 0x3C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PN_LSB : PN_LSB
bits : 0 - 15 (16 bit)
access : read-write
PN_MSB : PN_MSB
bits : 16 - 31 (16 bit)
access : read-write
Sync Control
address_offset : 0x3CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNC_PER : Symbol Sync Tracking Period
bits : 0 - 2 (3 bit)
access : read-write
TRACK_ENABLE : TRACK_ENABLE
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
symbol timing synchronization tracking disabled in Rx frontend
#1 : 1
symbol timing synchronization tracking enabled in Rx frontend (default)
End of enumeration elements list.
SNF_THR
address_offset : 0x3D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SNF_THR : SNIFF Mode Threshold
bits : 0 - 7 (8 bit)
access : read-write
FAD_THR
address_offset : 0x3D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FAD_THR : FAD_THR
bits : 0 - 7 (8 bit)
access : read-write
ZBDEM_AFC
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AFC_EN : AFC_EN
bits : 0 - 0 (1 bit)
access : read-write
DCD_EN : DCD Mode Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
NCD Mode (default)
#1 : 1
DCD Mode
End of enumeration elements list.
AFC_OUT : AFC_OUT
bits : 8 - 12 (5 bit)
access : read-only
LPPS Control Register
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPPS_ENABLE : LPPS Mode Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
LPPS mode disabled
#1 : 1
LPPS mode enabled
End of enumeration elements list.
LPPS_QGEN25_ALLOW : LPPS_QGEN25_ALLOW
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disallow TSM output qgen25_en to be duty-cycled during LPPS
#1 : 1
Allow TSM output qgen25_en to be duty-cycled during LPPS
End of enumeration elements list.
LPPS_ADC_ALLOW : LPPS_ADC_ALLOW
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disallow ADC-related TSM outputs {adc_en, adc_bias_en} to be duty-cycled during LPPS.
#1 : 1
Allow ADC-related TSM outputs {adc_en, adc_bias_en} to be duty-cycled during LPPS.
End of enumeration elements list.
LPPS_ADC_CLK_ALLOW : LPPS_ADC_CLK_ALLOW
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disallow ADC-related TSM outputs {xtal_adc_ref_clk_en, adc_clk_en} to be duty-cycled during LPPS.
#1 : 1
Allow ADC_CLK-related TSM outputs {xtal_adc_ref_clk_en, adc_clk_en} to be duty-cycled during LPPS.
End of enumeration elements list.
LPPS_ADC_I_Q_ALLOW : LPPS_ADC_I_Q_ALLOW
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disallow ADC_I/Q-related TSM outputs {adc_I_adc_en, adc_Q_adc_en} to be duty-cycled during LPPS.
#1 : 1
Allow ADC_I/Q-related TSM outputs {adc_I_adc_en, adc_Q_adc_en} to be duty-cycled during LPPS.
End of enumeration elements list.
LPPS_ADC_DAC_ALLOW : LPPS_ADC_DAC_ALLOW
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disallow ADC_DAC-related TSM outputs {adc_dac1_en, adc_dac2_en} to be duty-cycled during LPPS.
#1 : 1
Allow ADC_DAC-related TSM outputs {adc_dac1_en, adc_dac2_en} to be duty-cycled during LPPS.
End of enumeration elements list.
LPPS_BBF_ALLOW : LPPS_BBF_ALLOW
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disallow BBF-related TSM outputs {bbf_i_en, bbf_q_en, bbf_pdet_en, bbf_dcoc_en} to be duty-cycled during LPPS.
#1 : 1
Allow BBF-related TSM outputs {bbf_i_en, bbf_q_en, bbf_pdet_en, bbf_dcoc_en} to be duty-cycled during LPPS.
End of enumeration elements list.
LPPS_TCA_ALLOW : LPPS_TCA_ALLOW
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disallow TCA-related TSM outputs {tca_en, tza_i_en, tza_q_en, tza_pdet_en, tza_dcoc_en} to be duty-cycled during LPPS.
#1 : 1
Allow TCA-related TSM outputs {tca_en, tza_i_en, tza_q_en, tza_pdet_en, tza_dcoc_en} to be duty-cycled during LPPS.
End of enumeration elements list.
DCOC Offset
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBF_OFFSET_I : DCOC BBF I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBF_OFFSET_Q : DCOC BBF Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
AGC Control 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOW_AGC_EN : Slow AGC Enable
bits : 0 - 0 (1 bit)
access : read-write
SLOW_AGC_SRC : Slow AGC Source Selection
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
#0 : 0
BTLE Preamble Detect
#1 : 1
Zigbee Preamble Detect
#10 : 10
Fast AGC expire timer
End of enumeration elements list.
AGC_FREEZE_EN : AGC Freeze Enable
bits : 3 - 3 (1 bit)
access : read-write
FREEZE_AGC_SRC : Freeze AGC Source Selection
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#0 : 0
BTLE Preamble Detect
#1 : 1
Zigbee Preamble Detect
#10 : 10
BTLE access match (orf_access_match freeze)
#11 : 11
Zigbee LQI done (1=freeze, 0=run AGC)
End of enumeration elements list.
AGC_UP_EN : AGC Up Enable
bits : 6 - 6 (1 bit)
access : read-write
AGC_UP_SRC : AGC Up Source
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDET LO
#1 : 1
RSSI
End of enumeration elements list.
AGC_DOWN_BBF_STEP_SZ : AGC_DOWN_BBF_STEP_SZ
bits : 8 - 11 (4 bit)
access : read-write
AGC_DOWN_TZA_STEP_SZ : AGC_DOWN_TZA_STEP_SZ
bits : 12 - 15 (4 bit)
access : read-write
AGC_UP_RSSI_THRESH : AGC UP RSSI Threshold
bits : 16 - 23 (8 bit)
access : read-write
AGC_DOWN_RSSI_THRESH : AGC DOWN RSSI Threshold
bits : 24 - 31 (8 bit)
access : read-write
DCOC Calibration Reciprocals
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_TMP_CALC_RECIP : DCOC Calculation Reciprocal
bits : 0 - 9 (10 bit)
access : read-write
ALPHA_CALC_RECIP : Alpha Calculation Reciprocal
bits : 10 - 20 (11 bit)
access : read-write
ADC Control
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_32MHZ_SEL : ADC 32MHZ Clock Select
bits : 0 - 0 (1 bit)
access : read-write
ADC_2X_CLK_SEL : ADC_2X_CLK_SEL
bits : 2 - 2 (1 bit)
access : read-write
ADC_DITHER_ON : ADC Dither On
bits : 9 - 9 (1 bit)
access : read-write
ADC_TEST_ON : ADC Test On
bits : 10 - 10 (1 bit)
access : read-write
ADC_COMP_ON : ADC Comparator Enable
bits : 16 - 31 (16 bit)
access : read-write
ADC Tuning
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_R1_TUNE : ADC_R1_TUNE
bits : 0 - 2 (3 bit)
access : read-write
ADC_R2_TUNE : ADC_R2_TUNE
bits : 4 - 6 (3 bit)
access : read-write
ADC_C1_TUNE : ADC_C1_TUNE
bits : 16 - 19 (4 bit)
access : read-write
ADC_C2_TUNE : ADC_C2_TUNE
bits : 20 - 23 (4 bit)
access : read-write
ADC Adjustment
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_IB_OPAMP1_ADJ : ADC_IB_OPAMP1_ADJ
bits : 0 - 2 (3 bit)
access : read-write
ADC_IB_OPAMP2_ADJ : ADC_IB_OPAMP2_ADJ
bits : 4 - 6 (3 bit)
access : read-write
ADC_IB_DAC1_ADJ : ADC_IB_DAC1_ADJ
bits : 12 - 14 (3 bit)
access : read-write
ADC_IB_DAC2_ADJ : ADC_IB_DAC2_ADJ
bits : 16 - 18 (3 bit)
access : read-write
ADC_IB_FLSH_ADJ : ADC_IB_FLSH_ADJ
bits : 24 - 26 (3 bit)
access : read-write
ADC_FLSH_RES_ADJ : ADC_FLSH_RES_ADJ
bits : 28 - 30 (3 bit)
access : read-write
ADC Regulators
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_ANA_REG_SUPPLY : ADC_ANA_REG_SUPPLY
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0 : 0
1.2V
#1 : 1
1.05V
#10 : 10
1.275V
#11 : 11
1.3V
#0100 : 100
1.125V
#0101 : 101
1.15V
#0110 : 110
1.175V
#0111 : 111
1.2V
#1000 : 1000
1.225V
#1001 : 1001
1.25V
#1100 : 1100
1.325V
#1101 : 1101
1.35V
#1110 : 1110
1.375V
#1111 : 1111
1.4V
End of enumeration elements list.
ADC_REG_DIG_SUPPLY : ADC_REG_DIG_SUPPLY
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0 : 0
1.2V
#1 : 1
1.05V
#10 : 10
1.275V
#11 : 11
1.3V
#0100 : 100
1.125V
#0101 : 101
1.15V
#0110 : 110
1.175V
#0111 : 111
1.2V
#1000 : 1000
1.225V
#1001 : 1001
1.25V
#1100 : 1100
1.325V
#1101 : 1101
1.35V
#1110 : 1110
1.375V
#1111 : 1111
1.4V
End of enumeration elements list.
ADC_ANA_REG_BYPASS_ON : ADC_ANA_REG_BYPASS_ON
bits : 8 - 8 (1 bit)
access : read-write
ADC_DIG_REG_BYPASS_ON : ADC_DIG_REG_BYPASS_ON
bits : 9 - 9 (1 bit)
access : read-write
ADC_VCMREF_BYPASS_ON : ADC_VCMREF_BYPASS_ON
bits : 15 - 15 (1 bit)
access : read-write
ADC_INTERNAL_IREF_BYPASS_ON : ADC_INTERNAL_IREF_BYPASS_ON
bits : 17 - 17 (1 bit)
access : read-write
ADC Regulator Trims
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_IREF_OPAMPS_RES_TRIM : ADC_IREF_OPAMPS_RES_TRIM
bits : 0 - 2 (3 bit)
access : read-write
ADC_IREF_FLSH_RES_TRIM : ADC_IREF_FLSH_RES_TRIM
bits : 4 - 6 (3 bit)
access : read-write
ADC_VCM_TRIM : ADC_VCM_TRIM
bits : 8 - 10 (3 bit)
access : read-write
ADC Test Control
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_ATST_SEL : ADC Analog Test Selection
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
#0 : 0
Inject 5uA refrence current on ATST0 ,Inject 0.6V reference voltage on ATST1
#1 : 1
Monitor Flash refrence currents on ATST3
#00010 : 10
Monitor DAC refrence current on ATST0,Monitor mirrored reference current at ATST1,Monitor operational amplifiers reference current at ATST2, Monitor buffered 0.6V reference voltage used for opamp1 common mode at ATST3
#00011 : 11
Monitored buffered 0.6V reference voltrage used for opamp2 common mode at ATST0 monitor buffered 0.6V reference voltage used for opam3 comon mode at ATST2. However opamp3 does not exisit in this silicon but there is still a buffered reference available.
End of enumeration elements list.
ADC_DIG_REG_ATST_SEL : ADC_DIG_REG_ATST_SEL
bits : 8 - 9 (2 bit)
access : read-write
ADC_ANA_REG_ATST_SEL : ADC_ANA_REG_ATST_SEL
bits : 12 - 13 (2 bit)
access : read-write
DCOC_ALPHA_RADIUS_GS_IDX : Alpha-R Scaling
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
1
#001 : 001
1/2
#010 : 010
1/4
#011 : 011
1/8
#100 : 100
1/16
#101 : 101
1/32
#110 : 110
1/64
End of enumeration elements list.
ADC_SPARE : ADC_SPARE
bits : 24 - 27 (4 bit)
access : read-write
ADC_SPARE3 : ADC_SPARE3
bits : 27 - 27 (1 bit)
access : read-write
Baseband Filter Control
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBF_CAP_TUNE : BBF_CAP_TUNE
bits : 0 - 3 (4 bit)
access : read-write
BBF_RES_TUNE2 : BBF_RES_TUNE2
bits : 4 - 7 (4 bit)
access : read-write
BBF_CUR_CNTL : BBF_CUR_CNTL
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low current setting.
#1 : 1
High current setting.
End of enumeration elements list.
BBF_DCOC_ON : BBF_DCOC_ON
bits : 9 - 9 (1 bit)
access : read-write
BBF_TMUX_ON : BBF_TMUX_ON
bits : 11 - 11 (1 bit)
access : read-write
DCOC_ALPHAC_SCALE_GS_IDX : DCOC Alpha-C Scaling
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 00
1/2
#01 : 01
1/4
#10 : 10
1/8
#11 : 11
1/16
End of enumeration elements list.
BBF_SPARE : BBF_SPARE
bits : 12 - 15 (4 bit)
access : read-write
BBF_SPARE_3_2 : BBF_SPARE_3_2
bits : 14 - 15 (2 bit)
access : read-write
RX Analog Control
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_ATST_SEL : RX_ATST_SEL
bits : 0 - 3 (4 bit)
access : read-write
IQMC_DC_GAIN_ADJ_EN : IQMC_DC_GAIN_ADJ_EN
bits : 4 - 4 (1 bit)
access : read-write
LNM_SPARE : LNM_SPARE
bits : 4 - 7 (4 bit)
access : read-write
LNM_SPARE_3_2_1 : LNM_SPARE_3_2_1
bits : 5 - 7 (3 bit)
access : read-write
Crystal Oscillator Control Register 1
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTAL_TRIM : XTAL Trim
bits : 0 - 7 (8 bit)
access : read-write
XTAL_GM : XTAL_GM
bits : 8 - 12 (5 bit)
access : read-write
XTAL_BYPASS : XTAL Bypass
bits : 13 - 13 (1 bit)
access : read-write
XTAL_READY_COUNT_SEL : XTAL Ready Count Select
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
1024 clock cycles
#01 : 01
2048 clock cycles
#10 : 10
4096 clock cycles
#11 : 11
8192 clock cycles
End of enumeration elements list.
XTAL_COMP_BIAS_LO : XTAL_COMP_BIAS (Low)
bits : 16 - 20 (5 bit)
access : read-write
XTAL_ALC_START_512U : XTAL_ALC_START_512U
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Start XTAL ALC at 256usec
#1 : 1
Start XTAL ALC at 512usec
End of enumeration elements list.
XTAL_ALC_ON : XTAL_ALC_ON
bits : 23 - 23 (1 bit)
access : read-write
XTAL_COMP_BIAS_HI : XTAL_COMP_BIAS (High)
bits : 24 - 28 (5 bit)
access : read-write
XTAL_READY : XTAL Ready Indicator
bits : 31 - 31 (1 bit)
access : read-only
Crystal Oscillator Control Register 2
address_offset : 0x438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTAL_REG_SUPPLY : XTAL_REG_SUPPLY
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0 : 0
1.2V
#1 : 1
1.05V
#10 : 10
1.275V
#11 : 11
1.3V
#0100 : 100
1.125V
#0101 : 101
1.15V
#0110 : 110
1.175V
#0111 : 111
1.2V
#1000 : 1000
1.225V
#1001 : 1001
1.25V
#1100 : 1100
1.325V
#1101 : 1101
1.35V
#1110 : 1110
1.375V
#1111 : 1111
1.4V
End of enumeration elements list.
XTAL_REG_BYPASS_ON : XTAL_REG_BYPASS_ON
bits : 4 - 4 (1 bit)
access : read-write
XTAL_REG_ON_OVRD_ON : XTAL_REG_ON_OVRD_ON
bits : 8 - 8 (1 bit)
access : read-write
XTAL_REG_ON_OVRD : XTAL_REG_ON_OVRD
bits : 9 - 9 (1 bit)
access : read-write
XTAL_ON_OVRD_ON : XTAL_ON_OVRD_ON
bits : 10 - 10 (1 bit)
access : read-write
XTAL_ON_OVRD : XTAL_ON_OVRD
bits : 11 - 11 (1 bit)
access : read-write
XTAL_DIG_CLK_OUT_ON : XTAL_DIG_CLK_OUT_ON
bits : 12 - 12 (1 bit)
access : read-write
XTAL_REG_ATST_SEL : XTAL_REG_ATST_SEL
bits : 16 - 17 (2 bit)
access : read-write
XTAL_ATST_SEL : XTAL_ATST_SEL
bits : 24 - 25 (2 bit)
access : read-write
XTAL_ATST_ON : XTAL_ATST_ON
bits : 26 - 26 (1 bit)
access : read-write
XTAL_SPARE : XTAL_SPARE
bits : 28 - 31 (4 bit)
access : read-write
Bandgap Control
address_offset : 0x43C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BGAP_CURRENT_TRIM : BGAP_CURRENT_TRIM
bits : 0 - 3 (4 bit)
access : read-write
BGAP_VOLTAGE_TRIM : BGAP_VOLTAGE_TRIM
bits : 4 - 7 (4 bit)
access : read-write
BGAP_ATST_SEL : BGAP_ATST_SEL
bits : 8 - 11 (4 bit)
access : read-write
BGAP_ATST_ON : BGAP_ATST_ON
bits : 12 - 12 (1 bit)
access : read-write
PLL Control Register
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_VCO_BIAS : PLL VCO Bias Control
bits : 0 - 2 (3 bit)
access : read-write
PLL_LFILT_CNTL : PLL Loop Filter Control
bits : 4 - 6 (3 bit)
access : read-write
PLL_REG_SUPPLY : PLL_REG_SUPPLY
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0 : 0
1.2V
#1 : 1
1.05V
#10 : 10
1.275V
#11 : 11
1.3V
#0100 : 100
1.125V
#0101 : 101
1.15V
#0110 : 110
1.175V
#0111 : 111
1.2V
#1000 : 1000
1.225V
#1001 : 1001
1.25V
#1100 : 1100
1.325V
#1101 : 1101
1.35V
#1110 : 1110
1.375V
#1111 : 1111
1.4V
End of enumeration elements list.
PLL_REG_BYPASS_ON : PLL_REG_BYPASS_ON
bits : 16 - 16 (1 bit)
access : read-write
PLL_VCO_LDO_BYPASS : PLL_VCO_LDO_BYPASS
bits : 17 - 17 (1 bit)
access : read-write
HPM_BIAS : HPM Array Bias
bits : 24 - 30 (7 bit)
access : read-write
PLL_VCO_SPARE : PLL_VCO_SPARE
bits : 24 - 31 (8 bit)
access : read-write
PLL_VCO_SPARE7 : PLL_VCO_SPARE7
bits : 31 - 31 (1 bit)
access : read-write
PLL Control Register 2
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_VCO_KV : PLL_VCO_KV
bits : 0 - 2 (3 bit)
access : read-write
PLL_KMOD_SLOPE : PLL_KMOD_SLOPE
bits : 3 - 3 (1 bit)
access : read-write
PLL_VCO_REG_SUPPLY : PLL_VCO_REG_SUPPLY
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#0 : 0
1.15V
#1 : 1
1.2V
#10 : 10
1.25V
#11 : 11
1.3V
End of enumeration elements list.
PLL_TMUX_ON : PLL_TMUX_ON
bits : 8 - 8 (1 bit)
access : read-write
DCOC TZA DC step
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_TZA_STEP_RCP : DCOC_TZA_STEP_RCP
bits : 0 - 12 (13 bit)
access : read-write
DCOC_TZA_STEP_GAIN : DCOC_TZA_STEP_GAIN
bits : 16 - 27 (12 bit)
access : read-write
PLL Test Control
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_TMUX_SEL : PLL_TMUX_SEL
bits : 0 - 1 (2 bit)
access : read-write
PLL_VCO_REG_ATST : PLL_VCO_REG_ATST
bits : 4 - 5 (2 bit)
access : read-write
PLL_REG_ATST_SEL : PLL_REG_ATST_SEL
bits : 8 - 9 (2 bit)
access : read-write
PLL_VCO_TEST_CLK_MODE : PLL_VCO_TEST_CLK_MODE
bits : 12 - 12 (1 bit)
access : read-write
PLL_FORCE_VTUNE_EXTERNALLY : PLL_FORCE_VTUNE_EXTERNALLY
bits : 13 - 13 (1 bit)
access : read-write
PLL_RIPPLE_COUNTER_TEST_MODE : PLL_RIPPLE_COUNTER_TEST_MODE
bits : 14 - 14 (1 bit)
access : read-write
QGEN Control
address_offset : 0x458 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QGEN_REG_SUPPLY : QGEN_REG_SUPPLY
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0 : 0
1.2V
#1 : 1
1.05V
#10 : 10
1.275V
#11 : 11
1.3V
#0100 : 100
1.125V
#0101 : 101
1.15V
#0110 : 110
1.175V
#0111 : 111
1.2V
#1000 : 1000
1.225V
#1001 : 1001
1.25V
#1100 : 1100
1.325V
#1101 : 1101
1.35V
#1110 : 1110
1.375V
#1111 : 1111
1.4V
End of enumeration elements list.
QGEN_REG_ATST_SEL : QGEN_REG_ATST_SEL
bits : 4 - 7 (4 bit)
access : read-write
QGEN_REG_BYPASS_ON : QGEN_REG_BYPASS_ON
bits : 8 - 8 (1 bit)
access : read-write
TCA Control
address_offset : 0x464 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCA_BIAS_CURR : TCA_BIAS_CURR
bits : 0 - 1 (2 bit)
access : read-write
TCA_LOW_PWR_ON : TCA_LOW_PWR_ON
bits : 2 - 2 (1 bit)
access : read-write
TCA_TX_REG_BYPASS_ON : TCA_TX_REG_BYPASS_ON
bits : 3 - 3 (1 bit)
access : read-write
TCA_TX_REG_SUPPLY : TCA_TX_REG_SUPPLY
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0 : 0
1.2V
#1 : 1
1.05V
#10 : 10
1.275V
#11 : 11
1.3V
#0100 : 100
1.125V
#0101 : 101
1.15V
#0110 : 110
1.175V
#0111 : 111
1.2V
#1000 : 1000
1.225V
#1001 : 1001
1.25V
#1100 : 1100
1.325V
#1101 : 1101
1.35V
#1110 : 1110
1.375V
#1111 : 1111
1.4V
End of enumeration elements list.
TCA_TX_REG_ATST_SEL : TCA_TX_REG_ATST_SEL
bits : 8 - 9 (2 bit)
access : read-write
TZA Control
address_offset : 0x468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TZA_CAP_TUNE : TZA_CAP_TUNE
bits : 0 - 3 (4 bit)
access : read-write
TZA_GAIN : TZA_GAIN
bits : 4 - 4 (1 bit)
access : read-write
TZA_DCOC_ON : TZA_DCOC_ON
bits : 5 - 5 (1 bit)
access : read-write
TZA_CUR_CNTL : TZA_CUR_CNTL
bits : 6 - 7 (2 bit)
access : read-write
TZA_SPARE : TZA_SPARE
bits : 20 - 23 (4 bit)
access : read-write
TX Analog Control
address_offset : 0x474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HPM_CAL_ADJUST : HPM Cal Count Adjust
bits : 0 - 3 (4 bit)
access : read-write
TX_SPARE : TX_SPARE
bits : 0 - 3 (4 bit)
access : read-write
Analog Spare
address_offset : 0x47C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IQMC_DC_GAIN_ADJ : IQ Mismatch Correction DC Gain Coeff
bits : 0 - 10 (11 bit)
access : read-write
ANALOG_SPARE : ANALOG_SPARE
bits : 0 - 15 (16 bit)
access : read-write
DCOC_TRK_EST_GS_CNT : DCOC Tracking Estimator Gearshift Count
bits : 11 - 13 (3 bit)
access : read-write
Enumeration:
#000 : 0
Only use {dcoc_alpha_radius_idx, dcoc_alphac_scaling_idx, dcoc_sign_scaling_idx}
#001 : 1
Switch from {dcoc_alpha_radius_idx, dcoc_alphac_scaling_idx, dcoc_sign_scaling_idx} to {dcoc_alpha_radius_gs_idx, dcoc_alphac_scaling_gs_idx, dcoc_sign_scaling_idx} after the 1 update correction.
#010 : 10
Switch after 2 update corrections.
#011 : 11
Switch after 3 update corrections.
#100 : 100
Switch after 4 update corrections.
#101 : 101
Switch after 5 update corrections.
#110 : 110
Switch after 6 update corrections.
#111 : 111
Switch after 7 update corrections.
End of enumeration elements list.
HPM_LSB_INVERT : High port LSB array inversion control
bits : 14 - 15 (2 bit)
access : read-write
ANA_DTEST : ANA_DTEST
bits : 16 - 21 (6 bit)
access : read-only
DCOC Calibration Result
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCOC_CAL_RES_I : DCOC Calibration Result - I Channel
bits : 0 - 11 (12 bit)
access : read-only
DCOC_CAL_RES_Q : DCOC Calibration Result - Q Channel
bits : 16 - 27 (12 bit)
access : read-only
DCOC Offset
address_offset : 0x49C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBF_OFFSET_I : DCOC BBF I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBF_OFFSET_Q : DCOC BBF Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
IQMC Control
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IQMC_CAL_EN : IQ Mismatch Cal Enable
bits : 0 - 0 (1 bit)
access : read-write
IQMC_NUM_ITER : IQ Mismatch Cal Num Iter
bits : 8 - 15 (8 bit)
access : read-write
Receive Channel Filter Coefficient
address_offset : 0x4E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_CH_FILT_HX : RX Channel Filter Coefficient
bits : 0 - 7 (8 bit)
access : read-write
IQMC Calibration
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IQMC_GAIN_ADJ : IQ Mismatch Correction Gain Coeff
bits : 0 - 10 (11 bit)
access : read-write
IQMC_PHASE_ADJ : IQ Mismatch Correction Phase Coeff
bits : 16 - 27 (12 bit)
access : read-write
TCA AGC Step Values 3..0
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCA_AGC_VAL_0 : TCA_AGC step 0
bits : 0 - 7 (8 bit)
access : read-write
TCA_AGC_VAL_1 : TCA_AGC step 1
bits : 8 - 15 (8 bit)
access : read-write
TCA_AGC_VAL_2 : TCA_AGC step 2
bits : 16 - 23 (8 bit)
access : read-write
TCA_AGC_VAL_3 : TCA_AGC step 3
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0x554 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBF_OFFSET_I : DCOC BBF I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBF_OFFSET_Q : DCOC BBF Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC TZA DC step
address_offset : 0x568 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_TZA_STEP_RCP : DCOC_TZA_STEP_RCP
bits : 0 - 12 (13 bit)
access : read-write
DCOC_TZA_STEP_GAIN : DCOC_TZA_STEP_GAIN
bits : 16 - 27 (12 bit)
access : read-write
TCA AGC Step Values 7..4
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCA_AGC_VAL_4 : TCA_AGC step 4
bits : 0 - 7 (8 bit)
access : read-write
TCA_AGC_VAL_5 : TCA_AGC step 5
bits : 8 - 15 (8 bit)
access : read-write
TCA_AGC_VAL_6 : TCA_AGC step 6
bits : 16 - 23 (8 bit)
access : read-write
TCA_AGC_VAL_7 : TCA_AGC step 7
bits : 24 - 31 (8 bit)
access : read-write
TCA AGC Step Values 8
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCA_AGC_VAL_8 : TCA_AGC step 8
bits : 0 - 7 (8 bit)
access : read-write
BBF Resistor Tune Values 7..0
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBF_RES_TUNE_VAL_0 : BBF Resistor Tune Step 0
bits : 0 - 3 (4 bit)
access : read-write
BBF_RES_TUNE_VAL_1 : BBF Resistor Tune Step 1
bits : 4 - 7 (4 bit)
access : read-write
BBF_RES_TUNE_VAL_2 : BBF Resistor Tune Step 2
bits : 8 - 11 (4 bit)
access : read-write
BBF_RES_TUNE_VAL_3 : BBF Resistor Tune Step 3
bits : 12 - 15 (4 bit)
access : read-write
BBF_RES_TUNE_VAL_4 : BBF Resistor Tune Step 4
bits : 16 - 19 (4 bit)
access : read-write
BBF_RES_TUNE_VAL_5 : BBF Resistor Tune Step 5
bits : 20 - 23 (4 bit)
access : read-write
BBF_RES_TUNE_VAL_6 : BBF Resistor Tune Step 6
bits : 24 - 27 (4 bit)
access : read-write
BBF_RES_TUNE_VAL_7 : BBF Resistor Tune Step 7
bits : 28 - 31 (4 bit)
access : read-write
DCOC Calibration Result
address_offset : 0x60C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCOC_CAL_RES_I : DCOC Calibration Result - I Channel
bits : 0 - 11 (12 bit)
access : read-only
DCOC_CAL_RES_Q : DCOC Calibration Result - Q Channel
bits : 16 - 27 (12 bit)
access : read-only
DCOC Offset
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBF_OFFSET_I : DCOC BBF I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBF_OFFSET_Q : DCOC BBF Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
BBF Resistor Tune Values 10..8
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBF_RES_TUNE_VAL_8 : BBF Resistor Tune Step 8
bits : 0 - 3 (4 bit)
access : read-write
BBF_RES_TUNE_VAL_9 : BBF Resistor Tune Step 9
bits : 4 - 7 (4 bit)
access : read-write
BBF_RES_TUNE_VAL_10 : BBF Resistor Tune Step 10
bits : 8 - 11 (4 bit)
access : read-write
TCA AGC Linear Gain Values 2..0
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCA_AGC_LIN_VAL_0 : LNM linear gain value for index 0, e.g. nominal value is 10^(-3/20). Stored with 2 fractional bits, e.g. round([10^(-3/20)]*2^2) = 3decimal
bits : 0 - 9 (10 bit)
access : read-write
TCA_AGC_LIN_VAL_1 : TCA AGC Linear Gain Step 1
bits : 10 - 19 (10 bit)
access : read-write
TCA_AGC_LIN_VAL_2 : TCA AGC Linear Gain Step 2
bits : 20 - 29 (10 bit)
access : read-write
DCOC TZA DC step
address_offset : 0x688 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_TZA_STEP_RCP : DCOC_TZA_STEP_RCP
bits : 0 - 12 (13 bit)
access : read-write
DCOC_TZA_STEP_GAIN : DCOC_TZA_STEP_GAIN
bits : 16 - 27 (12 bit)
access : read-write
Receive Channel Filter Coefficient
address_offset : 0x68C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_CH_FILT_HX : RX Channel Filter Coefficient
bits : 0 - 7 (8 bit)
access : read-write
TCA AGC Linear Gain Values 5..3
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCA_AGC_LIN_VAL_3 : TCA AGC Linear Gain Step 3
bits : 0 - 9 (10 bit)
access : read-write
TCA_AGC_LIN_VAL_4 : TCA AGC Linear Gain Step 4
bits : 10 - 19 (10 bit)
access : read-write
TCA_AGC_LIN_VAL_5 : TCA AGC Linear Gain Step 5
bits : 20 - 29 (10 bit)
access : read-write
DCOC Offset
address_offset : 0x6D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBF_OFFSET_I : DCOC BBF I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBF_OFFSET_Q : DCOC BBF Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
TCA AGC Linear Gain Values 8..6
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCA_AGC_LIN_VAL_6 : TCA AGC Linear Gain Step 6
bits : 0 - 9 (10 bit)
access : read-write
TCA_AGC_LIN_VAL_7 : TCA AGC Linear Gain Step 7
bits : 10 - 19 (10 bit)
access : read-write
TCA_AGC_LIN_VAL_8 : TCA AGC Linear Gain Step 8
bits : 20 - 29 (10 bit)
access : read-write
BBF Resistor Tune Values 3..0
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBF_RES_TUNE_LIN_VAL_0 : BBF Resistor Tune Linear Gain Step 0
bits : 0 - 7 (8 bit)
access : read-write
BBF_RES_TUNE_LIN_VAL_1 : BBF Resistor Tune Linear Gain Step 1
bits : 8 - 15 (8 bit)
access : read-write
BBF_RES_TUNE_LIN_VAL_2 : BBF Resistor Tune Linear Gain Step 2
bits : 16 - 23 (8 bit)
access : read-write
BBF_RES_TUNE_LIN_VAL_3 : BBF Resistor Tune Linear Gain Step 3
bits : 24 - 31 (8 bit)
access : read-write
BBF Resistor Tune Values 7..4
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBF_RES_TUNE_LIN_VAL_4 : BBF Resistor Tune Linear Gain Step 4
bits : 0 - 7 (8 bit)
access : read-write
BBF_RES_TUNE_LIN_VAL_5 : BBF Resistor Tune Linear Gain Step 5
bits : 8 - 15 (8 bit)
access : read-write
BBF_RES_TUNE_LIN_VAL_6 : BBF Resistor Tune Linear Gain Step 6
bits : 16 - 23 (8 bit)
access : read-write
BBF_RES_TUNE_LIN_VAL_7 : BBF Resistor Tune Linear Gain Step 7
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0x794 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBF_OFFSET_I : DCOC BBF I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBF_OFFSET_Q : DCOC BBF Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC TZA DC step
address_offset : 0x7AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_TZA_STEP_RCP : DCOC_TZA_STEP_RCP
bits : 0 - 12 (13 bit)
access : read-write
DCOC_TZA_STEP_GAIN : DCOC_TZA_STEP_GAIN
bits : 16 - 27 (12 bit)
access : read-write
BBF Resistor Tune Values 10..8
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBF_RES_TUNE_LIN_VAL_8 : BBF Resistor Tune Linear Gain Step 8
bits : 0 - 7 (8 bit)
access : read-write
BBF_RES_TUNE_LIN_VAL_9 : BBF Resistor Tune Linear Gain Step 9
bits : 8 - 15 (8 bit)
access : read-write
BBF_RES_TUNE_LIN_VAL_10 : BBF Resistor Tune Linear Gain Step 10
bits : 16 - 23 (8 bit)
access : read-write
AGC Control 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBF_ALT_CODE : BBF_ALT_CODE
bits : 0 - 3 (4 bit)
access : read-write
LNM_ALT_CODE : LNM_ALT_CODE
bits : 4 - 11 (8 bit)
access : read-write
LNM_USER_GAIN : LNM_USER_GAIN
bits : 12 - 15 (4 bit)
access : read-write
BBF_USER_GAIN : BBF_USER_GAIN
bits : 16 - 19 (4 bit)
access : read-write
USER_LNM_GAIN_EN : User LNM Gain Enable
bits : 20 - 20 (1 bit)
access : read-write
USER_BBF_GAIN_EN : User BBF Gain Enable
bits : 21 - 21 (1 bit)
access : read-write
PRESLOW_EN : Pre-slow Enable
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pre-slow is disabled.
#1 : 1
Pre-slow is enabled.
End of enumeration elements list.
TZA_GAIN_SETTLE_TIME : TZA_GAIN_SETTLE_TIME
bits : 24 - 31 (8 bit)
access : read-write
AGC Gain Tables Step 03..00
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBF_GAIN_00 : BBF Gain 00
bits : 0 - 3 (4 bit)
access : read-write
LNM_GAIN_00 : LNM Gain 00
bits : 4 - 7 (4 bit)
access : read-write
BBF_GAIN_01 : BBF Gain 01
bits : 8 - 11 (4 bit)
access : read-write
LNM_GAIN_01 : LNM Gain 01
bits : 12 - 15 (4 bit)
access : read-write
BBF_GAIN_02 : BBF Gain 02
bits : 16 - 19 (4 bit)
access : read-write
LNM_GAIN_02 : LNM Gain 02
bits : 20 - 23 (4 bit)
access : read-write
BBF_GAIN_03 : BBF Gain 03
bits : 24 - 27 (4 bit)
access : read-write
LNM_GAIN_03 : LNM Gain 03
bits : 28 - 31 (4 bit)
access : read-write
Receive Channel Filter Coefficient
address_offset : 0x838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_CH_FILT_HX : RX Channel Filter Coefficient
bits : 0 - 7 (8 bit)
access : read-write
AGC Gain Tables Step 07..04
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBF_GAIN_04 : BBF Gain 04
bits : 0 - 3 (4 bit)
access : read-write
LNM_GAIN_04 : LNM Gain 04
bits : 4 - 7 (4 bit)
access : read-write
BBF_GAIN_05 : BBF Gain 05
bits : 8 - 11 (4 bit)
access : read-write
LNM_GAIN_05 : LNM Gain 05
bits : 12 - 15 (4 bit)
access : read-write
BBF_GAIN_06 : BBF Gain 06
bits : 16 - 19 (4 bit)
access : read-write
LNM_GAIN_06 : LNM Gain 06
bits : 20 - 23 (4 bit)
access : read-write
BBF_GAIN_07 : BBF Gain 07
bits : 24 - 27 (4 bit)
access : read-write
LNM_GAIN_07 : LNM Gain 07
bits : 28 - 31 (4 bit)
access : read-write
DCOC Offset
address_offset : 0x85C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBF_OFFSET_I : DCOC BBF I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBF_OFFSET_Q : DCOC BBF Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
AGC Gain Tables Step 11..08
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBF_GAIN_08 : BBF Gain 08
bits : 0 - 3 (4 bit)
access : read-write
LNM_GAIN_08 : LNM Gain 08
bits : 4 - 7 (4 bit)
access : read-write
BBF_GAIN_09 : BBF Gain 09
bits : 8 - 11 (4 bit)
access : read-write
LNM_GAIN_09 : LNM Gain 09
bits : 12 - 15 (4 bit)
access : read-write
BBF_GAIN_10 : BBF Gain 10
bits : 16 - 19 (4 bit)
access : read-write
LNM_GAIN_10 : LNM Gain 10
bits : 20 - 23 (4 bit)
access : read-write
BBF_GAIN_11 : BBF Gain 11
bits : 24 - 27 (4 bit)
access : read-write
LNM_GAIN_11 : LNM Gain 11
bits : 28 - 31 (4 bit)
access : read-write
AGC Gain Tables Step 15..12
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBF_GAIN_12 : BBF Gain 12
bits : 0 - 3 (4 bit)
access : read-write
LNM_GAIN_12 : LNM Gain 12
bits : 4 - 7 (4 bit)
access : read-write
BBF_GAIN_13 : BBF Gain 13
bits : 8 - 11 (4 bit)
access : read-write
LNM_GAIN_13 : LNM Gain 13
bits : 12 - 15 (4 bit)
access : read-write
BBF_GAIN_14 : BBF Gain 14
bits : 16 - 19 (4 bit)
access : read-write
LNM_GAIN_14 : LNM Gain 14
bits : 20 - 23 (4 bit)
access : read-write
BBF_GAIN_15 : BBF Gain 15
bits : 24 - 27 (4 bit)
access : read-write
LNM_GAIN_15 : LNM Gain 15
bits : 28 - 31 (4 bit)
access : read-write
DCOC TZA DC step
address_offset : 0x8D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_TZA_STEP_RCP : DCOC_TZA_STEP_RCP
bits : 0 - 12 (13 bit)
access : read-write
DCOC_TZA_STEP_GAIN : DCOC_TZA_STEP_GAIN
bits : 16 - 27 (12 bit)
access : read-write
AGC Gain Tables Step 19..16
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBF_GAIN_16 : BBF Gain 16
bits : 0 - 3 (4 bit)
access : read-write
LNM_GAIN_16 : LNM Gain 16
bits : 4 - 7 (4 bit)
access : read-write
BBF_GAIN_17 : BBF Gain 17
bits : 8 - 11 (4 bit)
access : read-write
LNM_GAIN_17 : LNM Gain 17
bits : 12 - 15 (4 bit)
access : read-write
BBF_GAIN_18 : BBF Gain 18
bits : 16 - 19 (4 bit)
access : read-write
LNM_GAIN_18 : LNM Gain 18
bits : 20 - 23 (4 bit)
access : read-write
BBF_GAIN_19 : BBF Gain 193
bits : 24 - 27 (4 bit)
access : read-write
LNM_GAIN_19 : LNM Gain 19
bits : 28 - 31 (4 bit)
access : read-write
DCOC Offset
address_offset : 0x928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBF_OFFSET_I : DCOC BBF I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBF_OFFSET_Q : DCOC BBF Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
AGC Gain Tables Step 23..20
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBF_GAIN_20 : BBF Gain 20
bits : 0 - 3 (4 bit)
access : read-write
LNM_GAIN_20 : LNM Gain 20
bits : 4 - 7 (4 bit)
access : read-write
BBF_GAIN_21 : BBF Gain 21
bits : 8 - 11 (4 bit)
access : read-write
LNM_GAIN_21 : LNM Gain 21
bits : 12 - 15 (4 bit)
access : read-write
BBF_GAIN_22 : BBF Gain 22
bits : 16 - 19 (4 bit)
access : read-write
LNM_GAIN_22 : LNM Gain 22
bits : 20 - 23 (4 bit)
access : read-write
BBF_GAIN_23 : BBF Gain 23
bits : 24 - 27 (4 bit)
access : read-write
LNM_GAIN_23 : LNM Gain 23
bits : 28 - 31 (4 bit)
access : read-write
AGC Gain Tables Step 26..24
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBF_GAIN_24 : BBF Gain 24
bits : 0 - 3 (4 bit)
access : read-write
LNM_GAIN_24 : LNM Gain 24
bits : 4 - 7 (4 bit)
access : read-write
BBF_GAIN_25 : BBF Gain 25
bits : 8 - 11 (4 bit)
access : read-write
LNM_GAIN_25 : LNM Gain 25
bits : 12 - 15 (4 bit)
access : read-write
BBF_GAIN_26 : BBF Gain 26
bits : 16 - 19 (4 bit)
access : read-write
LNM_GAIN_26 : LNM Gain 26
bits : 20 - 23 (4 bit)
access : read-write
Receive Channel Filter Coefficient
address_offset : 0x9E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_CH_FILT_HX : RX Channel Filter Coefficient
bits : 0 - 7 (8 bit)
access : read-write
DCOC Offset
address_offset : 0x9F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBF_OFFSET_I : DCOC BBF I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBF_OFFSET_Q : DCOC BBF Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC TZA DC step
address_offset : 0xA00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_TZA_STEP_RCP : DCOC_TZA_STEP_RCP
bits : 0 - 12 (13 bit)
access : read-write
DCOC_TZA_STEP_GAIN : DCOC_TZA_STEP_GAIN
bits : 16 - 27 (12 bit)
access : read-write
DCOC Offset
address_offset : 0xACC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBF_OFFSET_I : DCOC BBF I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBF_OFFSET_Q : DCOC BBF Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC TZA DC step
address_offset : 0xB30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_TZA_STEP_RCP : DCOC_TZA_STEP_RCP
bits : 0 - 12 (13 bit)
access : read-write
DCOC_TZA_STEP_GAIN : DCOC_TZA_STEP_GAIN
bits : 16 - 27 (12 bit)
access : read-write
Receive Channel Filter Coefficient
address_offset : 0xB9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_CH_FILT_HX : RX Channel Filter Coefficient
bits : 0 - 7 (8 bit)
access : read-write
DCOC Offset
address_offset : 0xBA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBF_OFFSET_I : DCOC BBF I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBF_OFFSET_Q : DCOC BBF Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
AGC Control 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBF_PDET_RST : BBF PDET Reset
bits : 0 - 0 (1 bit)
access : read-write
TZA_PDET_RST : TZA PDET Reset
bits : 1 - 1 (1 bit)
access : read-write
BBF_GAIN_SETTLE_TIME : BBF Gain Settle Time
bits : 4 - 11 (8 bit)
access : read-write
BBF_PDET_THRESH_LO : BBF PDET Threshold Low
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 000
0.6V
#001 : 001
0.675V
#010 : 010
0.75V
#011 : 011
0.825V
#100 : 100
0.9V
#101 : 101
0.975V
#110 : 110
1.05V
#111 : 111
1.125V
End of enumeration elements list.
BBF_PDET_THRESH_HI : BBF PDET Threshold High
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
#000 : 000
0.6V
#001 : 001
0.675V
#010 : 010
0.75V
#011 : 011
0.825V
#100 : 100
0.9V
#101 : 101
0.975V
#110 : 110
1.05V
#111 : 111
1.125V
End of enumeration elements list.
TZA_PDET_THRESH_LO : TZA PDET Threshold Low
bits : 18 - 20 (3 bit)
access : read-write
Enumeration:
#000 : 000
0.6V
#001 : 001
0.675V
#010 : 010
0.75V
#011 : 011
0.825V
#100 : 100
0.9V
#101 : 101
0.975V
#110 : 110
1.05V
#111 : 111
1.125V
End of enumeration elements list.
TZA_PDET_THRESH_HI : TZA PDET Threshold High
bits : 21 - 23 (3 bit)
access : read-write
Enumeration:
#000 : 000
0.6V
#001 : 001
0.675V
#010 : 010
0.75V
#011 : 011
0.825V
#100 : 100
0.9V
#101 : 101
0.975V
#110 : 110
1.05V
#111 : 111
1.125V
End of enumeration elements list.
AGC_FAST_EXPIRE : AGC Fast Expire
bits : 24 - 29 (6 bit)
access : read-write
DCOC TZA DC step
address_offset : 0xC64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_TZA_STEP_RCP : DCOC_TZA_STEP_RCP
bits : 0 - 12 (13 bit)
access : read-write
DCOC_TZA_STEP_GAIN : DCOC_TZA_STEP_GAIN
bits : 16 - 27 (12 bit)
access : read-write
DCOC Offset
address_offset : 0xC80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBF_OFFSET_I : DCOC BBF I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBF_OFFSET_Q : DCOC BBF Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
Receive Channel Filter Coefficient
address_offset : 0xD54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_CH_FILT_HX : RX Channel Filter Coefficient
bits : 0 - 7 (8 bit)
access : read-write
DCOC Offset
address_offset : 0xD60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBF_OFFSET_I : DCOC BBF I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBF_OFFSET_Q : DCOC BBF Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC TZA DC step
address_offset : 0xD9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_TZA_STEP_RCP : DCOC_TZA_STEP_RCP
bits : 0 - 12 (13 bit)
access : read-write
DCOC_TZA_STEP_GAIN : DCOC_TZA_STEP_GAIN
bits : 16 - 27 (12 bit)
access : read-write
DCOC Offset
address_offset : 0xE44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBF_OFFSET_I : DCOC BBF I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBF_OFFSET_Q : DCOC BBF Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
Receive Channel Filter Coefficient
address_offset : 0xF10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_CH_FILT_HX : RX Channel Filter Coefficient
bits : 0 - 7 (8 bit)
access : read-write
DCOC Offset
address_offset : 0xF2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBF_OFFSET_I : DCOC BBF I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBF_OFFSET_Q : DCOC BBF Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
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