\n

ZLL

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x180 byte (0x0)
mem_usage : registers
protection : not protected

Registers

IRQSTS

T1CMP

PKT_BUFFER13

PKT_BUFFER14

PKT_BUFFER15

T2CMP

PKT_BUFFER16

PKT_BUFFER17

PKT_BUFFER18

PKT_BUFFER19

T2PRIMECMP

PKT_BUFFER20

PKT_BUFFER21

PKT_BUFFER22

T3CMP

PKT_BUFFER23

PKT_BUFFER24

T4CMP

PKT_BUFFER0

PKT_BUFFER25

PKT_BUFFER26

PKT_BUFFER27

PA_PWR

PKT_BUFFER28

PKT_BUFFER29

PKT_BUFFER30

CHANNEL_NUM0

PKT_BUFFER31

LQI_AND_RSSI

MACSHORTADDRS0

PKT_BUFFER1

MACLONGADDRS0_LSB

MACLONGADDRS0_MSB

RX_FRAME_FILTER

PHY_CTRL

CCA_LQI_CTRL

PKT_BUFFER2

CCA2_CTRL

FAD_CTRL

SNF_CTRL

BSM_CTRL

PKT_BUFFER3

MACSHORTADDRS1

MACLONGADDRS1_LSB

MACLONGADDRS1_MSB

DUAL_PAN_CTRL

PKT_BUFFER4

CHANNEL_NUM1

SAM_CTRL

SAM_TABLE

SAM_MATCH

PKT_BUFFER5

SAM_FREE_IDX

SEQ_CTRL_STS

ACKDELAY

EVENT_TMR

FILTERFAIL_CODE

RX_WTR_MARK

PKT_BUFFER6

SLOT_PRELOAD

SEQ_STATE

TMR_PRESCALE

PKT_BUFFER7

LENIENCY_LSB

LENIENCY_MSB

PART_ID

PKT_BUFFER8

PKT_BUFFER9

TIMESTAMP

PKT_BUFFER10

PKT_BUFFER11

PKT_BUFFER12


IRQSTS

INTERRUPT REQUEST STATUS
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQSTS IRQSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEQIRQ TXIRQ RXIRQ CCAIRQ RXWTRMRKIRQ FILTERFAIL_IRQ PLL_UNLOCK_IRQ RX_FRM_PEND PB_ERR_IRQ TMRSTATUS PI SRCADDR CCA CRCVALID TMR1IRQ TMR2IRQ TMR3IRQ TMR4IRQ TMR1MSK TMR2MSK TMR3MSK TMR4MSK RX_FRAME_LENGTH

SEQIRQ : Sequence-end Interrupt Status bit. A '1' indicates the completion of an autosequence. This interrupt will assert whenever the Sequence Manager transitions from non-idle to idle state, for any reason. This is write a '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

A Sequencer Interrupt has not occurred

#1 : 1

A Sequencer Interrupt has occurred

End of enumeration elements list.

TXIRQ : Transmitter Interrupt Status bit. A '1' indicates the completion of a transmit operation. This is write a '1' to clear bit.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

A TX Interrupt has not occurred

#1 : 1

A TX Interrupt has occurred

End of enumeration elements list.

RXIRQ : Receiver Interrupt Status bit. A '1' indicates the completion of a receive operation. This is write a '1' to clear bit.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

A RX Interrupt has not occurred

#1 : 1

A RX Interrupt has occurred

End of enumeration elements list.

CCAIRQ : Clear Channel Assessment Interrupt Status bit. A '1' indicates completion of CCA operation. This is write '1' to clear bit.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

A CCA Interrupt has not occurred

#1 : 1

A CCA Interrupt has occurred

End of enumeration elements list.

RXWTRMRKIRQ : Receiver Byte Count Water Mark Interrupt Status bit. A '1' indicates that the number of bytes specified in the RX_WTR_MARK register has been reached. This is write a '1' to clear bit.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

A RX Watermark Interrupt has not occurred

#1 : 1

A RX Watermark Interrupt has occurred

End of enumeration elements list.

FILTERFAIL_IRQ : Receiver Packet Filter Fail Interrupt Status bit. A '1' indicates that the most-recently received packet has been rejected due to elements within the packet. This is write a '1' to clear bit. In Dual PAN mode, FILTERFAIL_IRQ applies to either or both networks, as follows: A: If PAN0 and PAN1 occupy different channels and CURRENT_NETWORK=0, FILTERFAIL_IRQ applies to PAN0. B: If PAN0 and PAN1 occupy different channels and CURRENT_NETWORK=1, FILTERFAIL_IRQ applies to PAN1. C: If PAN0 and PAN1 occupy the same channel, FILTERFAIL_IRQ is the logical 'AND' of the individual PANs' Filter Fail status.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

A Filter Fail Interrupt has not occurred

#1 : 1

A Filter Fail Interrupt has occurred

End of enumeration elements list.

PLL_UNLOCK_IRQ : PLL Un-lock Interrupt Status bit. A '1' indicates an unlock event has occurred in the PLL. This is write a '1' to clear bit.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

A PLL Unlock Interrupt has not occurred

#1 : 1

A PLL Unlock Interrupt has occurred

End of enumeration elements list.

RX_FRM_PEND : Status of the frame pending bit of the frame control field for the most-recently received packet. Read-only.
bits : 7 - 7 (1 bit)
access : read-only

PB_ERR_IRQ : Packet Buffer Underrun Error IRQ
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

A Packet Buffer Underrun Error Interrupt has not occurred

#1 : 1

A Packet Buffer Underrun Error Interrupt has occurred

End of enumeration elements list.

TMRSTATUS : Composite TMR Status
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

#0 : 0

no TMRxIRQ is asserted

#1 : 1

At least one of the TMRxIRQ is asserted (TMR1IRQ, TMR2IRQ, TMR3IRQ, or TMR4IRQ)

End of enumeration elements list.

PI : Poll Indication
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

#0 : 0

the received packet was not a data request

#1 : 1

the received packet was a data request, regardless of whether a Source Address table match occurred, or whether Source Address Management is enabled or not

End of enumeration elements list.

SRCADDR : Source Address Match Status
bits : 13 - 13 (1 bit)
access : read-only

CCA : CCA Status
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

#0 : 0

IDLE

#1 : 1

BUSY

End of enumeration elements list.

CRCVALID : CRC Valid Status
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

#0 : 0

Rx FCS != calculated CRC (incorrect)

#1 : 1

Rx FCS = calculated CRC (correct)

End of enumeration elements list.

TMR1IRQ : Timer 1 IRQ
bits : 16 - 16 (1 bit)
access : read-write

TMR2IRQ : Timer 2 IRQ
bits : 17 - 17 (1 bit)
access : read-write

TMR3IRQ : Timer 3 IRQ
bits : 18 - 18 (1 bit)
access : read-write

TMR4IRQ : Timer 4 IRQ
bits : 19 - 19 (1 bit)
access : read-write

TMR1MSK : Timer Comperator 1 Interrupt Mask bit
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

allows interrupt when comparator matches event timer count

#1 : 1

Interrupt generation is disabled, but a TMR1IRQ flag can be set

End of enumeration elements list.

TMR2MSK : Timer Comperator 2 Interrupt Mask bit
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

allows interrupt when comparator matches event timer count

#1 : 1

Interrupt generation is disabled, but a TMR2IRQ flag can be set

End of enumeration elements list.

TMR3MSK : Timer Comperator 3 Interrupt Mask bit
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

allows interrupt when comparator matches event timer count

#1 : 1

Interrupt generation is disabled, but a TMR3IRQ flag can be set

End of enumeration elements list.

TMR4MSK : Timer Comperator 4 Interrupt Mask bit
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

allows interrupt when comparator matches event timer count

#1 : 1

Interrupt generation is disabled, but a TMR4IRQ flag can be set

End of enumeration elements list.

RX_FRAME_LENGTH : Receive Frame Length
bits : 24 - 30 (7 bit)
access : read-only


T1CMP

T1 COMPARE
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T1CMP T1CMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T1CMP

T1CMP : TMR1 Compare Value
bits : 0 - 23 (24 bit)
access : read-write


PKT_BUFFER13

PACKET BUFFER
address_offset : 0x106C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER13 PKT_BUFFER13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


PKT_BUFFER14

PACKET BUFFER
address_offset : 0x11A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER14 PKT_BUFFER14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


PKT_BUFFER15

PACKET BUFFER
address_offset : 0x12E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER15 PKT_BUFFER15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


T2CMP

T2 COMPARE
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T2CMP T2CMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T2CMP

T2CMP : TMR2 Compare Value
bits : 0 - 23 (24 bit)
access : read-write


PKT_BUFFER16

PACKET BUFFER
address_offset : 0x1420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER16 PKT_BUFFER16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


PKT_BUFFER17

PACKET BUFFER
address_offset : 0x1564 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER17 PKT_BUFFER17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


PKT_BUFFER18

PACKET BUFFER
address_offset : 0x16AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER18 PKT_BUFFER18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


PKT_BUFFER19

PACKET BUFFER
address_offset : 0x17F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER19 PKT_BUFFER19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


T2PRIMECMP

T2 PRIME COMPARE
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T2PRIMECMP T2PRIMECMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T2PRIMECMP

T2PRIMECMP : TMR2 Prime Compare Value
bits : 0 - 15 (16 bit)
access : read-write


PKT_BUFFER20

PACKET BUFFER
address_offset : 0x1948 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER20 PKT_BUFFER20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


PKT_BUFFER21

PACKET BUFFER
address_offset : 0x1A9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER21 PKT_BUFFER21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


PKT_BUFFER22

PACKET BUFFER
address_offset : 0x1BF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER22 PKT_BUFFER22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


T3CMP

T3 COMPARE
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T3CMP T3CMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T3CMP

T3CMP : TMR3 Compare Value
bits : 0 - 23 (24 bit)
access : read-write


PKT_BUFFER23

PACKET BUFFER
address_offset : 0x1D50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER23 PKT_BUFFER23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


PKT_BUFFER24

PACKET BUFFER
address_offset : 0x1EB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER24 PKT_BUFFER24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


T4CMP

T4 COMPARE
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

T4CMP T4CMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T4CMP

T4CMP : TMR4 Compare Value
bits : 0 - 23 (24 bit)
access : read-write


PKT_BUFFER0

PACKET BUFFER
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER0 PKT_BUFFER0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


PKT_BUFFER25

PACKET BUFFER
address_offset : 0x2014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER25 PKT_BUFFER25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


PKT_BUFFER26

PACKET BUFFER
address_offset : 0x217C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER26 PKT_BUFFER26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


PKT_BUFFER27

PACKET BUFFER
address_offset : 0x22E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER27 PKT_BUFFER27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


PA_PWR

PA POWER
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA_PWR PA_PWR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA_PWR

PA_PWR : PA Power
bits : 0 - 3 (4 bit)
access : read-write


PKT_BUFFER28

PACKET BUFFER
address_offset : 0x2458 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER28 PKT_BUFFER28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


PKT_BUFFER29

PACKET BUFFER
address_offset : 0x25CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER29 PKT_BUFFER29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


PKT_BUFFER30

PACKET BUFFER
address_offset : 0x2744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER30 PKT_BUFFER30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


CHANNEL_NUM0

CHANNEL NUMBER 0
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL_NUM0 CHANNEL_NUM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL_NUM0

CHANNEL_NUM0 : Channel Number for PAN0
bits : 0 - 6 (7 bit)
access : read-write


PKT_BUFFER31

PACKET BUFFER
address_offset : 0x28C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER31 PKT_BUFFER31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


LQI_AND_RSSI

LQI AND RSSI
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LQI_AND_RSSI LQI_AND_RSSI read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LQI_VALUE RSSI CCA1_ED_FNL

LQI_VALUE : LQI Value
bits : 0 - 7 (8 bit)
access : read-only

RSSI : RSSI Value
bits : 8 - 15 (8 bit)
access : read-only

CCA1_ED_FNL : RSSI Value
bits : 16 - 23 (8 bit)
access : read-only


MACSHORTADDRS0

MAC SHORT ADDRESS 0
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACSHORTADDRS0 MACSHORTADDRS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MACPANID0 MACSHORTADDRS0

MACPANID0 : MAC PAN ID for PAN0
bits : 0 - 15 (16 bit)
access : read-write

MACSHORTADDRS0 : MAC SHORT ADDRESS for PAN0
bits : 16 - 31 (16 bit)
access : read-write


PKT_BUFFER1

PACKET BUFFER
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER1 PKT_BUFFER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


MACLONGADDRS0_LSB

MAC LONG ADDRESS 0 LSB
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACLONGADDRS0_LSB MACLONGADDRS0_LSB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MACLONGADDRS0_LSB

MACLONGADDRS0_LSB : MAC LONG ADDRESS for PAN0 LSB
bits : 0 - 31 (32 bit)
access : read-write


MACLONGADDRS0_MSB

MAC LONG ADDRESS 0 MSB
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACLONGADDRS0_MSB MACLONGADDRS0_MSB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MACLONGADDRS0_MSB

MACLONGADDRS0_MSB : MAC LONG ADDRESS for PAN0 MSB
bits : 0 - 31 (32 bit)
access : read-write


RX_FRAME_FILTER

RECEIVE FRAME FILTER
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX_FRAME_FILTER RX_FRAME_FILTER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BEACON_FT DATA_FT ACK_FT CMD_FT NS_FT ACTIVE_PROMISCUOUS FRM_VER

BEACON_FT : Beacon Frame Type Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

reject all Beacon frames

#1 : 1

Beacon frame type enabled.

End of enumeration elements list.

DATA_FT : Data Frame Type Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

reject all Data frames

#1 : 1

Data frame type enabled.

End of enumeration elements list.

ACK_FT : Ack Frame Type Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

reject all Acknowledge frames

#1 : 1

Acknowledge frame type enabled.

End of enumeration elements list.

CMD_FT : MAC Command Frame Type Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

reject all MAC Command frames

#1 : 1

MAC Command frame type enabled.

End of enumeration elements list.

NS_FT : Not Specified Frame Type Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

reject all reserved frame types

#1 : 1

Not-specified (reserved) frame type enabled. No packet filtering is performed, except for frame length checking (FrameLength>=5 and FrameLength<=127).

End of enumeration elements list.

ACTIVE_PROMISCUOUS : Active Promiscuous
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

normal operation

#1 : 1

Provide Data Indication on all received packets under the same rules which apply in PROMISCUOUS mode, however acknowledge those packets under rules which apply in non-PROMISCUOUS mode

End of enumeration elements list.

FRM_VER : Frame Version Selector
bits : 6 - 7 (2 bit)
access : read-write


PHY_CTRL

PHY CONTROL
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PHY_CTRL PHY_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XCVSEQ AUTOACK RXACKRQD CCABFRTX SLOTTED TMRTRIGEN SEQMSK TXMSK RXMSK CCAMSK RX_WMRK_MSK FILTERFAIL_MSK PLL_UNLOCK_MSK CRC_MSK PB_ERR_MSK TMR1CMP_EN TMR2CMP_EN TMR3CMP_EN TMR4CMP_EN TC2PRIME_EN PROMISCUOUS TMRLOAD CCATYPE PANCORDNTR0 TC3TMOUT TRCV_MSK

XCVSEQ : Zigbee Transceiver Sequence Selector
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0 : 0

I (IDLE)

#1 : 1

R (RECEIVE)

#010 : 10

T (TRANSMIT)

#011 : 11

C (CCA)

#100 : 100

TR (TRANSMIT/RECEIVE)

#101 : 101

CCCA (CONTINUOUS CCA)

End of enumeration elements list.

AUTOACK : Auto Acknowledge Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

sequence manager will not follow a receive frame with a Tx Ack frame, under any conditions; the autosequence will terminate after the receive frame.

#1 : 1

sequence manager will follow a receive frame with an automatic hardware-generated Tx Ack frame, assuming other necessary conditions are met.

End of enumeration elements list.

RXACKRQD : Receive Acknowledge Frame required
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

An ordinary receive frame (any type of frame) follows the transmit frame.

#1 : 1

A receive Ack frame is expected to follow the transmit frame (non-Ack frames are rejected).

End of enumeration elements list.

CCABFRTX : CCA Before TX
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

no CCA required, transmit operation begins immediately.

#1 : 1

at least one CCA measurement is required prior to the transmit operation (see also SLOTTED).

End of enumeration elements list.

SLOTTED : Slotted Mode
bits : 6 - 6 (1 bit)
access : read-write

TMRTRIGEN : Timer2 Trigger Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

programmed sequence initiates immediately upon write to XCVSEQ.

#1 : 1

allow timer TC2 (or TC2') to initiate a preprogrammed sequence (see XCVSEQ register).

End of enumeration elements list.

SEQMSK : Sequencer Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

allows completion of an autosequence to generate a zigbee interrupt

#1 : 1

Completion of an autosequence will set the SEQIRQ status bit, but a zigbee interrupt is not generated

End of enumeration elements list.

TXMSK : TX Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

allows completion of a TX operation to generate a zigbee interrupt

#1 : 1

Completion of a TX operation will set the TXIRQ status bit, but a zigbee interrupt is not generated

End of enumeration elements list.

RXMSK : RX Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

allows completion of a RX operation to generate a zigbee interrupt

#1 : 1

Completion of a RX operation will set the RXIRQ status bit, but a zigbee interrupt is not generated

End of enumeration elements list.

CCAMSK : CCA Interrupt Mask
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

allows completion of a CCA operation to generate a zigbee interrupt

#1 : 1

Completion of a CCA operation will set the CCAIRQ status bit, but an zigbee interrupt

End of enumeration elements list.

RX_WMRK_MSK : RX Watermark Interrupt Mask
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

allows a Received Byte Count match to the RX_WTR_MARK threshold register to generate a zigbee interrupt

#1 : 1

A Received Byte Count match to the RX_WTR_MARK threshold register will set the RXWTRMRKIRQ status bit, but a zigbee interrupt is not generated

End of enumeration elements list.

FILTERFAIL_MSK : FilterFail Interrupt Mask
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

allows Packet Processor Filtering Failure to generate a zigbee interrupt

#1 : 1

A Packet Processor Filtering Failure will set the FILTERFAIL_IRQ status bit, but a zigbee interrupt is not generated

End of enumeration elements list.

PLL_UNLOCK_MSK : PLL Unlock Interrupt Mask
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

allows PLL unlock event to generate a zigbee interrupt

#1 : 1

A PLL unlock event will set the PLL_UNLOCK_IRQ status bit, but a zigbee interrupt is not generated

End of enumeration elements list.

CRC_MSK : CRC Mask
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

sequence manager ignores CRCVALID and considers the receive operation complete after the last octet of the frame has been received.

#1 : 1

sequence manager requires CRCVALID=1 at the end of the received frame in order for the receive operation to complete successfully; if CRCVALID=0, sequence manager will return to preamble-detect mode after the last octet of the frame has been received.

End of enumeration elements list.

PB_ERR_MSK : Packet Buffer Error Interrupt Mask
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

Enable Packet Buffer Error to assert a zigbee interrupt

#1 : 1

Mask Packet Buffer Error from generating a zigbee interrupt

End of enumeration elements list.

TMR1CMP_EN : Timer 1 Compare Enable
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

Don't allow an Event Timer Match to T1CMP to set TMR1IRQ

#1 : 1

Allow an Event Timer Match to T1CMP to set TMR1IRQ

End of enumeration elements list.

TMR2CMP_EN : Timer 2 Compare Enable
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

Don't allow an Event Timer Match to T2CMP or T2PRIMECMP to set TMR2IRQ

#1 : 1

Allow an Event Timer Match to T2CMP or T2PRIMECMP to set TMR2IRQ

End of enumeration elements list.

TMR3CMP_EN : Timer 3 Compare Enable
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

Don't allow an Event Timer Match to T3CMP to set TMR3IRQ

#1 : 1

Allow an Event Timer Match to T3CMP to set TMR3IRQ

End of enumeration elements list.

TMR4CMP_EN : Timer 4 Compare Enable
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Don't allow an Event Timer Match to T4CMP to set TMR4IRQ

#1 : 1

Allow an Event Timer Match to T4CMP to set TMR4IRQ

End of enumeration elements list.

TC2PRIME_EN : Timer 2 Prime Compare Enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Don't allow a match of the lower 16 bits of Event Timer to T2PRIMECMP to set TMR2IRQ

#1 : 1

Allow a match of the lower 16 bits of Event Timer to T2PRIMECMP to set TMR2IRQ

End of enumeration elements list.

PROMISCUOUS : Promiscuous Mode Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

normal mode

#1 : 1

all packet filtering except frame length checking (FrameLength>=5 and FrameLength<=127) is bypassed.

End of enumeration elements list.

TMRLOAD : Event Timer Load Enable
bits : 26 - 26 (1 bit)
access : write-only

CCATYPE : Clear Channel Assessment Type
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

#0 : 0

ENERGY DETECT

#1 : 1

CCA MODE 1

#10 : 10

CCA MODE 2

#11 : 11

CCA MODE 3

End of enumeration elements list.

PANCORDNTR0 : Device is a PAN Coordinator on PAN0
bits : 29 - 29 (1 bit)
access : read-write

TC3TMOUT : TMR3 Timeout Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

TMR3 is a software timer only

#1 : 1

Enable TMR3 to abort Rx or CCCA operations.

End of enumeration elements list.

TRCV_MSK : Transceiver Global Interrupt Mask
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Enable any unmasked interrupt source to assert zigbee interrupt

#1 : 1

Mask all interrupt sources from asserting zigbee interrupt

End of enumeration elements list.


CCA_LQI_CTRL

CCA AND LQI CONTROL
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCA_LQI_CTRL CCA_LQI_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCA1_THRESH LQI_OFFSET_COMP CCA3_AND_NOT_OR

CCA1_THRESH : CCA Mode 1 Threshold
bits : 0 - 7 (8 bit)
access : read-write

LQI_OFFSET_COMP : LQI Offset Compensation
bits : 16 - 23 (8 bit)
access : read-write

CCA3_AND_NOT_OR : CCA Mode 3 AND not OR
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

CCA1 or CCA2

#1 : 1

CCA1 and CCA2

End of enumeration elements list.


PKT_BUFFER2

PACKET BUFFER
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER2 PKT_BUFFER2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


CCA2_CTRL

CCA2 CONTROL
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCA2_CTRL CCA2_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCA2_NUM_CORR_PEAKS CCA2_MIN_NUM_CORR_TH CCA2_CORR_THRESH

CCA2_NUM_CORR_PEAKS : CCA Mode 2 Number of Correlation Peaks Detected
bits : 0 - 3 (4 bit)
access : read-only

CCA2_MIN_NUM_CORR_TH : CCA Mode 2 Threshold Number of Correlation Peaks
bits : 4 - 6 (3 bit)
access : read-write

CCA2_CORR_THRESH : CCA Mode 2 Correlation Threshold
bits : 8 - 15 (8 bit)
access : read-write


FAD_CTRL

FAD CONTROL
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FAD_CTRL FAD_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAD_EN ANTX FAD_NOT_GPIO ANTX_EN ANTX_HZ ANTX_CTRLMODE ANTX_POL

FAD_EN : FAD Enable
bits : 0 - 0 (1 bit)
access : read-write

ANTX : Antenna Selection
bits : 1 - 1 (1 bit)
access : read-write

FAD_NOT_GPIO : FAD/GPIO Selector
bits : 2 - 2 (1 bit)
access : read-write

ANTX_EN : FAD Antenna Controls Enable
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 00

all disabled (held low)

#01 : 01

only RX/TX_SWITCH enabled

#10 : 10

only ANT_A/B enabled

#11 : 11

all enabled

End of enumeration elements list.

ANTX_HZ : FAD PAD Tristate Control
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

ANT_A, ANT_B, RX_SWITCH and TX_SWITCH are actively driven outputs.

#1 : 1

Antenna controls high impedance- Set ANT_A, ANT_B, RX_SWITCH and TX_SWITCH in high impedance.

End of enumeration elements list.

ANTX_CTRLMODE : Antenna Diversity Control Mode
bits : 11 - 11 (1 bit)
access : read-write

ANTX_POL : Antenna Diversity PAD Polarity
bits : 12 - 15 (4 bit)
access : read-write


SNF_CTRL

SNF CONTROL
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNF_CTRL SNF_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SNF_EN

SNF_EN : SNF Enable
bits : 0 - 0 (1 bit)
access : read-write


BSM_CTRL

BSM CONTROL
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BSM_CTRL BSM_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BSM_EN

BSM_EN : BSM Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Zigbee Bit Streaming Mode Disabled

#1 : 1

Zigbee Bit Streaming Mode Enabled

End of enumeration elements list.


PKT_BUFFER3

PACKET BUFFER
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER3 PKT_BUFFER3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


MACSHORTADDRS1

MAC SHORT ADDRESS 1
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACSHORTADDRS1 MACSHORTADDRS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MACPANID1 MACSHORTADDRS1

MACPANID1 : MAC PAN ID for PAN1
bits : 0 - 15 (16 bit)
access : read-write

MACSHORTADDRS1 : MAC SHORT ADDRESS for PAN1
bits : 16 - 31 (16 bit)
access : read-write


MACLONGADDRS1_LSB

MAC LONG ADDRESS 1 LSB
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACLONGADDRS1_LSB MACLONGADDRS1_LSB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MACLONGADDRS1_LSB

MACLONGADDRS1_LSB : MAC LONG ADDRESS for PAN1 LSB
bits : 0 - 31 (32 bit)
access : read-write


MACLONGADDRS1_MSB

MAC LONG ADDRESS 1 MSB
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACLONGADDRS1_MSB MACLONGADDRS1_MSB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MACLONGADDRS1_MSB

MACLONGADDRS1_MSB : MAC LONG ADDRESS for PAN1 MSB
bits : 0 - 31 (32 bit)
access : read-write


DUAL_PAN_CTRL

DUAL PAN CONTROL
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DUAL_PAN_CTRL DUAL_PAN_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE_NETWORK DUAL_PAN_AUTO PANCORDNTR1 CURRENT_NETWORK ZB_DP_CHAN_OVRD_EN ZB_DP_CHAN_OVRD_SEL DUAL_PAN_DWELL DUAL_PAN_REMAIN RECD_ON_PAN0 RECD_ON_PAN1

ACTIVE_NETWORK : Active Network Selector
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Select PAN0

#1 : 1

Select PAN1

End of enumeration elements list.

DUAL_PAN_AUTO : Activates automatic Dual PAN operating mode
bits : 1 - 1 (1 bit)
access : read-write

PANCORDNTR1 : Device is a PAN Coordinator on PAN1
bits : 2 - 2 (1 bit)
access : read-write

CURRENT_NETWORK : Indicates which PAN is currently selected by hardware
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

#0 : 0

PAN0 is selected

#1 : 1

PAN1 is selected

End of enumeration elements list.

ZB_DP_CHAN_OVRD_EN : Dual PAN Channel Override Enable
bits : 4 - 4 (1 bit)
access : read-write

ZB_DP_CHAN_OVRD_SEL : Dual PAN Channel Override Selector
bits : 5 - 5 (1 bit)
access : read-write

DUAL_PAN_DWELL : Dual PAN Channel Frequency Dwell Time
bits : 8 - 15 (8 bit)
access : read-write

DUAL_PAN_REMAIN : Time Remaining before next PAN switch in auto Dual PAN mode
bits : 16 - 21 (6 bit)
access : read-only

RECD_ON_PAN0 : Last Packet was Received on PAN0
bits : 22 - 22 (1 bit)
access : read-only

RECD_ON_PAN1 : Last Packet was Received on PAN1
bits : 23 - 23 (1 bit)
access : read-only


PKT_BUFFER4

PACKET BUFFER
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER4 PKT_BUFFER4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


CHANNEL_NUM1

CHANNEL NUMBER 1
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL_NUM1 CHANNEL_NUM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL_NUM1

CHANNEL_NUM1 : Channel Number for PAN1
bits : 0 - 6 (7 bit)
access : read-write


SAM_CTRL

SAM CONTROL
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAM_CTRL SAM_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAP0_EN SAA0_EN SAP1_EN SAA1_EN SAA0_START SAP1_START SAA1_START

SAP0_EN : Enables SAP0 Partition of the SAM Table
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disables SAP0 Partition

#1 : 1

Enables SAP0 Partition

End of enumeration elements list.

SAA0_EN : Enables SAA0 Partition of the SAM Table
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disables SAA0 Partition

#1 : 1

Enables SAA0 Partition

End of enumeration elements list.

SAP1_EN : Enables SAP1 Partition of the SAM Table
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disables SAP1 Partition

#1 : 1

Enables SAP1 Partition

End of enumeration elements list.

SAA1_EN : Enables SAA1 Partition of the SAM Table
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disables SAA1 Partition

#1 : 1

Enables SAA1 Partition

End of enumeration elements list.

SAA0_START : First Index of SAA0 partition
bits : 8 - 15 (8 bit)
access : read-write

SAP1_START : First Index of SAP1 partition
bits : 16 - 23 (8 bit)
access : read-write

SAA1_START : First Index of SAA1 partition
bits : 24 - 31 (8 bit)
access : read-write


SAM_TABLE

SOURCE ADDRESS MANAGEMENT TABLE
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAM_TABLE SAM_TABLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAM_INDEX SAM_INDEX_WR SAM_CHECKSUM SAM_INDEX_INV SAM_INDEX_EN ACK_FRM_PND ACK_FRM_PND_CTRL FIND_FREE_IDX INVALIDATE_ALL SAM_BUSY

SAM_INDEX : Contains the SAM table index to be enabled or invalidated
bits : 0 - 6 (7 bit)
access : read-write

SAM_INDEX_WR : Enables SAM Table Contents to be updated
bits : 7 - 7 (1 bit)
access : write-only

SAM_CHECKSUM : Software-computed source address checksum, to be installed into a table index
bits : 8 - 23 (16 bit)
access : read-write

SAM_INDEX_INV : Invalidate the SAM table index selected by SAM_INDEX
bits : 24 - 24 (1 bit)
access : write-only

SAM_INDEX_EN : Enable the SAM table index selected by SAM_INDEX
bits : 25 - 25 (1 bit)
access : write-only

ACK_FRM_PND : Software-override value for the state of the AutoTxAck FramePending field
bits : 26 - 26 (1 bit)
access : read-write

ACK_FRM_PND_CTRL : Software-override control for the state of the AutoTxAck FramePending field
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

the FramePending field of the Frame Control Field of the next automatic TX acknowledge packet is determined by hardware

#1 : 1

the FramePending field of the Frame Control Field of the next automatic TX acknowledge packet tracks ACK_FRM_PEND

End of enumeration elements list.

FIND_FREE_IDX : Find First Free Index
bits : 28 - 28 (1 bit)
access : write-only

INVALIDATE_ALL : Invalidated Entire SAM Table
bits : 29 - 29 (1 bit)
access : write-only

SAM_BUSY : SAM Table Update Status Bit
bits : 31 - 31 (1 bit)
access : read-only


SAM_MATCH

SAM MATCH
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SAM_MATCH SAM_MATCH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAP0_MATCH SAP0_ADDR_PRESENT SAA0_MATCH SAA0_ADDR_ABSENT SAP1_MATCH SAP1_ADDR_PRESENT SAA1_MATCH SAA1_ADDR_ABSENT

SAP0_MATCH : Index in the SAP0 Partition of the SAM Table corresponding to the first checksum match
bits : 0 - 6 (7 bit)
access : read-only

SAP0_ADDR_PRESENT : A Checksum Match is Present in the SAP0 Partition of the SAM Table
bits : 7 - 7 (1 bit)
access : read-only

SAA0_MATCH : Index in the SAA0 Partition of the SAM Table corresponding to the first checksum match
bits : 8 - 14 (7 bit)
access : read-only

SAA0_ADDR_ABSENT : A Checksum Match is Absent in the SAA0 Partition of the SAM Table
bits : 15 - 15 (1 bit)
access : read-only

SAP1_MATCH : Index in the SAP1 Partition of the SAM Table corresponding to the first checksum match
bits : 16 - 22 (7 bit)
access : read-only

SAP1_ADDR_PRESENT : A Checksum Match is Present in the SAP1 Partition of the SAM Table
bits : 23 - 23 (1 bit)
access : read-only

SAA1_MATCH : Index in the SAA1 Partition of the SAM Table corresponding to the first checksum match
bits : 24 - 30 (7 bit)
access : read-only

SAA1_ADDR_ABSENT : A Checksum Match is Absent in the SAP1 Partition of the SAM Table
bits : 31 - 31 (1 bit)
access : read-only


PKT_BUFFER5

PACKET BUFFER
address_offset : 0x73C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER5 PKT_BUFFER5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


SAM_FREE_IDX

SAM FREE INDEX
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SAM_FREE_IDX SAM_FREE_IDX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAP0_1ST_FREE_IDX SAA0_1ST_FREE_IDX SAP1_1ST_FREE_IDX SAA1_1ST_FREE_IDX

SAP0_1ST_FREE_IDX : First non-enabled (invalid) index in the SAP0 partition
bits : 0 - 7 (8 bit)
access : read-only

SAA0_1ST_FREE_IDX : First non-enabled (invalid) index in the SAA0 partition
bits : 8 - 15 (8 bit)
access : read-only

SAP1_1ST_FREE_IDX : First non-enabled (invalid) index in the SAP1 partition
bits : 16 - 23 (8 bit)
access : read-only

SAA1_1ST_FREE_IDX : First non-enabled (invalid) index in the SAA1 partition
bits : 24 - 31 (8 bit)
access : read-only


SEQ_CTRL_STS

SEQUENCE CONTROL AND STATUS
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEQ_CTRL_STS SEQ_CTRL_STS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLR_NEW_SEQ_INHIBIT EVENT_TMR_DO_NOT_LATCH LATCH_PREAMBLE NO_RX_RECYCLE FORCE_CRC_ERROR CONTINUOUS_EN XCVSEQ_ACTUAL SEQ_IDLE NEW_SEQ_INHIBIT RX_TIMEOUT_PENDING RX_MODE TMR2_SEQ_TRIG_ARMED SEQ_T_STATUS SW_ABORTED TC3_ABORTED PLL_ABORTED

CLR_NEW_SEQ_INHIBIT : Overrides the automatic hardware locking of the programmed XCVSEQ while an autosequence is underway
bits : 2 - 2 (1 bit)
access : read-write

EVENT_TMR_DO_NOT_LATCH : Overrides the automatic hardware latching of the Event Timer
bits : 3 - 3 (1 bit)
access : read-write

LATCH_PREAMBLE : Stickiness Control for Preamble Detection
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Don't make PREAMBLE_DET and SFD_DET bits of PHY_STS (SEQ_STATE) Register "sticky", i.e, these status bits reflect the realtime, dynamic state of preamble_detect and sfd_detect

#1 : 1

Make PREAMBLE_DET and SFD_DET bits of PHY_STS (SEQ_STATE) Register "sticky", i.e.,occurrences of preamble and SFD detection are latched and held until the start of the next autosequence

End of enumeration elements list.

NO_RX_RECYCLE : Disable Automatic RX Sequence Recycling
bits : 5 - 5 (1 bit)
access : read-write

FORCE_CRC_ERROR : Induce a CRC Error in Transmitted Packets
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

normal operation

#1 : 1

Force the next transmitted packet to have a CRC error

End of enumeration elements list.

CONTINUOUS_EN : Enable Continuous TX or RX Mode
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

normal operation

#1 : 1

Continuous TX or RX mode is enabled (depending on XCVSEQ setting).

End of enumeration elements list.

XCVSEQ_ACTUAL : Reflects the programmed sequence that has been recognized by the ZSM Sequence Manager
bits : 8 - 10 (3 bit)
access : read-only

SEQ_IDLE : ZSM Sequence Idle Indicator
bits : 11 - 11 (1 bit)
access : read-only

NEW_SEQ_INHIBIT : New Sequence Inhibit
bits : 12 - 12 (1 bit)
access : read-only

RX_TIMEOUT_PENDING : Indicates a TMR3 RX Timeout is Pending
bits : 13 - 13 (1 bit)
access : read-only

RX_MODE : RX Operation in Progress
bits : 14 - 14 (1 bit)
access : read-only

TMR2_SEQ_TRIG_ARMED : indicates that TMR2 has been programmed and is armed to trigger a new autosequence
bits : 15 - 15 (1 bit)
access : read-only

SEQ_T_STATUS : Status of the just-completed or ongoing Sequence T or Sequence TR
bits : 16 - 21 (6 bit)
access : read-only

SW_ABORTED : Autosequence has terminated due to a Software abort.
bits : 24 - 24 (1 bit)
access : read-only

TC3_ABORTED : Autosequence has terminated due to an TMR3 timeout
bits : 25 - 25 (1 bit)
access : read-only

PLL_ABORTED : Autosequence has terminated due to an PLL unlock event
bits : 26 - 26 (1 bit)
access : read-only


ACKDELAY

ACK DELAY
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACKDELAY ACKDELAY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACKDELAY TXDELAY

ACKDELAY : Provides a fine-tune adjustment of the time delay between Rx warmdown and the beginning of Tx warmup for an autoTxAck packet
bits : 0 - 5 (6 bit)
access : read-write

TXDELAY : Provides a fine-tune adjustment of the time delay between post-CCA Rx warm-down and the beginning of Tx warm-up
bits : 8 - 13 (6 bit)
access : read-write


EVENT_TMR

EVENT TIMER
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EVENT_TMR EVENT_TMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENT_TMR

EVENT_TMR : Event Timer
bits : 0 - 23 (24 bit)
access : read-only


FILTERFAIL_CODE

FILTER FAIL CODE
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FILTERFAIL_CODE FILTERFAIL_CODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILTERFAIL_CODE FILTERFAIL_PAN_SEL

FILTERFAIL_CODE : Filter Fail Code
bits : 0 - 9 (10 bit)
access : read-only

FILTERFAIL_PAN_SEL : PAN Selector for Filter Fail Code
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

FILTERFAIL_CODE[9:0] will report the FILTERFAIL status of PAN0

#1 : 1

FILTERFAIL_CODE[9:0] will report the FILTERFAIL status of PAN1

End of enumeration elements list.


RX_WTR_MARK

RECEIVE WATER MARK
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX_WTR_MARK RX_WTR_MARK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX_WTR_MARK

RX_WTR_MARK : Receive byte count needed to trigger a RXWTRMRKIRQ interrupt
bits : 0 - 7 (8 bit)
access : read-write


PKT_BUFFER6

PACKET BUFFER
address_offset : 0x854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER6 PKT_BUFFER6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


SLOT_PRELOAD

SLOT PRELOAD
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLOT_PRELOAD SLOT_PRELOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_PRELOAD

SLOT_PRELOAD : Slotted Mode Preload
bits : 0 - 7 (8 bit)
access : read-write


SEQ_STATE

ZIGBEE SEQUENCE STATE
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SEQ_STATE SEQ_STATE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEQ_STATE PREAMBLE_DET SFD_DET FILTERFAIL_FLAG_SEL CRCVALID PLL_ABORT PLL_ABORTED RX_BYTE_COUNT CCCA_BUSY_CNT

SEQ_STATE : ZSM Sequence State
bits : 0 - 4 (5 bit)
access : read-only

PREAMBLE_DET : Preamble Detected
bits : 8 - 8 (1 bit)
access : read-only

SFD_DET : SFD Detected
bits : 9 - 9 (1 bit)
access : read-only

FILTERFAIL_FLAG_SEL : Consolidated Filter Fail Flag
bits : 10 - 10 (1 bit)
access : read-only

CRCVALID : CRC Valid Indicator
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

#0 : 0

Rx FCS != calculated CRC (incorrect)

#1 : 1

Rx FCS = calculated CRC (correct)

End of enumeration elements list.

PLL_ABORT : Raw PLL Abort Signal
bits : 12 - 12 (1 bit)
access : read-only

PLL_ABORTED : Autosequence has terminated due to an PLL unlock event
bits : 13 - 13 (1 bit)
access : read-only

RX_BYTE_COUNT : Realtime Received Byte Count
bits : 16 - 23 (8 bit)
access : read-only

CCCA_BUSY_CNT : Number of CCA Measurements resulting in Busy Channel
bits : 24 - 29 (6 bit)
access : read-only


TMR_PRESCALE

TIMER PRESCALER
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMR_PRESCALE TMR_PRESCALE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMR_PRESCALE

TMR_PRESCALE : Timer Prescaler
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#010 : 010

500kHz (33.55 S)

#011 : 011

250kHz (67.11 S) -- default

#100 : 100

125kHz (134.22 S)

#101 : 101

62.5kHz (268.44 S)

#110 : 110

31.25kHz (536.87 S)

#111 : 111

15.625kHz (1073.74 S)

End of enumeration elements list.


PKT_BUFFER7

PACKET BUFFER
address_offset : 0x970 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER7 PKT_BUFFER7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


LENIENCY_LSB

LENIENCY LSB
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LENIENCY_LSB LENIENCY_LSB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENIENCY_REGISTER

LENIENCY_REGISTER : Leniency Register, bits [31:0]
bits : 0 - 31 (32 bit)
access : read-write


LENIENCY_MSB

LENIENCY MSB
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LENIENCY_MSB LENIENCY_MSB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENIENCY_REGISTER

LENIENCY_REGISTER : Leniency Register, bits [39:32]
bits : 0 - 7 (8 bit)
access : read-write


PART_ID

PART ID
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PART_ID PART_ID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PART_ID

PART_ID : Zigbee Part ID
bits : 0 - 7 (8 bit)
access : read-only


PKT_BUFFER8

PACKET BUFFER
address_offset : 0xA90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER8 PKT_BUFFER8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


PKT_BUFFER9

PACKET BUFFER
address_offset : 0xBB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER9 PKT_BUFFER9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


TIMESTAMP

TIMESTAMP
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TIMESTAMP TIMESTAMP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMESTAMP

TIMESTAMP : Timestamp
bits : 0 - 23 (24 bit)
access : read-only


PKT_BUFFER10

PACKET BUFFER
address_offset : 0xCDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER10 PKT_BUFFER10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


PKT_BUFFER11

PACKET BUFFER
address_offset : 0xE08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER11 PKT_BUFFER11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write


PKT_BUFFER12

PACKET BUFFER
address_offset : 0xF38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKT_BUFFER12 PKT_BUFFER12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKT_BUFFER

PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.