\n
address_offset : 0x0 Bytes (0x0)
size : 0x180 byte (0x0)
mem_usage : registers
protection : not protected
INTERRUPT REQUEST STATUS
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEQIRQ : Sequence-end Interrupt Status bit. A '1' indicates the completion of an autosequence. This interrupt will assert whenever the Sequence Manager transitions from non-idle to idle state, for any reason. This is write a '1' to clear bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
A Sequencer Interrupt has not occurred
#1 : 1
A Sequencer Interrupt has occurred
End of enumeration elements list.
TXIRQ : Transmitter Interrupt Status bit. A '1' indicates the completion of a transmit operation. This is write a '1' to clear bit.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
A TX Interrupt has not occurred
#1 : 1
A TX Interrupt has occurred
End of enumeration elements list.
RXIRQ : Receiver Interrupt Status bit. A '1' indicates the completion of a receive operation. This is write a '1' to clear bit.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
A RX Interrupt has not occurred
#1 : 1
A RX Interrupt has occurred
End of enumeration elements list.
CCAIRQ : Clear Channel Assessment Interrupt Status bit. A '1' indicates completion of CCA operation. This is write '1' to clear bit.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
A CCA Interrupt has not occurred
#1 : 1
A CCA Interrupt has occurred
End of enumeration elements list.
RXWTRMRKIRQ : Receiver Byte Count Water Mark Interrupt Status bit. A '1' indicates that the number of bytes specified in the RX_WTR_MARK register has been reached. This is write a '1' to clear bit.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
A RX Watermark Interrupt has not occurred
#1 : 1
A RX Watermark Interrupt has occurred
End of enumeration elements list.
FILTERFAIL_IRQ : Receiver Packet Filter Fail Interrupt Status bit. A '1' indicates that the most-recently received packet has been rejected due to elements within the packet. This is write a '1' to clear bit. In Dual PAN mode, FILTERFAIL_IRQ applies to either or both networks, as follows: A: If PAN0 and PAN1 occupy different channels and CURRENT_NETWORK=0, FILTERFAIL_IRQ applies to PAN0. B: If PAN0 and PAN1 occupy different channels and CURRENT_NETWORK=1, FILTERFAIL_IRQ applies to PAN1. C: If PAN0 and PAN1 occupy the same channel, FILTERFAIL_IRQ is the logical 'AND' of the individual PANs' Filter Fail status.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
A Filter Fail Interrupt has not occurred
#1 : 1
A Filter Fail Interrupt has occurred
End of enumeration elements list.
PLL_UNLOCK_IRQ : PLL Un-lock Interrupt Status bit. A '1' indicates an unlock event has occurred in the PLL. This is write a '1' to clear bit.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
A PLL Unlock Interrupt has not occurred
#1 : 1
A PLL Unlock Interrupt has occurred
End of enumeration elements list.
RX_FRM_PEND : Status of the frame pending bit of the frame control field for the most-recently received packet. Read-only.
bits : 7 - 7 (1 bit)
access : read-only
PB_ERR_IRQ : Packet Buffer Underrun Error IRQ
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
A Packet Buffer Underrun Error Interrupt has not occurred
#1 : 1
A Packet Buffer Underrun Error Interrupt has occurred
End of enumeration elements list.
TMRSTATUS : Composite TMR Status
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
#0 : 0
no TMRxIRQ is asserted
#1 : 1
At least one of the TMRxIRQ is asserted (TMR1IRQ, TMR2IRQ, TMR3IRQ, or TMR4IRQ)
End of enumeration elements list.
PI : Poll Indication
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
the received packet was not a data request
#1 : 1
the received packet was a data request, regardless of whether a Source Address table match occurred, or whether Source Address Management is enabled or not
End of enumeration elements list.
SRCADDR : Source Address Match Status
bits : 13 - 13 (1 bit)
access : read-only
CCA : CCA Status
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
#0 : 0
IDLE
#1 : 1
BUSY
End of enumeration elements list.
CRCVALID : CRC Valid Status
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
Rx FCS != calculated CRC (incorrect)
#1 : 1
Rx FCS = calculated CRC (correct)
End of enumeration elements list.
TMR1IRQ : Timer 1 IRQ
bits : 16 - 16 (1 bit)
access : read-write
TMR2IRQ : Timer 2 IRQ
bits : 17 - 17 (1 bit)
access : read-write
TMR3IRQ : Timer 3 IRQ
bits : 18 - 18 (1 bit)
access : read-write
TMR4IRQ : Timer 4 IRQ
bits : 19 - 19 (1 bit)
access : read-write
TMR1MSK : Timer Comperator 1 Interrupt Mask bit
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
allows interrupt when comparator matches event timer count
#1 : 1
Interrupt generation is disabled, but a TMR1IRQ flag can be set
End of enumeration elements list.
TMR2MSK : Timer Comperator 2 Interrupt Mask bit
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
allows interrupt when comparator matches event timer count
#1 : 1
Interrupt generation is disabled, but a TMR2IRQ flag can be set
End of enumeration elements list.
TMR3MSK : Timer Comperator 3 Interrupt Mask bit
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
allows interrupt when comparator matches event timer count
#1 : 1
Interrupt generation is disabled, but a TMR3IRQ flag can be set
End of enumeration elements list.
TMR4MSK : Timer Comperator 4 Interrupt Mask bit
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
allows interrupt when comparator matches event timer count
#1 : 1
Interrupt generation is disabled, but a TMR4IRQ flag can be set
End of enumeration elements list.
RX_FRAME_LENGTH : Receive Frame Length
bits : 24 - 30 (7 bit)
access : read-only
T1 COMPARE
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T1CMP : TMR1 Compare Value
bits : 0 - 23 (24 bit)
access : read-write
PACKET BUFFER
address_offset : 0x106C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
PACKET BUFFER
address_offset : 0x11A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
PACKET BUFFER
address_offset : 0x12E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
T2 COMPARE
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T2CMP : TMR2 Compare Value
bits : 0 - 23 (24 bit)
access : read-write
PACKET BUFFER
address_offset : 0x1420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
PACKET BUFFER
address_offset : 0x1564 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
PACKET BUFFER
address_offset : 0x16AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
PACKET BUFFER
address_offset : 0x17F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
T2 PRIME COMPARE
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T2PRIMECMP : TMR2 Prime Compare Value
bits : 0 - 15 (16 bit)
access : read-write
PACKET BUFFER
address_offset : 0x1948 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
PACKET BUFFER
address_offset : 0x1A9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
PACKET BUFFER
address_offset : 0x1BF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
T3 COMPARE
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T3CMP : TMR3 Compare Value
bits : 0 - 23 (24 bit)
access : read-write
PACKET BUFFER
address_offset : 0x1D50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
PACKET BUFFER
address_offset : 0x1EB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
T4 COMPARE
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T4CMP : TMR4 Compare Value
bits : 0 - 23 (24 bit)
access : read-write
PACKET BUFFER
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
PACKET BUFFER
address_offset : 0x2014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
PACKET BUFFER
address_offset : 0x217C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
PACKET BUFFER
address_offset : 0x22E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
PA POWER
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA_PWR : PA Power
bits : 0 - 3 (4 bit)
access : read-write
PACKET BUFFER
address_offset : 0x2458 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
PACKET BUFFER
address_offset : 0x25CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
PACKET BUFFER
address_offset : 0x2744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
CHANNEL NUMBER 0
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL_NUM0 : Channel Number for PAN0
bits : 0 - 6 (7 bit)
access : read-write
PACKET BUFFER
address_offset : 0x28C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
LQI AND RSSI
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LQI_VALUE : LQI Value
bits : 0 - 7 (8 bit)
access : read-only
RSSI : RSSI Value
bits : 8 - 15 (8 bit)
access : read-only
CCA1_ED_FNL : RSSI Value
bits : 16 - 23 (8 bit)
access : read-only
MAC SHORT ADDRESS 0
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACPANID0 : MAC PAN ID for PAN0
bits : 0 - 15 (16 bit)
access : read-write
MACSHORTADDRS0 : MAC SHORT ADDRESS for PAN0
bits : 16 - 31 (16 bit)
access : read-write
PACKET BUFFER
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
MAC LONG ADDRESS 0 LSB
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACLONGADDRS0_LSB : MAC LONG ADDRESS for PAN0 LSB
bits : 0 - 31 (32 bit)
access : read-write
MAC LONG ADDRESS 0 MSB
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACLONGADDRS0_MSB : MAC LONG ADDRESS for PAN0 MSB
bits : 0 - 31 (32 bit)
access : read-write
RECEIVE FRAME FILTER
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BEACON_FT : Beacon Frame Type Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
reject all Beacon frames
#1 : 1
Beacon frame type enabled.
End of enumeration elements list.
DATA_FT : Data Frame Type Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
reject all Data frames
#1 : 1
Data frame type enabled.
End of enumeration elements list.
ACK_FT : Ack Frame Type Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
reject all Acknowledge frames
#1 : 1
Acknowledge frame type enabled.
End of enumeration elements list.
CMD_FT : MAC Command Frame Type Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
reject all MAC Command frames
#1 : 1
MAC Command frame type enabled.
End of enumeration elements list.
NS_FT : Not Specified Frame Type Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
reject all reserved frame types
#1 : 1
Not-specified (reserved) frame type enabled. No packet filtering is performed, except for frame length checking (FrameLength>=5 and FrameLength<=127).
End of enumeration elements list.
ACTIVE_PROMISCUOUS : Active Promiscuous
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
normal operation
#1 : 1
Provide Data Indication on all received packets under the same rules which apply in PROMISCUOUS mode, however acknowledge those packets under rules which apply in non-PROMISCUOUS mode
End of enumeration elements list.
FRM_VER : Frame Version Selector
bits : 6 - 7 (2 bit)
access : read-write
PHY CONTROL
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XCVSEQ : Zigbee Transceiver Sequence Selector
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#0 : 0
I (IDLE)
#1 : 1
R (RECEIVE)
#010 : 10
T (TRANSMIT)
#011 : 11
C (CCA)
#100 : 100
TR (TRANSMIT/RECEIVE)
#101 : 101
CCCA (CONTINUOUS CCA)
End of enumeration elements list.
AUTOACK : Auto Acknowledge Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
sequence manager will not follow a receive frame with a Tx Ack frame, under any conditions; the autosequence will terminate after the receive frame.
#1 : 1
sequence manager will follow a receive frame with an automatic hardware-generated Tx Ack frame, assuming other necessary conditions are met.
End of enumeration elements list.
RXACKRQD : Receive Acknowledge Frame required
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
An ordinary receive frame (any type of frame) follows the transmit frame.
#1 : 1
A receive Ack frame is expected to follow the transmit frame (non-Ack frames are rejected).
End of enumeration elements list.
CCABFRTX : CCA Before TX
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
no CCA required, transmit operation begins immediately.
#1 : 1
at least one CCA measurement is required prior to the transmit operation (see also SLOTTED).
End of enumeration elements list.
SLOTTED : Slotted Mode
bits : 6 - 6 (1 bit)
access : read-write
TMRTRIGEN : Timer2 Trigger Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
programmed sequence initiates immediately upon write to XCVSEQ.
#1 : 1
allow timer TC2 (or TC2') to initiate a preprogrammed sequence (see XCVSEQ register).
End of enumeration elements list.
SEQMSK : Sequencer Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
allows completion of an autosequence to generate a zigbee interrupt
#1 : 1
Completion of an autosequence will set the SEQIRQ status bit, but a zigbee interrupt is not generated
End of enumeration elements list.
TXMSK : TX Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
allows completion of a TX operation to generate a zigbee interrupt
#1 : 1
Completion of a TX operation will set the TXIRQ status bit, but a zigbee interrupt is not generated
End of enumeration elements list.
RXMSK : RX Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
allows completion of a RX operation to generate a zigbee interrupt
#1 : 1
Completion of a RX operation will set the RXIRQ status bit, but a zigbee interrupt is not generated
End of enumeration elements list.
CCAMSK : CCA Interrupt Mask
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
allows completion of a CCA operation to generate a zigbee interrupt
#1 : 1
Completion of a CCA operation will set the CCAIRQ status bit, but an zigbee interrupt
End of enumeration elements list.
RX_WMRK_MSK : RX Watermark Interrupt Mask
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
allows a Received Byte Count match to the RX_WTR_MARK threshold register to generate a zigbee interrupt
#1 : 1
A Received Byte Count match to the RX_WTR_MARK threshold register will set the RXWTRMRKIRQ status bit, but a zigbee interrupt is not generated
End of enumeration elements list.
FILTERFAIL_MSK : FilterFail Interrupt Mask
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
allows Packet Processor Filtering Failure to generate a zigbee interrupt
#1 : 1
A Packet Processor Filtering Failure will set the FILTERFAIL_IRQ status bit, but a zigbee interrupt is not generated
End of enumeration elements list.
PLL_UNLOCK_MSK : PLL Unlock Interrupt Mask
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
allows PLL unlock event to generate a zigbee interrupt
#1 : 1
A PLL unlock event will set the PLL_UNLOCK_IRQ status bit, but a zigbee interrupt is not generated
End of enumeration elements list.
CRC_MSK : CRC Mask
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
sequence manager ignores CRCVALID and considers the receive operation complete after the last octet of the frame has been received.
#1 : 1
sequence manager requires CRCVALID=1 at the end of the received frame in order for the receive operation to complete successfully; if CRCVALID=0, sequence manager will return to preamble-detect mode after the last octet of the frame has been received.
End of enumeration elements list.
PB_ERR_MSK : Packet Buffer Error Interrupt Mask
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable Packet Buffer Error to assert a zigbee interrupt
#1 : 1
Mask Packet Buffer Error from generating a zigbee interrupt
End of enumeration elements list.
TMR1CMP_EN : Timer 1 Compare Enable
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Don't allow an Event Timer Match to T1CMP to set TMR1IRQ
#1 : 1
Allow an Event Timer Match to T1CMP to set TMR1IRQ
End of enumeration elements list.
TMR2CMP_EN : Timer 2 Compare Enable
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Don't allow an Event Timer Match to T2CMP or T2PRIMECMP to set TMR2IRQ
#1 : 1
Allow an Event Timer Match to T2CMP or T2PRIMECMP to set TMR2IRQ
End of enumeration elements list.
TMR3CMP_EN : Timer 3 Compare Enable
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Don't allow an Event Timer Match to T3CMP to set TMR3IRQ
#1 : 1
Allow an Event Timer Match to T3CMP to set TMR3IRQ
End of enumeration elements list.
TMR4CMP_EN : Timer 4 Compare Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Don't allow an Event Timer Match to T4CMP to set TMR4IRQ
#1 : 1
Allow an Event Timer Match to T4CMP to set TMR4IRQ
End of enumeration elements list.
TC2PRIME_EN : Timer 2 Prime Compare Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Don't allow a match of the lower 16 bits of Event Timer to T2PRIMECMP to set TMR2IRQ
#1 : 1
Allow a match of the lower 16 bits of Event Timer to T2PRIMECMP to set TMR2IRQ
End of enumeration elements list.
PROMISCUOUS : Promiscuous Mode Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
normal mode
#1 : 1
all packet filtering except frame length checking (FrameLength>=5 and FrameLength<=127) is bypassed.
End of enumeration elements list.
TMRLOAD : Event Timer Load Enable
bits : 26 - 26 (1 bit)
access : write-only
CCATYPE : Clear Channel Assessment Type
bits : 27 - 28 (2 bit)
access : read-write
Enumeration:
#0 : 0
ENERGY DETECT
#1 : 1
CCA MODE 1
#10 : 10
CCA MODE 2
#11 : 11
CCA MODE 3
End of enumeration elements list.
PANCORDNTR0 : Device is a PAN Coordinator on PAN0
bits : 29 - 29 (1 bit)
access : read-write
TC3TMOUT : TMR3 Timeout Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
TMR3 is a software timer only
#1 : 1
Enable TMR3 to abort Rx or CCCA operations.
End of enumeration elements list.
TRCV_MSK : Transceiver Global Interrupt Mask
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable any unmasked interrupt source to assert zigbee interrupt
#1 : 1
Mask all interrupt sources from asserting zigbee interrupt
End of enumeration elements list.
CCA AND LQI CONTROL
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCA1_THRESH : CCA Mode 1 Threshold
bits : 0 - 7 (8 bit)
access : read-write
LQI_OFFSET_COMP : LQI Offset Compensation
bits : 16 - 23 (8 bit)
access : read-write
CCA3_AND_NOT_OR : CCA Mode 3 AND not OR
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
CCA1 or CCA2
#1 : 1
CCA1 and CCA2
End of enumeration elements list.
PACKET BUFFER
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
CCA2 CONTROL
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCA2_NUM_CORR_PEAKS : CCA Mode 2 Number of Correlation Peaks Detected
bits : 0 - 3 (4 bit)
access : read-only
CCA2_MIN_NUM_CORR_TH : CCA Mode 2 Threshold Number of Correlation Peaks
bits : 4 - 6 (3 bit)
access : read-write
CCA2_CORR_THRESH : CCA Mode 2 Correlation Threshold
bits : 8 - 15 (8 bit)
access : read-write
FAD CONTROL
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FAD_EN : FAD Enable
bits : 0 - 0 (1 bit)
access : read-write
ANTX : Antenna Selection
bits : 1 - 1 (1 bit)
access : read-write
FAD_NOT_GPIO : FAD/GPIO Selector
bits : 2 - 2 (1 bit)
access : read-write
ANTX_EN : FAD Antenna Controls Enable
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
all disabled (held low)
#01 : 01
only RX/TX_SWITCH enabled
#10 : 10
only ANT_A/B enabled
#11 : 11
all enabled
End of enumeration elements list.
ANTX_HZ : FAD PAD Tristate Control
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
ANT_A, ANT_B, RX_SWITCH and TX_SWITCH are actively driven outputs.
#1 : 1
Antenna controls high impedance- Set ANT_A, ANT_B, RX_SWITCH and TX_SWITCH in high impedance.
End of enumeration elements list.
ANTX_CTRLMODE : Antenna Diversity Control Mode
bits : 11 - 11 (1 bit)
access : read-write
ANTX_POL : Antenna Diversity PAD Polarity
bits : 12 - 15 (4 bit)
access : read-write
SNF CONTROL
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SNF_EN : SNF Enable
bits : 0 - 0 (1 bit)
access : read-write
BSM CONTROL
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BSM_EN : BSM Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Zigbee Bit Streaming Mode Disabled
#1 : 1
Zigbee Bit Streaming Mode Enabled
End of enumeration elements list.
PACKET BUFFER
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
MAC SHORT ADDRESS 1
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACPANID1 : MAC PAN ID for PAN1
bits : 0 - 15 (16 bit)
access : read-write
MACSHORTADDRS1 : MAC SHORT ADDRESS for PAN1
bits : 16 - 31 (16 bit)
access : read-write
MAC LONG ADDRESS 1 LSB
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACLONGADDRS1_LSB : MAC LONG ADDRESS for PAN1 LSB
bits : 0 - 31 (32 bit)
access : read-write
MAC LONG ADDRESS 1 MSB
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACLONGADDRS1_MSB : MAC LONG ADDRESS for PAN1 MSB
bits : 0 - 31 (32 bit)
access : read-write
DUAL PAN CONTROL
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE_NETWORK : Active Network Selector
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Select PAN0
#1 : 1
Select PAN1
End of enumeration elements list.
DUAL_PAN_AUTO : Activates automatic Dual PAN operating mode
bits : 1 - 1 (1 bit)
access : read-write
PANCORDNTR1 : Device is a PAN Coordinator on PAN1
bits : 2 - 2 (1 bit)
access : read-write
CURRENT_NETWORK : Indicates which PAN is currently selected by hardware
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
PAN0 is selected
#1 : 1
PAN1 is selected
End of enumeration elements list.
ZB_DP_CHAN_OVRD_EN : Dual PAN Channel Override Enable
bits : 4 - 4 (1 bit)
access : read-write
ZB_DP_CHAN_OVRD_SEL : Dual PAN Channel Override Selector
bits : 5 - 5 (1 bit)
access : read-write
DUAL_PAN_DWELL : Dual PAN Channel Frequency Dwell Time
bits : 8 - 15 (8 bit)
access : read-write
DUAL_PAN_REMAIN : Time Remaining before next PAN switch in auto Dual PAN mode
bits : 16 - 21 (6 bit)
access : read-only
RECD_ON_PAN0 : Last Packet was Received on PAN0
bits : 22 - 22 (1 bit)
access : read-only
RECD_ON_PAN1 : Last Packet was Received on PAN1
bits : 23 - 23 (1 bit)
access : read-only
PACKET BUFFER
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
CHANNEL NUMBER 1
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL_NUM1 : Channel Number for PAN1
bits : 0 - 6 (7 bit)
access : read-write
SAM CONTROL
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAP0_EN : Enables SAP0 Partition of the SAM Table
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables SAP0 Partition
#1 : 1
Enables SAP0 Partition
End of enumeration elements list.
SAA0_EN : Enables SAA0 Partition of the SAM Table
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables SAA0 Partition
#1 : 1
Enables SAA0 Partition
End of enumeration elements list.
SAP1_EN : Enables SAP1 Partition of the SAM Table
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables SAP1 Partition
#1 : 1
Enables SAP1 Partition
End of enumeration elements list.
SAA1_EN : Enables SAA1 Partition of the SAM Table
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables SAA1 Partition
#1 : 1
Enables SAA1 Partition
End of enumeration elements list.
SAA0_START : First Index of SAA0 partition
bits : 8 - 15 (8 bit)
access : read-write
SAP1_START : First Index of SAP1 partition
bits : 16 - 23 (8 bit)
access : read-write
SAA1_START : First Index of SAA1 partition
bits : 24 - 31 (8 bit)
access : read-write
SOURCE ADDRESS MANAGEMENT TABLE
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAM_INDEX : Contains the SAM table index to be enabled or invalidated
bits : 0 - 6 (7 bit)
access : read-write
SAM_INDEX_WR : Enables SAM Table Contents to be updated
bits : 7 - 7 (1 bit)
access : write-only
SAM_CHECKSUM : Software-computed source address checksum, to be installed into a table index
bits : 8 - 23 (16 bit)
access : read-write
SAM_INDEX_INV : Invalidate the SAM table index selected by SAM_INDEX
bits : 24 - 24 (1 bit)
access : write-only
SAM_INDEX_EN : Enable the SAM table index selected by SAM_INDEX
bits : 25 - 25 (1 bit)
access : write-only
ACK_FRM_PND : Software-override value for the state of the AutoTxAck FramePending field
bits : 26 - 26 (1 bit)
access : read-write
ACK_FRM_PND_CTRL : Software-override control for the state of the AutoTxAck FramePending field
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
the FramePending field of the Frame Control Field of the next automatic TX acknowledge packet is determined by hardware
#1 : 1
the FramePending field of the Frame Control Field of the next automatic TX acknowledge packet tracks ACK_FRM_PEND
End of enumeration elements list.
FIND_FREE_IDX : Find First Free Index
bits : 28 - 28 (1 bit)
access : write-only
INVALIDATE_ALL : Invalidated Entire SAM Table
bits : 29 - 29 (1 bit)
access : write-only
SAM_BUSY : SAM Table Update Status Bit
bits : 31 - 31 (1 bit)
access : read-only
SAM MATCH
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SAP0_MATCH : Index in the SAP0 Partition of the SAM Table corresponding to the first checksum match
bits : 0 - 6 (7 bit)
access : read-only
SAP0_ADDR_PRESENT : A Checksum Match is Present in the SAP0 Partition of the SAM Table
bits : 7 - 7 (1 bit)
access : read-only
SAA0_MATCH : Index in the SAA0 Partition of the SAM Table corresponding to the first checksum match
bits : 8 - 14 (7 bit)
access : read-only
SAA0_ADDR_ABSENT : A Checksum Match is Absent in the SAA0 Partition of the SAM Table
bits : 15 - 15 (1 bit)
access : read-only
SAP1_MATCH : Index in the SAP1 Partition of the SAM Table corresponding to the first checksum match
bits : 16 - 22 (7 bit)
access : read-only
SAP1_ADDR_PRESENT : A Checksum Match is Present in the SAP1 Partition of the SAM Table
bits : 23 - 23 (1 bit)
access : read-only
SAA1_MATCH : Index in the SAA1 Partition of the SAM Table corresponding to the first checksum match
bits : 24 - 30 (7 bit)
access : read-only
SAA1_ADDR_ABSENT : A Checksum Match is Absent in the SAP1 Partition of the SAM Table
bits : 31 - 31 (1 bit)
access : read-only
PACKET BUFFER
address_offset : 0x73C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
SAM FREE INDEX
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SAP0_1ST_FREE_IDX : First non-enabled (invalid) index in the SAP0 partition
bits : 0 - 7 (8 bit)
access : read-only
SAA0_1ST_FREE_IDX : First non-enabled (invalid) index in the SAA0 partition
bits : 8 - 15 (8 bit)
access : read-only
SAP1_1ST_FREE_IDX : First non-enabled (invalid) index in the SAP1 partition
bits : 16 - 23 (8 bit)
access : read-only
SAA1_1ST_FREE_IDX : First non-enabled (invalid) index in the SAA1 partition
bits : 24 - 31 (8 bit)
access : read-only
SEQUENCE CONTROL AND STATUS
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR_NEW_SEQ_INHIBIT : Overrides the automatic hardware locking of the programmed XCVSEQ while an autosequence is underway
bits : 2 - 2 (1 bit)
access : read-write
EVENT_TMR_DO_NOT_LATCH : Overrides the automatic hardware latching of the Event Timer
bits : 3 - 3 (1 bit)
access : read-write
LATCH_PREAMBLE : Stickiness Control for Preamble Detection
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Don't make PREAMBLE_DET and SFD_DET bits of PHY_STS (SEQ_STATE) Register "sticky", i.e, these status bits reflect the realtime, dynamic state of preamble_detect and sfd_detect
#1 : 1
Make PREAMBLE_DET and SFD_DET bits of PHY_STS (SEQ_STATE) Register "sticky", i.e.,occurrences of preamble and SFD detection are latched and held until the start of the next autosequence
End of enumeration elements list.
NO_RX_RECYCLE : Disable Automatic RX Sequence Recycling
bits : 5 - 5 (1 bit)
access : read-write
FORCE_CRC_ERROR : Induce a CRC Error in Transmitted Packets
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
normal operation
#1 : 1
Force the next transmitted packet to have a CRC error
End of enumeration elements list.
CONTINUOUS_EN : Enable Continuous TX or RX Mode
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
normal operation
#1 : 1
Continuous TX or RX mode is enabled (depending on XCVSEQ setting).
End of enumeration elements list.
XCVSEQ_ACTUAL : Reflects the programmed sequence that has been recognized by the ZSM Sequence Manager
bits : 8 - 10 (3 bit)
access : read-only
SEQ_IDLE : ZSM Sequence Idle Indicator
bits : 11 - 11 (1 bit)
access : read-only
NEW_SEQ_INHIBIT : New Sequence Inhibit
bits : 12 - 12 (1 bit)
access : read-only
RX_TIMEOUT_PENDING : Indicates a TMR3 RX Timeout is Pending
bits : 13 - 13 (1 bit)
access : read-only
RX_MODE : RX Operation in Progress
bits : 14 - 14 (1 bit)
access : read-only
TMR2_SEQ_TRIG_ARMED : indicates that TMR2 has been programmed and is armed to trigger a new autosequence
bits : 15 - 15 (1 bit)
access : read-only
SEQ_T_STATUS : Status of the just-completed or ongoing Sequence T or Sequence TR
bits : 16 - 21 (6 bit)
access : read-only
SW_ABORTED : Autosequence has terminated due to a Software abort.
bits : 24 - 24 (1 bit)
access : read-only
TC3_ABORTED : Autosequence has terminated due to an TMR3 timeout
bits : 25 - 25 (1 bit)
access : read-only
PLL_ABORTED : Autosequence has terminated due to an PLL unlock event
bits : 26 - 26 (1 bit)
access : read-only
ACK DELAY
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACKDELAY : Provides a fine-tune adjustment of the time delay between Rx warmdown and the beginning of Tx warmup for an autoTxAck packet
bits : 0 - 5 (6 bit)
access : read-write
TXDELAY : Provides a fine-tune adjustment of the time delay between post-CCA Rx warm-down and the beginning of Tx warm-up
bits : 8 - 13 (6 bit)
access : read-write
EVENT TIMER
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EVENT_TMR : Event Timer
bits : 0 - 23 (24 bit)
access : read-only
FILTER FAIL CODE
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILTERFAIL_CODE : Filter Fail Code
bits : 0 - 9 (10 bit)
access : read-only
FILTERFAIL_PAN_SEL : PAN Selector for Filter Fail Code
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
FILTERFAIL_CODE[9:0] will report the FILTERFAIL status of PAN0
#1 : 1
FILTERFAIL_CODE[9:0] will report the FILTERFAIL status of PAN1
End of enumeration elements list.
RECEIVE WATER MARK
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_WTR_MARK : Receive byte count needed to trigger a RXWTRMRKIRQ interrupt
bits : 0 - 7 (8 bit)
access : read-write
PACKET BUFFER
address_offset : 0x854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
SLOT PRELOAD
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_PRELOAD : Slotted Mode Preload
bits : 0 - 7 (8 bit)
access : read-write
ZIGBEE SEQUENCE STATE
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEQ_STATE : ZSM Sequence State
bits : 0 - 4 (5 bit)
access : read-only
PREAMBLE_DET : Preamble Detected
bits : 8 - 8 (1 bit)
access : read-only
SFD_DET : SFD Detected
bits : 9 - 9 (1 bit)
access : read-only
FILTERFAIL_FLAG_SEL : Consolidated Filter Fail Flag
bits : 10 - 10 (1 bit)
access : read-only
CRCVALID : CRC Valid Indicator
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
#0 : 0
Rx FCS != calculated CRC (incorrect)
#1 : 1
Rx FCS = calculated CRC (correct)
End of enumeration elements list.
PLL_ABORT : Raw PLL Abort Signal
bits : 12 - 12 (1 bit)
access : read-only
PLL_ABORTED : Autosequence has terminated due to an PLL unlock event
bits : 13 - 13 (1 bit)
access : read-only
RX_BYTE_COUNT : Realtime Received Byte Count
bits : 16 - 23 (8 bit)
access : read-only
CCCA_BUSY_CNT : Number of CCA Measurements resulting in Busy Channel
bits : 24 - 29 (6 bit)
access : read-only
TIMER PRESCALER
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMR_PRESCALE : Timer Prescaler
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#010 : 010
500kHz (33.55 S)
#011 : 011
250kHz (67.11 S) -- default
#100 : 100
125kHz (134.22 S)
#101 : 101
62.5kHz (268.44 S)
#110 : 110
31.25kHz (536.87 S)
#111 : 111
15.625kHz (1073.74 S)
End of enumeration elements list.
PACKET BUFFER
address_offset : 0x970 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
LENIENCY LSB
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LENIENCY_REGISTER : Leniency Register, bits [31:0]
bits : 0 - 31 (32 bit)
access : read-write
LENIENCY MSB
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LENIENCY_REGISTER : Leniency Register, bits [39:32]
bits : 0 - 7 (8 bit)
access : read-write
PART ID
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PART_ID : Zigbee Part ID
bits : 0 - 7 (8 bit)
access : read-only
PACKET BUFFER
address_offset : 0xA90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
PACKET BUFFER
address_offset : 0xBB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
TIMESTAMP
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TIMESTAMP : Timestamp
bits : 0 - 23 (24 bit)
access : read-only
PACKET BUFFER
address_offset : 0xCDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
PACKET BUFFER
address_offset : 0xE08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
PACKET BUFFER
address_offset : 0xF38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PKT_BUFFER : Packet Buffer Entry
bits : 0 - 31 (32 bit)
access : read-write
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