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INTREQ

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xB Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0xC4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DRQSEL

EXC02MON

IRQ00MON

IRQ01MON

IRQ02MON

IRQ03MON

IRQ04MON

IRQ05MON

IRQ06MON

IRQ07MON

IRQ08MON

IRQ09MON

IRQ10MON

IRQ11MON

IRQ12MON

IRQ13MON

IRQ14MON

IRQ15MON

IRQ16MON

IRQ17MON

IRQ18MON

IRQ19MON

IRQ20MON

IRQ21MON

IRQ22MON

IRQ23MON

IRQ24MON

IRQ25MON

IRQ26MON

IRQ28MON

IRQ29MON

IRQ30MON

IRQ31MON

IRQ38MON

IRQ39MON

IRQ40MON

IRQ41MON

IRQ42MON

IRQ43MON

IRQ44MON

IRQ45MON


DRQSEL

DMA Request Selection Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRQSEL DRQSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCSCAN0 ADCSCAN1 ADCSCAN2 IRQ0BT0 IRQ0BT2 IRQ0BT3 IRQ0BT4 IRQ0BT6 MFS0RX MFS0TX MFS1RX MFS1TX MFS2RX MFS2TX MFS3RX MFS3TX MFS4RX MFS4TX MFS5RX MFS5TX MFS6RX MFS6TX MFS7RX MFS7TX EXINT0 EXINT1 EXINT2 EXINT3

ADCSCAN0 : The scan conversion interrupt signal of the A/D converter unit 0 is output as a transfer request to the DMAC.
bits : 5 - 4 (0 bit)
access : read-write

ADCSCAN1 : The scan conversion interrupt signal of the A/D converter unit 1 is output as a transfer request to the DMAC.
bits : 6 - 5 (0 bit)
access : read-write

ADCSCAN2 : The scan conversion interrupt signal of the A/D converter unit 2 is output as a transfer request to the DMAC.
bits : 7 - 6 (0 bit)
access : read-write

IRQ0BT0 : The IRQ0 interrupt signal of the base timer ch.0 is output as a transfer request to the DMAC.
bits : 8 - 7 (0 bit)
access : read-write

IRQ0BT2 : The IRQ0 interrupt signal of the base timer ch.3 is output as a transfer request to the DMAC.
bits : 9 - 8 (0 bit)
access : read-write

IRQ0BT3 : The IRQ0 interrupt signal of the base timer ch.3 is output as a transfer request to the DMAC.
bits : 9 - 8 (0 bit)
access : read-write

IRQ0BT4 : The IRQ0 interrupt signal of the base timer ch.4 is output as a transfer request to the DMAC.
bits : 10 - 9 (0 bit)
access : read-write

IRQ0BT6 : The IRQ0 interrupt signal of the base timer ch.6 is output as a transfer request to the DMAC.
bits : 11 - 10 (0 bit)
access : read-write

MFS0RX : The reception interrupt signal of the MFS ch.0 is output as a transfer request to the DMAC (including extension).
bits : 12 - 11 (0 bit)
access : read-write

MFS0TX : The transmission interrupt signal of the MFS ch.0 is output as a transfer request to the DMAC (including extension).
bits : 13 - 12 (0 bit)
access : read-write

MFS1RX : The reception interrupt signal of the MFS ch.1 is output as a transfer request to the DMAC (including extension).
bits : 14 - 13 (0 bit)
access : read-write

MFS1TX : The transmission interrupt signal of the MFS ch.1 is output as a transfer request to the DMAC (including extension).
bits : 15 - 14 (0 bit)
access : read-write

MFS2RX : The reception interrupt signal of the MFS ch.2 is output as a transfer request to the DMAC (including extension).
bits : 16 - 15 (0 bit)
access : read-write

MFS2TX : The transmission interrupt signal of the MFS ch.2 is output as a transfer request to the DMAC (including extension).
bits : 17 - 16 (0 bit)
access : read-write

MFS3RX : The reception interrupt signal of the MFS ch.3 is output as a transfer request to the DMAC (including extension).
bits : 18 - 17 (0 bit)
access : read-write

MFS3TX : The transmission interrupt signal of the MFS ch.3 is output as a transfer request to the DMAC (including extension).
bits : 19 - 18 (0 bit)
access : read-write

MFS4RX : The reception interrupt signal of the MFS ch.4 is output as a transfer request to the DMAC (including extension).
bits : 20 - 19 (0 bit)
access : read-write

MFS4TX : The transmission interrupt signal of the MFS ch.4 is output as a transfer request to the DMAC (including extension).
bits : 21 - 20 (0 bit)
access : read-write

MFS5RX : The reception interrupt signal of the MFS ch.5 is output as a transfer request to the DMAC (including extension).
bits : 22 - 21 (0 bit)
access : read-write

MFS5TX : The transmission interrupt signal of the MFS ch.5 is output as a transfer request to the DMAC (including extension).
bits : 23 - 22 (0 bit)
access : read-write

MFS6RX : The reception interrupt signal of the MFS ch.6 is output as a transfer request to the DMAC (including extension).
bits : 24 - 23 (0 bit)
access : read-write

MFS6TX : The transmission interrupt signal of the MFS ch.6 is output as a transfer request to the DMAC (including extension).
bits : 25 - 24 (0 bit)
access : read-write

MFS7RX : The reception interrupt signal of the MFS ch.7 is output as a transfer request to the DMAC (including extension).
bits : 26 - 25 (0 bit)
access : read-write

MFS7TX : The transmission interrupt signal of the MFS ch.7 is output as a transfer request to the DMAC (including extension).
bits : 27 - 26 (0 bit)
access : read-write

EXINT0 : The interrupt signal of the external interrupt ch.0 is output as a transfer request to the DMAC (including extension).
bits : 28 - 27 (0 bit)
access : read-write

EXINT1 : The interrupt signal of the external interrupt ch.1 is output as a transfer request to the DMAC (including extension).
bits : 29 - 28 (0 bit)
access : read-write

EXINT2 : The interrupt signal of the external interrupt ch.2 is output as a transfer request to the DMAC (including extension).
bits : 30 - 29 (0 bit)
access : read-write

EXINT3 : The interrupt signal of the external interrupt ch.3 is output as a transfer request to the DMAC (including extension).
bits : 31 - 30 (0 bit)
access : read-write


EXC02MON

EXC02 batch read register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXC02MON EXC02MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NMI HWINT

NMI : External NMIX pin interrupt request
bits : 0 - -1 (0 bit)
access : read-write

HWINT : Hardware watchdog timer interrupt request
bits : 1 - 0 (0 bit)
access : read-write


IRQ00MON

IRQ00 Batch Read Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ00MON IRQ00MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCSINT

FCSINT : Anomalous frequency detection by CSV interrupt request
bits : 0 - -1 (0 bit)
access : read-write


IRQ01MON

IRQ01 Batch Read Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ01MON IRQ01MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWWDTINT

SWWDTINT : Software watchdog timer interrupt request
bits : 0 - -1 (0 bit)
access : read-write


IRQ02MON

IRQ02 Batch Read Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ02MON IRQ02MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVDINT

LVDINT : Low voltage detection (LVD) interrupt request
bits : 0 - -1 (0 bit)
access : read-write


IRQ03MON

IRQ03 Batch Read Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ03MON IRQ03MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAVE0INT0 WAVE0INT1 WAVE0INT2 WAVE0INT3

WAVE0INT0 : DTIF (motor emergency stop) interrupt request in MFT unit 0
bits : 0 - -1 (0 bit)
access : read-write

WAVE0INT1 : WFG timer 10 interrupt request in MFT unit 0
bits : 1 - 0 (0 bit)
access : read-write

WAVE0INT2 : WFG timer 32 interrupt request in MFT unit 0
bits : 2 - 1 (0 bit)
access : read-write

WAVE0INT3 : WFG timer 54 interrupt request in MFT unit 0
bits : 3 - 2 (0 bit)
access : read-write


IRQ04MON

IRQ04 Batch Read Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ04MON IRQ04MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTINT0 EXTINT1 EXTINT2 EXTINT3 EXTINT4 EXTINT5 EXTINT6

EXTINT0 : Interrupt request on external interrupt ch.0
bits : 0 - -1 (0 bit)
access : read-write

EXTINT1 : Interrupt request on external interrupt ch.1
bits : 1 - 0 (0 bit)
access : read-write

EXTINT2 : Interrupt request on external interrupt ch.2
bits : 2 - 1 (0 bit)
access : read-write

EXTINT3 : Interrupt request on external interrupt ch.3
bits : 3 - 2 (0 bit)
access : read-write

EXTINT4 : Interrupt request on external interrupt ch.4
bits : 4 - 3 (0 bit)
access : read-write

EXTINT5 : Interrupt request on external interrupt ch.5
bits : 5 - 4 (0 bit)
access : read-write

EXTINT6 : Interrupt request on external interrupt ch.6
bits : 6 - 5 (0 bit)
access : read-write


IRQ05MON

IRQ05 Batch Read Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ05MON IRQ05MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTINT15

EXTINT15 : Interrupt request on external interrupt ch.15
bits : 7 - 6 (0 bit)
access : read-write


IRQ06MON

IRQ06 Batch Read Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ06MON IRQ06MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMINT1 TIMINT2 QUD0INT0 QUD0INT1 QUD0INT2 QUD0INT3 QUD0INT4 QUD0INT5 QUD1INT0 QUD1INT1 QUD1INT2 QUD1INT3 QUD1INT4 QUD1INT5

TIMINT1 : Dual timer 1 interrupt request
bits : 0 - -1 (0 bit)
access : read-write

TIMINT2 : Dual timer 2 interrupt request
bits : 1 - 0 (0 bit)
access : read-write

QUD0INT0 : PC match interrupt request on QPRC ch.0
bits : 2 - 1 (0 bit)
access : read-write

QUD0INT1 : PC and RC match interrupt request on QPRC ch.0
bits : 3 - 2 (0 bit)
access : read-write

QUD0INT2 : Overflow/underflow/zero index interrupt request on QPRC ch.0
bits : 4 - 3 (0 bit)
access : read-write

QUD0INT3 : PC count invert interrupt request on QPRC ch.0
bits : 5 - 4 (0 bit)
access : read-write

QUD0INT4 : Interrupt request detected RC out of range on QPRC ch.0
bits : 6 - 5 (0 bit)
access : read-write

QUD0INT5 : PC match and RC match interrupt request on QPRC ch.0
bits : 7 - 6 (0 bit)
access : read-write

QUD1INT0 : PC match interrupt request on QPRC ch.1
bits : 8 - 7 (0 bit)
access : read-write

QUD1INT1 : PC and RC match interrupt request on QPRC ch.1
bits : 9 - 8 (0 bit)
access : read-write

QUD1INT2 : Overflow/underflow/zero index interrupt request on QPRC ch.1
bits : 10 - 9 (0 bit)
access : read-write

QUD1INT3 : PC count invert interrupt request on QPRC ch.1
bits : 11 - 10 (0 bit)
access : read-write

QUD1INT4 : Interrupt request detected RC out of range on QPRC ch.1
bits : 12 - 11 (0 bit)
access : read-write

QUD1INT5 : PC match and RC match interrupt request on QPRC ch.1
bits : 13 - 12 (0 bit)
access : read-write


IRQ07MON

IRQ07 Batch Read Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ07MON IRQ07MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT

MFSINT : Reception interrupt request on MFS ch.0
bits : 0 - -1 (0 bit)
access : read-write


IRQ08MON

IRQ08 Batch Read Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ08MON IRQ08MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : Transmission interrupt request on MFS ch.0
bits : 0 - -1 (0 bit)
access : read-write

MFSINT1 : Status interrupt request on MFS ch.0
bits : 1 - 0 (0 bit)
access : read-write


IRQ09MON

IRQ09 Batch Read Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ09MON IRQ09MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT

MFSINT : Reception interrupt request on MFS ch.1
bits : 0 - -1 (0 bit)
access : read-write


IRQ10MON

IRQ10 Batch Read Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ10MON IRQ10MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : Transmission interrupt request on MFS ch.1
bits : 0 - -1 (0 bit)
access : read-write

MFSINT1 : Status interrupt request on MFS ch.1
bits : 1 - 0 (0 bit)
access : read-write


IRQ11MON

IRQ11 Batch Read Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ11MON IRQ11MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT

MFSINT : Reception interrupt request on MFS ch.2
bits : 0 - -1 (0 bit)
access : read-write


IRQ12MON

IRQ12 Batch Read Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ12MON IRQ12MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : Transmission interrupt request on MFS ch.2
bits : 0 - -1 (0 bit)
access : read-write

MFSINT1 : Status interrupt request on MFS ch.2
bits : 1 - 0 (0 bit)
access : read-write


IRQ13MON

IRQ13 Batch Read Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ13MON IRQ13MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT

MFSINT : Reception interrupt request on MFS ch.3
bits : 0 - -1 (0 bit)
access : read-write


IRQ14MON

IRQ14 Batch Read Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ14MON IRQ14MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : Transmission interrupt request on MFS ch.3
bits : 0 - -1 (0 bit)
access : read-write

MFSINT1 : Status interrupt request on MFS ch.3
bits : 1 - 0 (0 bit)
access : read-write


IRQ15MON

IRQ15 Batch Read Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ15MON IRQ15MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT

MFSINT : Reception interrupt request on MFS ch.4
bits : 0 - -1 (0 bit)
access : read-write


IRQ16MON

IRQ16 Batch Read Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ16MON IRQ16MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : Transmission interrupt request on MFS ch.4
bits : 0 - -1 (0 bit)
access : read-write

MFSINT1 : Status interrupt request on MFS ch.4
bits : 1 - 0 (0 bit)
access : read-write


IRQ17MON

IRQ17 Batch Read Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ17MON IRQ17MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT

MFSINT : Reception interrupt request on MFS ch.5
bits : 0 - -1 (0 bit)
access : read-write


IRQ18MON

IRQ18 Batch Read Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ18MON IRQ18MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : Transmission interrupt request on MFS ch.5
bits : 0 - -1 (0 bit)
access : read-write

MFSINT1 : Status interrupt request on MFS ch.5
bits : 1 - 0 (0 bit)
access : read-write


IRQ19MON

IRQ19 Batch Read Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ19MON IRQ19MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT

MFSINT : Reception interrupt request on MFS ch.6
bits : 0 - -1 (0 bit)
access : read-write


IRQ20MON

IRQ20 Batch Read Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ20MON IRQ20MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : Transmission interrupt request on MFS ch.6
bits : 0 - -1 (0 bit)
access : read-write

MFSINT1 : Status interrupt request on MFS ch.6
bits : 1 - 0 (0 bit)
access : read-write


IRQ21MON

IRQ21 Batch Read Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ21MON IRQ21MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT

MFSINT : Reception interrupt request on MFS ch.7
bits : 0 - -1 (0 bit)
access : read-write


IRQ22MON

IRQ22 Batch Read Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ22MON IRQ22MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFSINT0 MFSINT1

MFSINT0 : Transmission interrupt request on MFS ch.7
bits : 0 - -1 (0 bit)
access : read-write

MFSINT1 : Status interrupt request on MFS ch.7
bits : 1 - 0 (0 bit)
access : read-write


IRQ23MON

IRQ23 Batch Read Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ23MON IRQ23MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPGINT0 PPGINT1 PPGINT2

PPGINT0 : Interrupt request on PPG ch.0
bits : 0 - -1 (0 bit)
access : read-write

PPGINT1 : Interrupt request on PPG ch.2
bits : 1 - 0 (0 bit)
access : read-write

PPGINT2 : Interrupt request on PPG ch.4
bits : 2 - 1 (0 bit)
access : read-write


IRQ24MON

IRQ24 Batch Read Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ24MON IRQ24MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOSCINT SOSCINT MPLLINT WCINT

MOSCINT : Stabilization wait completion interrupt request for main clock oscillation
bits : 0 - -1 (0 bit)
access : read-write

SOSCINT : Stabilization wait completion interrupt request for sub-clock oscillation
bits : 1 - 0 (0 bit)
access : read-write

MPLLINT : Stabilization wait completion interrupt request for main PLL oscillation
bits : 2 - 1 (0 bit)
access : read-write

WCINT : Watch counter interrupt request
bits : 4 - 3 (0 bit)
access : read-write


IRQ25MON

IRQ25 Batch Read Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ25MON IRQ25MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCINT0 ADCINT1 ADCINT2 ADCINT3

ADCINT0 : Priority conversion interrupt request in the corresponding A/D unit 0.
bits : 0 - -1 (0 bit)
access : read-write

ADCINT1 : Scan conversion interrupt request in the corresponding A/D unit 0.
bits : 1 - 0 (0 bit)
access : read-write

ADCINT2 : FIFO overrun interrupt request in the corresponding A/D unit 0.
bits : 2 - 1 (0 bit)
access : read-write

ADCINT3 : Conversion result comparison interrupt request in the corresponding A/D unit 0.
bits : 3 - 2 (0 bit)
access : read-write


IRQ26MON

IRQ26 Batch Read Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ26MON IRQ26MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCINT0 ADCINT1 ADCINT2 ADCINT3

ADCINT0 : Priority conversion interrupt request in the corresponding A/D unit 1
bits : 0 - -1 (0 bit)
access : read-write

ADCINT1 : Scan conversion interrupt request in the corresponding A/D unit 1
bits : 1 - 0 (0 bit)
access : read-write

ADCINT2 : FIFO overrun interrupt request in the corresponding A/D unit 1
bits : 2 - 1 (0 bit)
access : read-write

ADCINT3 : Conversion result comparison interrupt request in the corresponding A/D unit 1
bits : 3 - 2 (0 bit)
access : read-write


IRQ28MON

IRQ28 Batch Read Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ28MON IRQ28MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRT0INT0 FRT0INT1 FRT0INT2 FRT0INT3 FRT0INT4 FRT0INT5

FRT0INT0 : Peak value detection interrupt request on the free run timer ch.0 in the MFT unit 0
bits : 0 - -1 (0 bit)
access : read-write

FRT0INT1 : Peak value detection interrupt request on the free run timer ch.1 in the MFT unit 0
bits : 1 - 0 (0 bit)
access : read-write

FRT0INT2 : Peak value detection interrupt request on the free run timer ch.2 in the MFT unit 0
bits : 2 - 1 (0 bit)
access : read-write

FRT0INT3 : Zero detection interrupt request on the free run timer ch.0 in the MFT unit 0
bits : 3 - 2 (0 bit)
access : read-write

FRT0INT4 : Zero detection interrupt request on the free run timer ch.1 in the MFT unit 0
bits : 4 - 3 (0 bit)
access : read-write

FRT0INT5 : Zero detection interrupt request on the free run timer ch.2 in the MFT unit 0
bits : 5 - 4 (0 bit)
access : read-write


IRQ29MON

IRQ29 Batch Read Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ29MON IRQ29MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICU0INT0 ICU0INT1 ICU0INT2 ICU0INT3

ICU0INT0 : Interrupt request on the input capture ch.0 in the MFT unit 0
bits : 0 - -1 (0 bit)
access : read-write

ICU0INT1 : Interrupt request on the input capture ch.1 in the MFT unit 0
bits : 1 - 0 (0 bit)
access : read-write

ICU0INT2 : Interrupt request on the input capture ch.2 in the MFT unit 0
bits : 2 - 1 (0 bit)
access : read-write

ICU0INT3 : Interrupt request on the input capture ch.3 in the MFT unit 0
bits : 3 - 2 (0 bit)
access : read-write


IRQ30MON

IRQ30 Batch Read Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ30MON IRQ30MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCU0INT0 OCU0INT1 OCU0INT2 OCU0INT3 OCU0INT4 OCU0INT5

OCU0INT0 : Interrupt request on the output compare ch.0 in the MFT unit 0
bits : 0 - -1 (0 bit)
access : read-write

OCU0INT1 : Interrupt request on the output compare ch.1 in the MFT unit 0
bits : 1 - 0 (0 bit)
access : read-write

OCU0INT2 : Interrupt request on the output compare ch.2 in the MFT unit 0
bits : 2 - 1 (0 bit)
access : read-write

OCU0INT3 : Interrupt request on the output compare ch.3 in the MFT unit 0
bits : 3 - 2 (0 bit)
access : read-write

OCU0INT4 : Interrupt request on the output compare ch.4 in the MFT unit 0
bits : 4 - 3 (0 bit)
access : read-write

OCU0INT5 : Interrupt request on the output compare ch.5 in the MFT unit 0
bits : 5 - 4 (0 bit)
access : read-write


IRQ31MON

IRQ31 Batch Read Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ31MON IRQ31MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTINT0 BTINT1 BTINT2 BTINT3 BTINT4 BTINT5 BTINT6 BTINT7 BTINT8 BTINT9 BTINT10 BTINT11 BTINT12 BTINT13 BTINT14 BTINT15

BTINT0 : IRQ0 interrupt request on the base timer ch.0
bits : 0 - -1 (0 bit)
access : read-write

BTINT1 : IRQ1 interrupt request on the base timer ch.0
bits : 1 - 0 (0 bit)
access : read-write

BTINT2 : IRQ0 interrupt request on the base timer ch.1
bits : 2 - 1 (0 bit)
access : read-write

BTINT3 : IRQ1 interrupt request on the base timer ch.1
bits : 3 - 2 (0 bit)
access : read-write

BTINT4 : IRQ0 interrupt request on the base timer ch.2
bits : 4 - 3 (0 bit)
access : read-write

BTINT5 : IRQ1 interrupt request on the base timer ch.2
bits : 5 - 4 (0 bit)
access : read-write

BTINT6 : IRQ0 interrupt request on the base timer ch.3
bits : 6 - 5 (0 bit)
access : read-write

BTINT7 : IRQ1 interrupt request on the base timer ch.3
bits : 7 - 6 (0 bit)
access : read-write

BTINT8 : IRQ0 interrupt request on the base timer ch.4
bits : 8 - 7 (0 bit)
access : read-write

BTINT9 : IRQ1 interrupt request on the base timer ch.4
bits : 9 - 8 (0 bit)
access : read-write

BTINT10 : IRQ0 interrupt request on the base timer ch.5
bits : 10 - 9 (0 bit)
access : read-write

BTINT11 : IRQ1 interrupt request on the base timer ch.5
bits : 11 - 10 (0 bit)
access : read-write

BTINT12 : IRQ0 interrupt request on the base timer ch.6
bits : 12 - 11 (0 bit)
access : read-write

BTINT13 : IRQ1 interrupt request on the base timer ch.6
bits : 13 - 12 (0 bit)
access : read-write

BTINT14 : IRQ0 interrupt request on the base timer ch.7
bits : 14 - 13 (0 bit)
access : read-write

BTINT15 : IRQ1 interrupt request on the base timer ch.7
bits : 15 - 14 (0 bit)
access : read-write


IRQ38MON

IRQ38 Batch Read Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ38MON IRQ38MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAINT

DMAINT : Interrupt request on DMA ch.0.
bits : 0 - -1 (0 bit)
access : read-write


IRQ39MON

IRQ39 Batch Read Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ39MON IRQ39MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAINT

DMAINT : Interrupt request on DMA ch.1.
bits : 0 - -1 (0 bit)
access : read-write


IRQ40MON

IRQ40 Batch Read Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ40MON IRQ40MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAINT

DMAINT : Interrupt request on DMA ch.2.
bits : 0 - -1 (0 bit)
access : read-write


IRQ41MON

IRQ41 Batch Read Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ41MON IRQ41MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAINT

DMAINT : Interrupt request on DMA ch.3.
bits : 0 - -1 (0 bit)
access : read-write


IRQ42MON

IRQ42 Batch Read Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ42MON IRQ42MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAINT

DMAINT : Interrupt request on DMA ch.4.
bits : 0 - -1 (0 bit)
access : read-write


IRQ43MON

IRQ43 Batch Read Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ43MON IRQ43MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAINT

DMAINT : Interrupt request on DMA ch.5.
bits : 0 - -1 (0 bit)
access : read-write


IRQ44MON

IRQ44 Batch Read Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ44MON IRQ44MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAINT

DMAINT : Interrupt request on DMA ch.6.
bits : 0 - -1 (0 bit)
access : read-write


IRQ45MON

IRQ45 Batch Read Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ45MON IRQ45MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAINT

DMAINT : Interrupt request on DMA ch.7.
bits : 0 - -1 (0 bit)
access : read-write



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