CR

CIER

CIFR

CICR

AHB1RSTR

AHB2RSTR

AHB3RSTR

APB1RSTR1

APB1RSTR2

ICSCR

APB2RSTR

AHB1ENR

AHB2ENR

AHB3ENR

APB1ENR1

APB1ENR2

APB2ENR

AHB1SMENR

AHB2SMENR

AHB3SMENR

APB1SMENR1

APB1SMENR2

CFGR

APB2SMENR

CCIPR1

BDCR

CSR

CRRCR

CCIPR2

PLLSYSCFGR

HSION : HSI clock enable
bits : 8 - 8 (1 bit)
access : read-write

HSIKERON : HSI always enable for peripheral kernels
bits : 9 - 9 (1 bit)
access : read-write

HSIRDY : HSI clock ready flag
bits : 10 - 10 (1 bit)
access : read-only

HSEON : HSE clock enable
bits : 16 - 16 (1 bit)
access : read-write

HSERDY : HSE clock ready flag
bits : 17 - 17 (1 bit)
access : read-only

HSEBYP : HSE crystal oscillator bypass
bits : 18 - 18 (1 bit)
access : read-write

HSECSSON : Clock security system enable
bits : 19 - 19 (1 bit)
access : write-only

PLLSYSON : Main PLL enable
bits : 24 - 24 (1 bit)
access : read-write

PLLSYSRDY : Main PLL clock ready flag
bits : 25 - 25 (1 bit)
access : read-only

LSIRDYIE : LSI ready interrupt enable
bits : 0 - 0 (1 bit)

LSERDYIE : LSE ready interrupt enable
bits : 1 - 1 (1 bit)

HSIRDYIE : HSI ready interrupt enable
bits : 3 - 3 (1 bit)

HSERDYIE : HSE ready interrupt enable
bits : 4 - 4 (1 bit)

PLLSYSRDYIE : PLL ready interrupt enable
bits : 5 - 5 (1 bit)

LSECSSIE : LSE clock security system interrupt enable
bits : 9 - 9 (1 bit)

RC48RDYIE : HSI48 ready interrupt enable
bits : 10 - 10 (1 bit)

LSIRDYF : LSI ready interrupt flag
bits : 0 - 0 (1 bit)

LSERDYF : LSE ready interrupt flag
bits : 1 - 1 (1 bit)

HSIRDYF : HSI ready interrupt flag
bits : 3 - 3 (1 bit)

HSERDYF : HSE ready interrupt flag
bits : 4 - 4 (1 bit)

PLLSYSRDYF : PLL ready interrupt flag
bits : 5 - 5 (1 bit)

HSECSSF : Clock security system interrupt flag
bits : 8 - 8 (1 bit)

LSECSSF : LSE Clock security system interrupt flag
bits : 9 - 9 (1 bit)

RC48RDYF : HSI48 ready interrupt flag
bits : 10 - 10 (1 bit)

LSIRDYC : LSI ready interrupt clear
bits : 0 - 0 (1 bit)

LSERDYC : LSE ready interrupt clear
bits : 1 - 1 (1 bit)

HSIRDYC : HSI ready interrupt clear
bits : 3 - 3 (1 bit)

HSERDYC : HSE ready interrupt clear
bits : 4 - 4 (1 bit)

PLLSYSRDYC : PLL ready interrupt clear
bits : 5 - 5 (1 bit)

HSECSSC : Clock security system interrupt clear
bits : 8 - 8 (1 bit)

LSECSSC : LSE Clock security system interrupt clear
bits : 9 - 9 (1 bit)

RC48RDYC : HSI48 oscillator ready interrupt clear
bits : 10 - 10 (1 bit)

DMA1RST : DMA1 reset
bits : 0 - 0 (1 bit)

DMA2RST : DMA2 reset
bits : 1 - 1 (1 bit)

DMAMUX1RST : DMAMUXRST
bits : 2 - 2 (1 bit)

CORDICRST : CORDIC reset
bits : 3 - 3 (1 bit)

MATRIXRST : MATRIX reset
bits : 4 - 4 (1 bit)

FLITFRST_ : FLITF reset
bits : 8 - 8 (1 bit)

CRCRST : CRC reset
bits : 12 - 12 (1 bit)

GPIOARST : IO port A reset
bits : 0 - 0 (1 bit)

GPIOBRST : IO port B reset
bits : 1 - 1 (1 bit)

GPIOCRST : IO port C reset
bits : 2 - 2 (1 bit)

GPIODRST : IO port D reset
bits : 3 - 3 (1 bit)

GPIOERST : IO port E reset
bits : 4 - 4 (1 bit)

GPIOFRST : IO port F reset
bits : 5 - 5 (1 bit)

GPIOGRST : IO port G reset
bits : 6 - 6 (1 bit)

ADC12RST : ADC reset
bits : 13 - 13 (1 bit)

ADC345RST_ : SAR ADC345 interface reset
bits : 14 - 14 (1 bit)

DAC1RST_ : DAC1 interface reset
bits : 16 - 16 (1 bit)

DAC2RST : DAC2 interface reset
bits : 17 - 17 (1 bit)

DAC3RST : DAC3 interface reset
bits : 18 - 18 (1 bit)

DAC4RST : DAC4 interface reset
bits : 19 - 19 (1 bit)

CRYPTRST : Cryptography module reset
bits : 24 - 24 (1 bit)

RNGRST : Random Number Generator module reset
bits : 26 - 26 (1 bit)

FMCRST : Flexible memory controller reset
bits : 0 - 0 (1 bit)

QUADSPI1RST : Quad SPI 1 module reset
bits : 8 - 8 (1 bit)

TIM2RST : TIM2 timer reset
bits : 0 - 0 (1 bit)

TIM3RST : TIM3 timer reset
bits : 1 - 1 (1 bit)

TIM4RST : TIM3 timer reset
bits : 2 - 2 (1 bit)

TIM5RST : TIM5 timer reset
bits : 3 - 3 (1 bit)

TIM6RST : TIM6 timer reset
bits : 4 - 4 (1 bit)

TIM7RST : TIM7 timer reset
bits : 5 - 5 (1 bit)

CRSRST : Clock recovery system reset
bits : 8 - 8 (1 bit)

SPI2RST : SPI2 reset
bits : 14 - 14 (1 bit)

SPI3RST : SPI3 reset
bits : 15 - 15 (1 bit)

USART2RST : USART2 reset
bits : 17 - 17 (1 bit)

USART3RST : USART3 reset
bits : 18 - 18 (1 bit)

UART4RST : UART4 reset
bits : 19 - 19 (1 bit)

UART5RST : UART5 reset
bits : 20 - 20 (1 bit)

I2C1RST : I2C1 reset
bits : 21 - 21 (1 bit)

I2C2RST : I2C2 reset
bits : 22 - 22 (1 bit)

USBDRST : USBD reset
bits : 23 - 23 (1 bit)

FDCANRST : FDCAN reset
bits : 25 - 25 (1 bit)

PWRRST : Power interface reset
bits : 28 - 28 (1 bit)

I2C3 : I2C3 interface reset
bits : 30 - 30 (1 bit)

LPTIM1RST : Low Power Timer 1 reset
bits : 31 - 31 (1 bit)

LPUART1RST : Low-power UART 1 reset
bits : 0 - 0 (1 bit)

I2C4RST : I2C4 reset
bits : 1 - 1 (1 bit)

USBPDRST : USBPD reset
bits : 8 - 8 (1 bit)

HSICAL0 : Internal High Speed clock Calibration
bits : 16 - 23 (8 bit)
access : read-only

HSITRIM : Internal High Speed clock trimming
bits : 24 - 30 (7 bit)
access : read-write

SYSCFGRST : System configuration (SYSCFG) reset
bits : 0 - 0 (1 bit)

TIM1RST : TIM1 timer reset
bits : 11 - 11 (1 bit)

SPI1RST : SPI1 reset
bits : 12 - 12 (1 bit)

TIM8RST : TIM8 timer reset
bits : 13 - 13 (1 bit)

USART1RST : USART1 reset
bits : 14 - 14 (1 bit)

SPI4RST : SPI 4 reset
bits : 15 - 15 (1 bit)

TIM15RST : TIM15 timer reset
bits : 16 - 16 (1 bit)

TIM16RST : TIM16 timer reset
bits : 17 - 17 (1 bit)

TIM17RST : TIM17 timer reset
bits : 18 - 18 (1 bit)

TIM20RST : Timer 20 reset
bits : 20 - 20 (1 bit)

SAI1RST : Serial audio interface 1 (SAI1) reset
bits : 21 - 21 (1 bit)

HRTIM1RST : HRTIMER reset
bits : 26 - 26 (1 bit)

DMA1EN : DMA1 clock enable
bits : 0 - 0 (1 bit)

DMA2EN : DMA2 clock enable
bits : 1 - 1 (1 bit)

DMAMUXEN : DMAMUX clock enable
bits : 2 - 2 (1 bit)

CORDICEN : CORDIC clock enable
bits : 3 - 3 (1 bit)

FMACEN : FMAC clock enable
bits : 4 - 4 (1 bit)

FLITFEN : FLITF clock enable
bits : 8 - 8 (1 bit)

CRCEN : CRC clock enable
bits : 12 - 12 (1 bit)

GPIOAEN : IO port A clock enable
bits : 0 - 0 (1 bit)

GPIOBEN : IO port B clock enable
bits : 1 - 1 (1 bit)

GPIOCEN : IO port C clock enable
bits : 2 - 2 (1 bit)

GPIODEN : IO port D clock enable
bits : 3 - 3 (1 bit)

GPIOEEN : IO port E clock enable
bits : 4 - 4 (1 bit)

GPIOFEN : IO port F clock enable
bits : 5 - 5 (1 bit)

GPIOGEN : IO port G clock enable
bits : 6 - 6 (1 bit)

ADC12EN : ADC clock enable
bits : 13 - 13 (1 bit)

ADC345EN : DCMI clock enable
bits : 14 - 14 (1 bit)

DAC1 : AES accelerator clock enable
bits : 16 - 16 (1 bit)

DAC2 : HASH clock enable
bits : 17 - 17 (1 bit)

DAC3 : Random Number Generator clock enable
bits : 18 - 18 (1 bit)

DAC4 : DAC4 clock enable
bits : 19 - 19 (1 bit)

CRYPTEN : Cryptography clock enable
bits : 24 - 24 (1 bit)

RNGEN : Random Number Generator clock enable
bits : 26 - 26 (1 bit)

FMCEN : Flexible memory controller clock enable
bits : 0 - 0 (1 bit)

QUADSPI1EN : Quad SPI 1 module clock enable
bits : 8 - 8 (1 bit)

TIM2EN : TIM2 timer clock enable
bits : 0 - 0 (1 bit)

TIM3EN : TIM3 timer clock enable
bits : 1 - 1 (1 bit)

TIM4EN : TIM4 timer clock enable
bits : 2 - 2 (1 bit)

TIM5EN : TIM5 timer clock enable
bits : 3 - 3 (1 bit)

TIM6EN : TIM6 timer clock enable
bits : 4 - 4 (1 bit)

TIM7EN : TIM7 timer clock enable
bits : 5 - 5 (1 bit)

CRSEN : CRSclock enable
bits : 8 - 8 (1 bit)

RTCAPBEN : RTC APB clock enable
bits : 10 - 10 (1 bit)

WWDGEN : Window watchdog clock enable
bits : 11 - 11 (1 bit)

SPI2EN : SPI2 clock enable
bits : 14 - 14 (1 bit)

SP3EN : SPI3 clock enable
bits : 15 - 15 (1 bit)

USART2EN : USART2 clock enable
bits : 17 - 17 (1 bit)

USART3EN : USART3 clock enable
bits : 18 - 18 (1 bit)

UART4EN : UART4 clock enable
bits : 19 - 19 (1 bit)

UART5EN : UART5 clock enable
bits : 20 - 20 (1 bit)

I2C1EN : I2C1 clock enable
bits : 21 - 21 (1 bit)

I2C2EN : I2C2 clock enable
bits : 22 - 22 (1 bit)

USBDEN : USBDclock enable
bits : 23 - 23 (1 bit)

FDCANEN : FDCAN clock enable
bits : 25 - 25 (1 bit)

PWREN : Power interface clock enable
bits : 28 - 28 (1 bit)

I2C3 : OPAMP interface clock enable
bits : 30 - 30 (1 bit)

LPTIM1EN : Low power timer 1 clock enable
bits : 31 - 31 (1 bit)

LPUART1EN : Low power UART 1 clock enable
bits : 0 - 0 (1 bit)

I2C4EN : I2C4 clock enable
bits : 1 - 1 (1 bit)

USBPDEN : USBPD clock enable
bits : 8 - 8 (1 bit)

SYSCFGEN : SYSCFG clock enable
bits : 0 - 0 (1 bit)

TIM1EN : TIM1 timer clock enable
bits : 11 - 11 (1 bit)

SPI1EN : SPI1 clock enable
bits : 12 - 12 (1 bit)

TIM8EN : TIM8 timer clock enable
bits : 13 - 13 (1 bit)

USART1EN : USART1clock enable
bits : 14 - 14 (1 bit)

SPI4EN : SPI 4 clock enable
bits : 15 - 15 (1 bit)

TIM15EN : TIM15 timer clock enable
bits : 16 - 16 (1 bit)

TIM16EN : TIM16 timer clock enable
bits : 17 - 17 (1 bit)

TIM17EN : TIM17 timer clock enable
bits : 18 - 18 (1 bit)

TIM20EN : Timer 20 clock enable
bits : 20 - 20 (1 bit)

SAI1EN : SAI1 clock enable
bits : 21 - 21 (1 bit)

HRTIMEREN : HRTIMER clock enable
bits : 26 - 26 (1 bit)

DMA1SMEN : DMA1 clocks enable during Sleep and Stop modes
bits : 0 - 0 (1 bit)

DMA2SMEN : DMA2 clocks enable during Sleep and Stop modes
bits : 1 - 1 (1 bit)

DMAMUX1SMEN : DMAMUX clock enable during Sleep and Stop modes
bits : 2 - 2 (1 bit)

CORDICSMEN : CORDIC clock enable during sleep mode
bits : 3 - 3 (1 bit)

FMACSMEN : FMACSM clock enable
bits : 4 - 4 (1 bit)

FLASHSMEN : Flash memory interface clocks enable during Sleep and Stop modes
bits : 8 - 8 (1 bit)

SRAM1SMEN : SRAM1 interface clocks enable during Sleep and Stop modes
bits : 9 - 9 (1 bit)

CRCSMEN : CRCSMEN
bits : 12 - 12 (1 bit)

GPIOASMEN : IO port A clocks enable during Sleep and Stop modes
bits : 0 - 0 (1 bit)

GPIOBSMEN : IO port B clocks enable during Sleep and Stop modes
bits : 1 - 1 (1 bit)

GPIOCSMEN : IO port C clocks enable during Sleep and Stop modes
bits : 2 - 2 (1 bit)

GPIODSMEN : IO port D clocks enable during Sleep and Stop modes
bits : 3 - 3 (1 bit)

GPIOESMEN : IO port E clocks enable during Sleep and Stop modes
bits : 4 - 4 (1 bit)

GPIOFSMEN : IO port F clocks enable during Sleep and Stop modes
bits : 5 - 5 (1 bit)

GPIOGSMEN : IO port G clocks enable during Sleep and Stop modes
bits : 6 - 6 (1 bit)

SRAM2SMEN : SRAM2 interface clocks enable during Sleep and Stop modes
bits : 9 - 9 (1 bit)

SRAM3SMEN : SRAM2 interface clocks enable during Sleep and Stop modes
bits : 10 - 10 (1 bit)

AD12CSMEN : ADC clocks enable during Sleep and Stop modes
bits : 13 - 13 (1 bit)

ADC345SMEN : DCMI clock enable during Sleep and Stop modes
bits : 14 - 14 (1 bit)

DAC1SMEN : AES accelerator clocks enable during Sleep and Stop modes
bits : 16 - 16 (1 bit)

DAC2SMEN : HASH clock enable during Sleep and Stop modes
bits : 17 - 17 (1 bit)

DAC3SMEN : DAC3 clock enable during sleep mode
bits : 18 - 18 (1 bit)

DAC4SMEN : DAC4 clock enable during sleep mode
bits : 19 - 19 (1 bit)

CRYPTSMEN : Cryptography clock enable during sleep mode
bits : 24 - 24 (1 bit)

RNGSMEN : Random Number Generator clock enable during sleep mode
bits : 26 - 26 (1 bit)

FMCSMEN : Flexible memory controller clocks enable during Sleep and Stop modes
bits : 0 - 0 (1 bit)

QUADSPI1SMEN : QUAD SPI 1 module clock enable during sleep mode
bits : 8 - 8 (1 bit)

TIM2SMEN : TIM2 timer clocks enable during Sleep and Stop modes
bits : 0 - 0 (1 bit)

TIM3SMEN : TIM3 timer clocks enable during Sleep and Stop modes
bits : 1 - 1 (1 bit)

TIM4SMEN : TIM4 timer clocks enable during Sleep and Stop modes
bits : 2 - 2 (1 bit)

TIM5SMEN : TIM5 timer clocks enable during Sleep and Stop modes
bits : 3 - 3 (1 bit)

TIM6SMEN : TIM6 timer clocks enable during Sleep and Stop modes
bits : 4 - 4 (1 bit)

TIM7SMEN : TIM7 timer clocks enable during Sleep and Stop modes
bits : 5 - 5 (1 bit)

CRSSMEN : CRS clock enable during sleep mode
bits : 8 - 8 (1 bit)

RTCAPBSMEN : RTC APB clock enable during Sleep and Stop modes
bits : 10 - 10 (1 bit)

WWDGSMEN : Window watchdog clocks enable during Sleep and Stop modes
bits : 11 - 11 (1 bit)

SPI2SMEN : SPI2 clocks enable during Sleep and Stop modes
bits : 14 - 14 (1 bit)

SP3SMEN : SPI3 clocks enable during Sleep and Stop modes
bits : 15 - 15 (1 bit)

USART2SMEN : USART2 clocks enable during Sleep and Stop modes
bits : 17 - 17 (1 bit)

USART3SMEN : USART3 clocks enable during Sleep and Stop modes
bits : 18 - 18 (1 bit)

UART4SMEN : UART4 clocks enable during Sleep and Stop modes
bits : 19 - 19 (1 bit)

UART5SMEN : UART5 clocks enable during Sleep and Stop modes
bits : 20 - 20 (1 bit)

I2C1SMEN : I2C1 clocks enable during Sleep and Stop modes
bits : 21 - 21 (1 bit)

I2C2SMEN : I2C2 clocks enable during Sleep and Stop modes
bits : 22 - 22 (1 bit)

I2C3SMEN : I2C3 clocks enable during Sleep and Stop modes
bits : 23 - 23 (1 bit)

FDCANSMEN : FDCAN clock enable during sleep mode
bits : 25 - 25 (1 bit)

PWRSMEN : Power interface clocks enable during Sleep and Stop modes
bits : 28 - 28 (1 bit)

I2C3SMEN_3 : I2C 3 interface clock enable during sleep mode
bits : 30 - 30 (1 bit)

LPTIM1SMEN : Low Power Timer1 clock enable during sleep mode
bits : 31 - 31 (1 bit)

LPUART1SMEN : Low power UART 1 clocks enable during Sleep and Stop modes
bits : 0 - 0 (1 bit)

I2C4SMEN : I2C4 clocks enable during Sleep and Stop modes
bits : 1 - 1 (1 bit)

USBPDSMEN : USB PD clock enable during sleep mode
bits : 8 - 8 (1 bit)

SW : System clock switch
bits : 0 - 1 (2 bit)
access : read-write

SWS : System clock switch status
bits : 2 - 3 (2 bit)
access : read-only

HPRE : AHB prescaler
bits : 4 - 7 (4 bit)
access : read-write

PPRE1 : PB low-speed prescaler (APB1)
bits : 8 - 10 (3 bit)
access : read-write

PPRE2 : APB high-speed prescaler (APB2)
bits : 11 - 13 (3 bit)
access : read-write

MCOSEL : Microcontroller clock output
bits : 24 - 27 (4 bit)
access : read-write

MCOPRE : Microcontroller clock output prescaler
bits : 28 - 30 (3 bit)
access : read-write

SYSCFGSMEN : SYSCFG clocks enable during Sleep and Stop modes
bits : 0 - 0 (1 bit)

TIM1SMEN : TIM1 timer clocks enable during Sleep and Stop modes
bits : 11 - 11 (1 bit)

SPI1SMEN : SPI1 clocks enable during Sleep and Stop modes
bits : 12 - 12 (1 bit)

TIM8SMEN : TIM8 timer clocks enable during Sleep and Stop modes
bits : 13 - 13 (1 bit)

USART1SMEN : USART1clocks enable during Sleep and Stop modes
bits : 14 - 14 (1 bit)

SPI4SMEN : SPI4 timer clocks enable during Sleep and Stop modes
bits : 15 - 15 (1 bit)

TIM15SMEN : TIM15 timer clocks enable during Sleep and Stop modes
bits : 16 - 16 (1 bit)

TIM16SMEN : TIM16 timer clocks enable during Sleep and Stop modes
bits : 17 - 17 (1 bit)

TIM17SMEN : TIM17 timer clocks enable during Sleep and Stop modes
bits : 18 - 18 (1 bit)

TIM20SMEN : Timer 20clock enable during sleep mode
bits : 20 - 20 (1 bit)

SAI1SMEN : SAI1 clock enable during sleep mode
bits : 21 - 21 (1 bit)

HRTIMERSMEN : HRTIMER clock enable during sleep mode
bits : 26 - 26 (1 bit)

USART1SEL : USART1 clock source selection
bits : 0 - 1 (2 bit)

USART2SEL : USART2 clock source selection
bits : 2 - 3 (2 bit)

USART3SEL : USART3 clock source selection
bits : 4 - 5 (2 bit)

UART4SEL : UART4 clock source selection
bits : 6 - 7 (2 bit)

UART5SEL : UART5 clock source selection
bits : 8 - 9 (2 bit)

LPUART1SEL : LPUART1 clock source selection
bits : 10 - 11 (2 bit)

I2C1SEL : I2C1 clock source selection
bits : 12 - 13 (2 bit)

I2C2SEL : I2C2 clock source selection
bits : 14 - 15 (2 bit)

I2C3SEL : I2C3 clock source selection
bits : 16 - 17 (2 bit)

LPTIM1SEL : Low power timer 1 clock source selection
bits : 18 - 19 (2 bit)

SAISEL : Low power timer 2 clock source selection
bits : 20 - 21 (2 bit)

SPISEL_ : SAI1 clock source selection
bits : 22 - 23 (2 bit)

FDCANSEL : SAI2 clock source selection
bits : 24 - 25 (2 bit)

CLK48SEL : 48 MHz clock source selection
bits : 26 - 27 (2 bit)

ADCSEL : ADCs clock source selection
bits : 28 - 29 (2 bit)

ADC345SEL : ADC3/4/5 clock source selection
bits : 30 - 31 (2 bit)

LSEON : LSE oscillator enable
bits : 0 - 0 (1 bit)
access : read-write

LSERDY : LSE oscillator ready
bits : 1 - 1 (1 bit)
access : read-only

LSEBYP : LSE oscillator bypass
bits : 2 - 2 (1 bit)
access : read-write

LSEDRV : SE oscillator drive capability
bits : 3 - 4 (2 bit)
access : read-write

LSECSSON : LSECSSON
bits : 5 - 5 (1 bit)
access : read-write

LSECSSD : LSECSSD
bits : 6 - 6 (1 bit)
access : read-only

RTCSEL : RTC clock source selection
bits : 8 - 9 (2 bit)
access : read-write

RTCEN : RTC clock enable
bits : 15 - 15 (1 bit)
access : read-write

VSWRST : Vswitch domain software reset
bits : 16 - 16 (1 bit)
access : read-write

LSCCOEN : Low speed clock output enable
bits : 24 - 24 (1 bit)
access : read-write

LSCOSEL : Low speed clock output selection
bits : 25 - 25 (1 bit)
access : read-write

LSION : LSI oscillator enable
bits : 0 - 0 (1 bit)
access : read-write

LSIRDY : LSI oscillator ready
bits : 1 - 1 (1 bit)
access : read-only

RMVF : Remove reset flag
bits : 23 - 23 (1 bit)
access : read-write

OBLRSTF : Option byte loader reset flag
bits : 25 - 25 (1 bit)
access : read-only

PADRSTF : Pad reset flag
bits : 26 - 26 (1 bit)
access : read-only

BORRSTF : BOR flag
bits : 27 - 27 (1 bit)
access : read-only

SFTRSTF : Software reset flag
bits : 28 - 28 (1 bit)
access : read-only

WDGRSTF : Independent window watchdog reset flag
bits : 29 - 29 (1 bit)
access : read-only

WWDGRSTF : Window watchdog reset flag
bits : 30 - 30 (1 bit)
access : read-only

LPWRSTF : Low-power reset flag
bits : 31 - 31 (1 bit)
access : read-only

RC48ON : HSI48 clock enable
bits : 0 - 0 (1 bit)
access : read-write

RC48RDY : HSI48 clock ready flag
bits : 1 - 1 (1 bit)
access : read-only

RC48CAL : HSI48 clock calibration
bits : 7 - 15 (9 bit)
access : read-only

I2C4SEL : I2C4 clock source selection
bits : 0 - 1 (2 bit)

QUADSPISEL : Octospi clock source selection
bits : 20 - 21 (2 bit)

PLLSRC : Main PLL, PLLSAI1 and PLLSAI2 entry clock source
bits : 0 - 1 (2 bit)

PLLSYSM : Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock
bits : 4 - 7 (4 bit)

PLLSYSN : Main PLL multiplication factor for VCO
bits : 8 - 14 (7 bit)

PLLPEN : Main PLL PLLSAI3CLK output enable
bits : 16 - 16 (1 bit)

PLLSYSP : Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)
bits : 17 - 17 (1 bit)

PLLSYSQEN : Main PLL PLLUSB1CLK output enable
bits : 20 - 20 (1 bit)

PLLSYSQ : Main PLL division factor for PLLUSB1CLK(48 MHz clock)
bits : 21 - 22 (2 bit)

PLLSYSREN : Main PLL PLLCLK output enable
bits : 24 - 24 (1 bit)

PLLSYSR : Main PLL division factor for PLLCLK (system clock)
bits : 25 - 26 (2 bit)

PLLSYSPDIV : Main PLL division factor for PLLSAI2CLK
bits : 27 - 31 (5 bit)