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DMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ISR

CPAR1

CMAR1

CCR2

CNDTR2

CPAR2

CMAR2

CCR3

CNDTR3

CPAR3

CMAR3

IFCR

CCR4

CNDTR4

CPAR4

CMAR4

CCR5

CNDTR5

CPAR5

CMAR5

CCR6

CNDTR6

CPAR6

CMAR6

CCR1

CCR7

CNDTR7

CPAR7

CMAR7

CCR8

CNDTR8

CPAR8

CMAR8

CNDTR1


ISR

interrupt status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GIF1 TCIF1 HTIF1 TEIF1 GIF2 TCIF2 HTIF2 TEIF2 GIF3 TCIF3 HTIF3 TEIF3 GIF4 TCIF4 HTIF4 TEIF4 GIF5 TCIF5 HTIF5 TEIF5 GIF6 TCIF6 HTIF6 TEIF6 GIF7 TCIF7 HTIF7 TEIF7 GIF8 TCIF8 HTIF8 TEIF8

GIF1 : GIF1
bits : 0 - 0 (1 bit)

TCIF1 : TCIF1
bits : 1 - 1 (1 bit)

HTIF1 : HTIF1
bits : 2 - 2 (1 bit)

TEIF1 : TEIF1
bits : 3 - 3 (1 bit)

GIF2 : GIF2
bits : 4 - 4 (1 bit)

TCIF2 : TCIF2
bits : 5 - 5 (1 bit)

HTIF2 : HTIF2
bits : 6 - 6 (1 bit)

TEIF2 : TEIF2
bits : 7 - 7 (1 bit)

GIF3 : GIF3
bits : 8 - 8 (1 bit)

TCIF3 : TCIF3
bits : 9 - 9 (1 bit)

HTIF3 : HTIF3
bits : 10 - 10 (1 bit)

TEIF3 : TEIF3
bits : 11 - 11 (1 bit)

GIF4 : GIF4
bits : 12 - 12 (1 bit)

TCIF4 : TCIF4
bits : 13 - 13 (1 bit)

HTIF4 : HTIF4
bits : 14 - 14 (1 bit)

TEIF4 : TEIF4
bits : 15 - 15 (1 bit)

GIF5 : GIF5
bits : 16 - 16 (1 bit)

TCIF5 : TCIF5
bits : 17 - 17 (1 bit)

HTIF5 : HTIF5
bits : 18 - 18 (1 bit)

TEIF5 : TEIF5
bits : 19 - 19 (1 bit)

GIF6 : GIF6
bits : 20 - 20 (1 bit)

TCIF6 : TCIF6
bits : 21 - 21 (1 bit)

HTIF6 : HTIF6
bits : 22 - 22 (1 bit)

TEIF6 : TEIF6
bits : 23 - 23 (1 bit)

GIF7 : GIF7
bits : 24 - 24 (1 bit)

TCIF7 : TCIF7
bits : 25 - 25 (1 bit)

HTIF7 : HTIF7
bits : 26 - 26 (1 bit)

TEIF7 : TEIF7
bits : 27 - 27 (1 bit)

GIF8 : GIF8
bits : 28 - 28 (1 bit)

TCIF8 : TCIF8
bits : 29 - 29 (1 bit)

HTIF8 : HTIF8
bits : 30 - 30 (1 bit)

TEIF8 : TEIF8
bits : 31 - 31 (1 bit)


CPAR1

DMA channel x peripheral address register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPAR1 CPAR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


CMAR1

DMA channel x memory address register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMAR1 CMAR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory 1 address (used in case of Double buffer mode)
bits : 0 - 31 (32 bit)


CCR2

DMA channel 2 configuration register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR2 CCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM

EN : channel enable
bits : 0 - 0 (1 bit)

TCIE : TCIE
bits : 1 - 1 (1 bit)

HTIE : HTIE
bits : 2 - 2 (1 bit)

TEIE : TEIE
bits : 3 - 3 (1 bit)

DIR : DIR
bits : 4 - 4 (1 bit)

CIRC : CIRC
bits : 5 - 5 (1 bit)

PINC : PINC
bits : 6 - 6 (1 bit)

MINC : MINC
bits : 7 - 7 (1 bit)

PSIZE : PSIZE
bits : 8 - 9 (2 bit)

MSIZE : MSIZE
bits : 10 - 11 (2 bit)

PL : PL
bits : 12 - 13 (2 bit)

MEM2MEM : MEM2MEM
bits : 14 - 14 (1 bit)


CNDTR2

channel x number of data to transfer register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDTR2 CNDTR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data items to transfer
bits : 0 - 15 (16 bit)


CPAR2

DMA channel x peripheral address register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPAR2 CPAR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


CMAR2

DMA channel x memory address register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMAR2 CMAR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory 1 address (used in case of Double buffer mode)
bits : 0 - 31 (32 bit)


CCR3

DMA channel 3 configuration register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR3 CCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM

EN : channel enable
bits : 0 - 0 (1 bit)

TCIE : TCIE
bits : 1 - 1 (1 bit)

HTIE : HTIE
bits : 2 - 2 (1 bit)

TEIE : TEIE
bits : 3 - 3 (1 bit)

DIR : DIR
bits : 4 - 4 (1 bit)

CIRC : CIRC
bits : 5 - 5 (1 bit)

PINC : PINC
bits : 6 - 6 (1 bit)

MINC : MINC
bits : 7 - 7 (1 bit)

PSIZE : PSIZE
bits : 8 - 9 (2 bit)

MSIZE : MSIZE
bits : 10 - 11 (2 bit)

PL : PL
bits : 12 - 13 (2 bit)

MEM2MEM : MEM2MEM
bits : 14 - 14 (1 bit)


CNDTR3

channel x number of data to transfer register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDTR3 CNDTR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data items to transfer
bits : 0 - 15 (16 bit)


CPAR3

DMA channel x peripheral address register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPAR3 CPAR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


CMAR3

DMA channel x memory address register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMAR3 CMAR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory 1 address (used in case of Double buffer mode)
bits : 0 - 31 (32 bit)


IFCR

DMA interrupt flag clear register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFCR IFCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GIF1 TCIF1 HTIF1 TEIF1 GIF2 TCIF2 HTIF2 TEIF2 GIF3 TCIF3 HTIF3 TEIF3 GIF4 TCIF4 HTIF4 TEIF4 GIF5 TCIF5 HTIF5 TEIF5 GIF6 TCIF6 HTIF6 TEIF6 GIF7 TCIF7 HTIF7 TEIF7 GIF8 TCIF8 HTIF8 TEIF8

GIF1 : GIF1
bits : 0 - 0 (1 bit)

TCIF1 : TCIF1
bits : 1 - 1 (1 bit)

HTIF1 : HTIF1
bits : 2 - 2 (1 bit)

TEIF1 : TEIF1
bits : 3 - 3 (1 bit)

GIF2 : GIF2
bits : 4 - 4 (1 bit)

TCIF2 : TCIF2
bits : 5 - 5 (1 bit)

HTIF2 : HTIF2
bits : 6 - 6 (1 bit)

TEIF2 : TEIF2
bits : 7 - 7 (1 bit)

GIF3 : GIF3
bits : 8 - 8 (1 bit)

TCIF3 : TCIF3
bits : 9 - 9 (1 bit)

HTIF3 : HTIF3
bits : 10 - 10 (1 bit)

TEIF3 : TEIF3
bits : 11 - 11 (1 bit)

GIF4 : GIF4
bits : 12 - 12 (1 bit)

TCIF4 : TCIF4
bits : 13 - 13 (1 bit)

HTIF4 : HTIF4
bits : 14 - 14 (1 bit)

TEIF4 : TEIF4
bits : 15 - 15 (1 bit)

GIF5 : GIF5
bits : 16 - 16 (1 bit)

TCIF5 : TCIF5
bits : 17 - 17 (1 bit)

HTIF5 : HTIF5
bits : 18 - 18 (1 bit)

TEIF5 : TEIF5
bits : 19 - 19 (1 bit)

GIF6 : GIF6
bits : 20 - 20 (1 bit)

TCIF6 : TCIF6
bits : 21 - 21 (1 bit)

HTIF6 : HTIF6
bits : 22 - 22 (1 bit)

TEIF6 : TEIF6
bits : 23 - 23 (1 bit)

GIF7 : GIF7
bits : 24 - 24 (1 bit)

TCIF7 : TCIF7
bits : 25 - 25 (1 bit)

HTIF7 : HTIF7
bits : 26 - 26 (1 bit)

TEIF7 : TEIF7
bits : 27 - 27 (1 bit)

GIF8 : GIF8
bits : 28 - 28 (1 bit)

TCIF8 : TCIF8
bits : 29 - 29 (1 bit)

HTIF8 : HTIF8
bits : 30 - 30 (1 bit)

TEIF8 : TEIF8
bits : 31 - 31 (1 bit)


CCR4

DMA channel 3 configuration register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR4 CCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM

EN : channel enable
bits : 0 - 0 (1 bit)

TCIE : TCIE
bits : 1 - 1 (1 bit)

HTIE : HTIE
bits : 2 - 2 (1 bit)

TEIE : TEIE
bits : 3 - 3 (1 bit)

DIR : DIR
bits : 4 - 4 (1 bit)

CIRC : CIRC
bits : 5 - 5 (1 bit)

PINC : PINC
bits : 6 - 6 (1 bit)

MINC : MINC
bits : 7 - 7 (1 bit)

PSIZE : PSIZE
bits : 8 - 9 (2 bit)

MSIZE : MSIZE
bits : 10 - 11 (2 bit)

PL : PL
bits : 12 - 13 (2 bit)

MEM2MEM : MEM2MEM
bits : 14 - 14 (1 bit)


CNDTR4

channel x number of data to transfer register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDTR4 CNDTR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data items to transfer
bits : 0 - 15 (16 bit)


CPAR4

DMA channel x peripheral address register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPAR4 CPAR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


CMAR4

DMA channel x memory address register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMAR4 CMAR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory 1 address (used in case of Double buffer mode)
bits : 0 - 31 (32 bit)


CCR5

DMA channel 4 configuration register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR5 CCR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM

EN : channel enable
bits : 0 - 0 (1 bit)

TCIE : TCIE
bits : 1 - 1 (1 bit)

HTIE : HTIE
bits : 2 - 2 (1 bit)

TEIE : TEIE
bits : 3 - 3 (1 bit)

DIR : DIR
bits : 4 - 4 (1 bit)

CIRC : CIRC
bits : 5 - 5 (1 bit)

PINC : PINC
bits : 6 - 6 (1 bit)

MINC : MINC
bits : 7 - 7 (1 bit)

PSIZE : PSIZE
bits : 8 - 9 (2 bit)

MSIZE : MSIZE
bits : 10 - 11 (2 bit)

PL : PL
bits : 12 - 13 (2 bit)

MEM2MEM : MEM2MEM
bits : 14 - 14 (1 bit)


CNDTR5

channel x number of data to transfer register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDTR5 CNDTR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data items to transfer
bits : 0 - 15 (16 bit)


CPAR5

DMA channel x peripheral address register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPAR5 CPAR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


CMAR5

DMA channel x memory address register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMAR5 CMAR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory 1 address (used in case of Double buffer mode)
bits : 0 - 31 (32 bit)


CCR6

DMA channel 5 configuration register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR6 CCR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM

EN : channel enable
bits : 0 - 0 (1 bit)

TCIE : TCIE
bits : 1 - 1 (1 bit)

HTIE : HTIE
bits : 2 - 2 (1 bit)

TEIE : TEIE
bits : 3 - 3 (1 bit)

DIR : DIR
bits : 4 - 4 (1 bit)

CIRC : CIRC
bits : 5 - 5 (1 bit)

PINC : PINC
bits : 6 - 6 (1 bit)

MINC : MINC
bits : 7 - 7 (1 bit)

PSIZE : PSIZE
bits : 8 - 9 (2 bit)

MSIZE : MSIZE
bits : 10 - 11 (2 bit)

PL : PL
bits : 12 - 13 (2 bit)

MEM2MEM : MEM2MEM
bits : 14 - 14 (1 bit)


CNDTR6

channel x number of data to transfer register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDTR6 CNDTR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data items to transfer
bits : 0 - 15 (16 bit)


CPAR6

DMA channel x peripheral address register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPAR6 CPAR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


CMAR6

DMA channel x memory address register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMAR6 CMAR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory 1 address (used in case of Double buffer mode)
bits : 0 - 31 (32 bit)


CCR1

DMA channel 1 configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR1 CCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM

EN : channel enable
bits : 0 - 0 (1 bit)

TCIE : TCIE
bits : 1 - 1 (1 bit)

HTIE : HTIE
bits : 2 - 2 (1 bit)

TEIE : TEIE
bits : 3 - 3 (1 bit)

DIR : DIR
bits : 4 - 4 (1 bit)

CIRC : CIRC
bits : 5 - 5 (1 bit)

PINC : PINC
bits : 6 - 6 (1 bit)

MINC : MINC
bits : 7 - 7 (1 bit)

PSIZE : PSIZE
bits : 8 - 9 (2 bit)

MSIZE : MSIZE
bits : 10 - 11 (2 bit)

PL : PL
bits : 12 - 13 (2 bit)

MEM2MEM : MEM2MEM
bits : 14 - 14 (1 bit)


CCR7

DMA channel 6 configuration register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR7 CCR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM

EN : channel enable
bits : 0 - 0 (1 bit)

TCIE : TCIE
bits : 1 - 1 (1 bit)

HTIE : HTIE
bits : 2 - 2 (1 bit)

TEIE : TEIE
bits : 3 - 3 (1 bit)

DIR : DIR
bits : 4 - 4 (1 bit)

CIRC : CIRC
bits : 5 - 5 (1 bit)

PINC : PINC
bits : 6 - 6 (1 bit)

MINC : MINC
bits : 7 - 7 (1 bit)

PSIZE : PSIZE
bits : 8 - 9 (2 bit)

MSIZE : MSIZE
bits : 10 - 11 (2 bit)

PL : PL
bits : 12 - 13 (2 bit)

MEM2MEM : MEM2MEM
bits : 14 - 14 (1 bit)


CNDTR7

channel x number of data to transfer register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDTR7 CNDTR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data items to transfer
bits : 0 - 15 (16 bit)


CPAR7

DMA channel x peripheral address register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPAR7 CPAR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


CMAR7

DMA channel x memory address register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMAR7 CMAR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory 1 address (used in case of Double buffer mode)
bits : 0 - 31 (32 bit)


CCR8

DMA channel 7 configuration register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR8 CCR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM

EN : channel enable
bits : 0 - 0 (1 bit)

TCIE : TCIE
bits : 1 - 1 (1 bit)

HTIE : HTIE
bits : 2 - 2 (1 bit)

TEIE : TEIE
bits : 3 - 3 (1 bit)

DIR : DIR
bits : 4 - 4 (1 bit)

CIRC : CIRC
bits : 5 - 5 (1 bit)

PINC : PINC
bits : 6 - 6 (1 bit)

MINC : MINC
bits : 7 - 7 (1 bit)

PSIZE : PSIZE
bits : 8 - 9 (2 bit)

MSIZE : MSIZE
bits : 10 - 11 (2 bit)

PL : PL
bits : 12 - 13 (2 bit)

MEM2MEM : MEM2MEM
bits : 14 - 14 (1 bit)


CNDTR8

channel x number of data to transfer register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDTR8 CNDTR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data items to transfer
bits : 0 - 15 (16 bit)


CPAR8

DMA channel x peripheral address register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPAR8 CPAR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


CMAR8

DMA channel x memory address register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMAR8 CMAR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory 1 address (used in case of Double buffer mode)
bits : 0 - 31 (32 bit)


CNDTR1

channel x number of data to transfer register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDTR1 CNDTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data items to transfer
bits : 0 - 15 (16 bit)



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