\n

VREFBUF

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1D0 byte (0x0)
mem_usage : registers
protection : not protected

Registers

VREFBUF_CSR (CSR)

VREFBUF_CCR (CCR)


VREFBUF_CSR (CSR)

VREF_BUF Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREFBUF_CSR VREFBUF_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENVR HIZ VRR VRS

ENVR : Enable Voltage Reference
bits : 0 - 0 (1 bit)
access : read-write

HIZ : High impedence mode for the VREF_BUF
bits : 1 - 1 (1 bit)
access : read-write

VRR : Voltage reference buffer ready
bits : 3 - 3 (1 bit)
access : read-only

VRS : Voltage reference scale
bits : 4 - 5 (2 bit)
access : read-write


VREFBUF_CCR (CCR)

VREF_BUF Calibration Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREFBUF_CCR VREFBUF_CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIM

TRIM : Trimming code
bits : 0 - 5 (6 bit)



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