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COMP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

COMP_C1CSR (C1CSR)

COMP_C4CSR (C4CSR)

COMP_C2CSR (C2CSR)

COMP_C3CSR (C3CSR)


COMP_C1CSR (C1CSR)

Comparator control/status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP_C1CSR COMP_C1CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN COMP_DEGLITCH_EN INMSEL INPSEL POL HYST BLANKSEL BRGEN SCALEN VALUE LOCK

EN : EN
bits : 0 - 0 (1 bit)
access : read-write

COMP_DEGLITCH_EN : COMP_DEGLITCH_EN
bits : 1 - 1 (1 bit)
access : read-write

INMSEL : INMSEL
bits : 4 - 6 (3 bit)
access : read-write

INPSEL : INPSEL
bits : 8 - 8 (1 bit)
access : read-write

POL : POL
bits : 15 - 15 (1 bit)
access : read-write

HYST : HYST
bits : 16 - 18 (3 bit)
access : read-write

BLANKSEL : BLANKSEL
bits : 19 - 21 (3 bit)
access : read-write

BRGEN : BRGEN
bits : 22 - 22 (1 bit)
access : read-write

SCALEN : SCALEN
bits : 23 - 23 (1 bit)
access : read-write

VALUE : VALUE
bits : 30 - 30 (1 bit)
access : read-only

LOCK : LOCK
bits : 31 - 31 (1 bit)
access : read-write


COMP_C4CSR (C4CSR)

Comparator control/status register
address_offset : 0x12 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP_C4CSR COMP_C4CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN COMP_DEGLITCH_EN INMSEL INPSEL POL HYST BLANKSEL BRGEN SCALEN VALUE LOCK

EN : EN
bits : 0 - 0 (1 bit)
access : read-write

COMP_DEGLITCH_EN : COMP_DEGLITCH_EN
bits : 1 - 1 (1 bit)
access : read-write

INMSEL : INMSEL
bits : 4 - 6 (3 bit)
access : read-write

INPSEL : INPSEL
bits : 8 - 8 (1 bit)
access : read-write

POL : POL
bits : 15 - 15 (1 bit)
access : read-write

HYST : HYST
bits : 16 - 18 (3 bit)
access : read-write

BLANKSEL : BLANKSEL
bits : 19 - 21 (3 bit)
access : read-write

BRGEN : BRGEN
bits : 22 - 22 (1 bit)
access : read-write

SCALEN : SCALEN
bits : 23 - 23 (1 bit)
access : read-write

VALUE : VALUE
bits : 30 - 30 (1 bit)
access : read-only

LOCK : LOCK
bits : 31 - 31 (1 bit)
access : read-write


COMP_C2CSR (C2CSR)

Comparator control/status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP_C2CSR COMP_C2CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN COMP_DEGLITCH_EN INMSEL INPSEL POL HYST BLANKSEL BRGEN SCALEN VALUE LOCK

EN : EN
bits : 0 - 0 (1 bit)
access : read-write

COMP_DEGLITCH_EN : COMP_DEGLITCH_EN
bits : 1 - 1 (1 bit)
access : read-write

INMSEL : INMSEL
bits : 4 - 6 (3 bit)
access : read-write

INPSEL : INPSEL
bits : 8 - 8 (1 bit)
access : read-write

POL : POL
bits : 15 - 15 (1 bit)
access : read-write

HYST : HYST
bits : 16 - 18 (3 bit)
access : read-write

BLANKSEL : BLANKSEL
bits : 19 - 21 (3 bit)
access : read-write

BRGEN : BRGEN
bits : 22 - 22 (1 bit)
access : read-write

SCALEN : SCALEN
bits : 23 - 23 (1 bit)
access : read-write

VALUE : VALUE
bits : 30 - 30 (1 bit)
access : read-only

LOCK : LOCK
bits : 31 - 31 (1 bit)
access : read-write


COMP_C3CSR (C3CSR)

Comparator control/status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP_C3CSR COMP_C3CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN COMP_DEGLITCH_EN INMSEL INPSEL POL HYST BLANKSEL BRGEN SCALEN VALUE LOCK

EN : EN
bits : 0 - 0 (1 bit)
access : read-write

COMP_DEGLITCH_EN : COMP_DEGLITCH_EN
bits : 1 - 1 (1 bit)
access : read-write

INMSEL : INMSEL
bits : 4 - 6 (3 bit)
access : read-write

INPSEL : INPSEL
bits : 8 - 8 (1 bit)
access : read-write

POL : POL
bits : 15 - 15 (1 bit)
access : read-write

HYST : HYST
bits : 16 - 18 (3 bit)
access : read-write

BLANKSEL : BLANKSEL
bits : 19 - 21 (3 bit)
access : read-write

BRGEN : BRGEN
bits : 22 - 22 (1 bit)
access : read-write

SCALEN : SCALEN
bits : 23 - 23 (1 bit)
access : read-write

VALUE : VALUE
bits : 30 - 30 (1 bit)
access : read-only

LOCK : LOCK
bits : 31 - 31 (1 bit)
access : read-write



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