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EXBUS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x300 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MODE0

MODE6

MODE7

TIM0

TIM1

DCLKR

TIM6

TIM7

MODE1

AREA0

AREA1

AREA6

AREA7

ATIM0

ATIM1

ATIM6

ATIM7


MODE0

Mode Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE0 MODE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTH RBMON WEOFF NAND PAGE RDY SHRTDOUT MPXMODE ALEINV MPXDOFF MPXCSOF MOEXEUP

WDTH : specify Data Width
bits : 0 - 0 (1 bit)
access : read-write

RBMON : Read Byte Mask ON
bits : 2 - 1 (0 bit)
access : read-write

WEOFF : disable the write enable signal (MWEX) operation
bits : 3 - 2 (0 bit)
access : read-write

NAND : NAND Flash memory mode
bits : 4 - 3 (0 bit)
access : read-write

PAGE : NOR Flash memory page access mode
bits : 5 - 4 (0 bit)
access : read-write

RDY : control the external RDY function
bits : 6 - 5 (0 bit)
access : read-write

SHRTDOUT : select to which idle cycle the write data output is extended
bits : 7 - 6 (0 bit)
access : read-write

MPXMODE : select operation bus mode
bits : 8 - 7 (0 bit)
access : read-write

ALEINV : set up the polarity of the ALE signal
bits : 9 - 8 (0 bit)
access : read-write

MPXDOFF : select whether or not the address is output to the data lines in multiplex mode
bits : 11 - 10 (0 bit)
access : read-write

MPXCSOF : select a CS assertion from the start of accessing to the end of address output
bits : 12 - 11 (0 bit)
access : read-write

MOEXEUP : select how to set the MOEX width
bits : 13 - 12 (0 bit)
access : read-write


MODE6

Mode Register 6
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE6 MODE6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MODE7

Mode Register 7
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE7 MODE7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM0

Timing Register 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM0 TIM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RACC RADC FRADC RIDLC WACC WADC WWEC WIDLC

RACC : Read Access Cycle
bits : 0 - 2 (3 bit)
access : read-write

RADC : Read Address Setup cycle
bits : 4 - 6 (3 bit)
access : read-write

FRADC : First Read Address Cycle
bits : 8 - 10 (3 bit)
access : read-write

RIDLC : Read Idle Cycle
bits : 12 - 14 (3 bit)
access : read-write

WACC : Write Access Cycle
bits : 16 - 18 (3 bit)
access : read-write

WADC : Write Address Setup cycle
bits : 20 - 22 (3 bit)
access : read-write

WWEC : Write Enable Cycle
bits : 24 - 26 (3 bit)
access : read-write

WIDLC : Write Idle Cycle
bits : 28 - 30 (3 bit)
access : read-write


TIM1

Timing Register 1
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM1 TIM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DCLKR

Division Clock Register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCLKR DCLKR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDIV MCLKON

MDIV : MCLK Division Ratio Setup
bits : 0 - 2 (3 bit)
access : read-write

MCLKON : MCLK ON
bits : 4 - 3 (0 bit)
access : read-write


TIM6

Timing Register 6
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM6 TIM6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM7

Timing Register 7
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM7 TIM7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MODE1

Mode Register 1
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE1 MODE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AREA0

Area Register 0
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AREA0 AREA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR MASK

ADDR : Address
bits : 0 - 6 (7 bit)
access : read-write

MASK : address mask
bits : 16 - 21 (6 bit)
access : read-write


AREA1

Area Register 1
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AREA1 AREA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR MASK

ADDR : Address
bits : 0 - 6 (7 bit)
access : read-write

MASK : address mask
bits : 16 - 21 (6 bit)
access : read-write


AREA6

Area Register 6
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AREA6 AREA6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR MASK

ADDR : Address
bits : 0 - 6 (7 bit)
access : read-write

MASK : address mask
bits : 16 - 21 (6 bit)
access : read-write


AREA7

Area Register 7
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AREA7 AREA7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR MASK

ADDR : Address
bits : 0 - 6 (7 bit)
access : read-write

MASK : address mask
bits : 16 - 21 (6 bit)
access : read-write


ATIM0

ALE Timing Register 0
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ATIM0 ATIM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALC ALES ALEW

ALC : Address Latch Cycle
bits : 0 - 2 (3 bit)
access : read-write

ALES : Address Latch Enable Setup cycle
bits : 4 - 6 (3 bit)
access : read-write

ALEW : Address Latch Enable Width
bits : 8 - 10 (3 bit)
access : read-write


ATIM1

ALE Timing Register 1
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ATIM1 ATIM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ATIM6

ALE Timing Register 6
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ATIM6 ATIM6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ATIM7

ALE Timing Register 7
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ATIM7 ATIM7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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