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OPAMP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

OPAMP1_CSR

OPAMP1_TCMR

OPAMP2_TCMR

OPAMP3_TCMR

OPAMP2_CSR

OPAMP3_CSR


OPAMP1_CSR

OPAMP1 control/status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPAMP1_CSR OPAMP1_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPAEN FORCE_VP VP_SEL USERTRIM VM_SEL OPAHSM OPAINTOEN CALON CALSEL PGA_GAIN TRIMOFFSETP TRIMOFFSETN CALOUT LOCK

OPAEN : Operational amplifier Enable
bits : 0 - 0 (1 bit)

FORCE_VP : FORCE_VP
bits : 1 - 1 (1 bit)

VP_SEL : VP_SEL
bits : 2 - 3 (2 bit)

USERTRIM : USERTRIM
bits : 4 - 4 (1 bit)

VM_SEL : VM_SEL
bits : 5 - 6 (2 bit)

OPAHSM : OPAHSM
bits : 7 - 7 (1 bit)

OPAINTOEN : OPAINTOEN
bits : 8 - 8 (1 bit)

CALON : CALON
bits : 11 - 11 (1 bit)

CALSEL : CALSEL
bits : 12 - 13 (2 bit)

PGA_GAIN : PGA_GAIN
bits : 14 - 18 (5 bit)

TRIMOFFSETP : TRIMOFFSETP
bits : 19 - 23 (5 bit)

TRIMOFFSETN : TRIMOFFSETN
bits : 24 - 28 (5 bit)

CALOUT : CALOUT
bits : 30 - 30 (1 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


OPAMP1_TCMR

OPAMP1 control/status register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPAMP1_TCMR OPAMP1_TCMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VMS_SEL VPS_SEL T1CM_EN T8CM_EN T20CM_EN LOCK

VMS_SEL : VMS_SEL
bits : 0 - 0 (1 bit)

VPS_SEL : VPS_SEL
bits : 1 - 2 (2 bit)

T1CM_EN : T1CM_EN
bits : 3 - 3 (1 bit)

T8CM_EN : T8CM_EN
bits : 4 - 4 (1 bit)

T20CM_EN : T20CM_EN
bits : 5 - 5 (1 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


OPAMP2_TCMR

OPAMP2 control/status register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPAMP2_TCMR OPAMP2_TCMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VMS_SEL VPS_SEL T1CM_EN T8CM_EN T20CM_EN LOCK

VMS_SEL : VMS_SEL
bits : 0 - 0 (1 bit)

VPS_SEL : VPS_SEL
bits : 1 - 2 (2 bit)

T1CM_EN : T1CM_EN
bits : 3 - 3 (1 bit)

T8CM_EN : T8CM_EN
bits : 4 - 4 (1 bit)

T20CM_EN : T20CM_EN
bits : 5 - 5 (1 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


OPAMP3_TCMR

OPAMP3 control/status register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPAMP3_TCMR OPAMP3_TCMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VMS_SEL VPS_SEL T1CM_EN T8CM_EN T20CM_EN LOCK

VMS_SEL : VMS_SEL
bits : 0 - 0 (1 bit)

VPS_SEL : VPS_SEL
bits : 1 - 2 (2 bit)

T1CM_EN : T1CM_EN
bits : 3 - 3 (1 bit)

T8CM_EN : T8CM_EN
bits : 4 - 4 (1 bit)

T20CM_EN : T20CM_EN
bits : 5 - 5 (1 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


OPAMP2_CSR

OPAMP2 control/status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPAMP2_CSR OPAMP2_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPAEN FORCE_VP VP_SEL USERTRIM VM_SEL OPAHSM OPAINTOEN CALON CALSEL PGA_GAIN TRIMOFFSETP TRIMOFFSETN CALOUT LOCK

OPAEN : Operational amplifier Enable
bits : 0 - 0 (1 bit)

FORCE_VP : FORCE_VP
bits : 1 - 1 (1 bit)

VP_SEL : VP_SEL
bits : 2 - 3 (2 bit)

USERTRIM : USERTRIM
bits : 4 - 4 (1 bit)

VM_SEL : VM_SEL
bits : 5 - 6 (2 bit)

OPAHSM : OPAHSM
bits : 7 - 7 (1 bit)

OPAINTOEN : OPAINTOEN
bits : 8 - 8 (1 bit)

CALON : CALON
bits : 11 - 11 (1 bit)

CALSEL : CALSEL
bits : 12 - 13 (2 bit)

PGA_GAIN : PGA_GAIN
bits : 14 - 18 (5 bit)

TRIMOFFSETP : TRIMOFFSETP
bits : 19 - 23 (5 bit)

TRIMOFFSETN : TRIMOFFSETN
bits : 24 - 28 (5 bit)

CALOUT : CALOUT
bits : 30 - 30 (1 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)


OPAMP3_CSR

OPAMP3 control/status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPAMP3_CSR OPAMP3_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPAEN FORCE_VP VP_SEL USERTRIM VM_SEL OPAHSM OPAINTOEN CALON CALSEL PGA_GAIN TRIMOFFSETP TRIMOFFSETN CALOUT LOCK

OPAEN : Operational amplifier Enable
bits : 0 - 0 (1 bit)

FORCE_VP : FORCE_VP
bits : 1 - 1 (1 bit)

VP_SEL : VP_SEL
bits : 2 - 3 (2 bit)

USERTRIM : USERTRIM
bits : 4 - 4 (1 bit)

VM_SEL : VM_SEL
bits : 5 - 6 (2 bit)

OPAHSM : OPAHSM
bits : 7 - 7 (1 bit)

OPAINTOEN : OPAINTOEN
bits : 8 - 8 (1 bit)

CALON : CALON
bits : 11 - 11 (1 bit)

CALSEL : CALSEL
bits : 12 - 13 (2 bit)

PGA_GAIN : PGA_GAIN
bits : 14 - 18 (5 bit)

TRIMOFFSETP : TRIMOFFSETP
bits : 19 - 23 (5 bit)

TRIMOFFSETN : TRIMOFFSETN
bits : 24 - 28 (5 bit)

CALOUT : CALOUT
bits : 30 - 30 (1 bit)

LOCK : LOCK
bits : 31 - 31 (1 bit)



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