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DAC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DAC_CR

DAC_DHR8R1

DAC_DHR12R2

DAC_DHR12L2

DAC_DHR8R2

DAC_DHR12RD

DAC_DHR12LD

DAC_DHR8RD

DAC_DOR1

DAC_DOR2

DAC_SR

DAC_CCR

DAC_MCR

DAC_SWTRGR

DAC_SHSR1

DAC_SHSR2

DAC_SHHR

DAC_SHRR

DAC_STR1

DAC_STR2

DAC_STMODR

DAC_DHR12R1

DAC_DHR12L1


DAC_CR

DAC control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_CR DAC_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN1 TEN1 TSEL1 WAVE1 MAMP1 DMAEN1 DMAUDRIE1 CEN1 EN2 TEN2 TSEL2 WAVE2 MAMP2 DMAEN2 DMAUDRIE2 CEN2

EN1 : DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1.
bits : 0 - 0 (1 bit)

TEN1 : DAC channel1 trigger enable
bits : 1 - 1 (1 bit)

TSEL1 : DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).
bits : 2 - 5 (4 bit)

WAVE1 : DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).
bits : 6 - 7 (2 bit)

MAMP1 : DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
bits : 8 - 11 (4 bit)

DMAEN1 : DAC channel1 DMA enable This bit is set and cleared by software.
bits : 12 - 12 (1 bit)

DMAUDRIE1 : DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software.
bits : 13 - 13 (1 bit)

CEN1 : DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored.
bits : 14 - 14 (1 bit)

EN2 : DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2.
bits : 16 - 16 (1 bit)

TEN2 : DAC channel2 trigger enable
bits : 17 - 17 (1 bit)

TSEL2 : DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled).
bits : 18 - 21 (4 bit)

WAVE2 : DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
bits : 22 - 23 (2 bit)

MAMP2 : DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
bits : 24 - 27 (4 bit)

DMAEN2 : DAC channel2 DMA enable This bit is set and cleared by software.
bits : 28 - 28 (1 bit)

DMAUDRIE2 : DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software.
bits : 29 - 29 (1 bit)

CEN2 : DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration, it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored.
bits : 30 - 30 (1 bit)


DAC_DHR8R1

DAC channel1 8-bit right aligned data holding register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_DHR8R1 DAC_DHR8R1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC1DHR DACC1DHRB

DACC1DHR : DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1.
bits : 0 - 7 (8 bit)

DACC1DHRB : DAC channel1 8-bit right-aligned data
bits : 8 - 15 (8 bit)


DAC_DHR12R2

DAC channel2 12-bit right aligned data holding register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_DHR12R2 DAC_DHR12R2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC2DHR DACC2DHRB

DACC2DHR : DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.
bits : 0 - 11 (12 bit)

DACC2DHRB : DAC channel2 12-bit right-aligned data
bits : 16 - 27 (12 bit)


DAC_DHR12L2

DAC channel2 12-bit left aligned data holding register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_DHR12L2 DAC_DHR12L2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC2DHR DACC2DHRB

DACC2DHR : DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2.
bits : 4 - 15 (12 bit)

DACC2DHRB : DAC channel2 12-bit left-aligned data B
bits : 20 - 31 (12 bit)


DAC_DHR8R2

DAC channel2 8-bit right-aligned data holding register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_DHR8R2 DAC_DHR8R2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC2DHR DACC2DHRB

DACC2DHR : DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.
bits : 0 - 7 (8 bit)

DACC2DHRB : DAC channel2 8-bit right-aligned data
bits : 8 - 15 (8 bit)


DAC_DHR12RD

Dual DAC 12-bit right-aligned data holding register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_DHR12RD DAC_DHR12RD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC1DHR DACC2DHR

DACC1DHR : DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.
bits : 0 - 11 (12 bit)

DACC2DHR : DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.
bits : 16 - 27 (12 bit)


DAC_DHR12LD

DUAL DAC 12-bit left aligned data holding register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_DHR12LD DAC_DHR12LD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC1DHR DACC2DHR

DACC1DHR : DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.
bits : 4 - 15 (12 bit)

DACC2DHR : DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.
bits : 20 - 31 (12 bit)


DAC_DHR8RD

DUAL DAC 8-bit right aligned data holding register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_DHR8RD DAC_DHR8RD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC1DHR DACC2DHR

DACC1DHR : DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1.
bits : 0 - 7 (8 bit)

DACC2DHR : DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.
bits : 8 - 15 (8 bit)


DAC_DOR1

DAC channel1 data output register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DAC_DOR1 DAC_DOR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC1DOR DACC1DORB

DACC1DOR : DAC channel1 data output These bits are read-only, they contain data output for DAC channel1.
bits : 0 - 11 (12 bit)

DACC1DORB : DAC channel1 data output
bits : 16 - 27 (12 bit)


DAC_DOR2

DAC channel2 data output register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DAC_DOR2 DAC_DOR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC2DOR DACC2DORB

DACC2DOR : DAC channel2 data output These bits are read-only, they contain data output for DAC channel2.
bits : 0 - 11 (12 bit)

DACC2DORB : DAC channel2 data output
bits : 16 - 27 (12 bit)


DAC_SR

DAC status register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_SR DAC_SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAC1RDY DORSTAT1 DMAUDR1 CAL_FLAG1 BWST1 DAC2RDY DORSTAT2 DMAUDR2 CAL_FLAG2 BWST2

DAC1RDY : DAC channel1 ready status bit
bits : 11 - 11 (1 bit)
access : read-write

DORSTAT1 : DAC channel1 output register status bit
bits : 12 - 12 (1 bit)
access : read-write

DMAUDR1 : DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).
bits : 13 - 13 (1 bit)
access : read-write

CAL_FLAG1 : DAC Channel 1 calibration offset status This bit is set and cleared by hardware
bits : 14 - 14 (1 bit)
access : read-only

BWST1 : DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3LSI periods of synchronization).
bits : 15 - 15 (1 bit)
access : read-only

DAC2RDY : DAC channel 2 ready status bit
bits : 27 - 27 (1 bit)
access : read-write

DORSTAT2 : DAC channel 2 output register status bit
bits : 28 - 28 (1 bit)
access : read-write

DMAUDR2 : DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).
bits : 29 - 29 (1 bit)
access : read-write

CAL_FLAG2 : DAC Channel 2 calibration offset status This bit is set and cleared by hardware
bits : 30 - 30 (1 bit)
access : read-only

BWST2 : DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization).
bits : 31 - 31 (1 bit)
access : read-only


DAC_CCR

DAC calibration control register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_CCR DAC_CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTRIM1 OTRIM2

OTRIM1 : DAC Channel 1 offset trimming value
bits : 0 - 4 (5 bit)

OTRIM2 : DAC Channel 2 offset trimming value
bits : 16 - 20 (5 bit)


DAC_MCR

DAC mode control register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_MCR DAC_MCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE1 DMADOUBLE1 SINFORMAT1 HFSEL MODE2 DMADOUBLE2 SINFORMAT2

MODE1 : DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 1 mode: DAC Channel 1 in normal Mode DAC Channel 1 in sample & hold mode
bits : 0 - 2 (3 bit)

DMADOUBLE1 : DAC Channel1 DMA double data mode
bits : 8 - 8 (1 bit)

SINFORMAT1 : Enable signed format for DAC channel1
bits : 9 - 9 (1 bit)

HFSEL : High frequency interface mode selection
bits : 14 - 15 (2 bit)

MODE2 : DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 2 mode: DAC Channel 2 in normal Mode DAC Channel 2 in sample & hold mode
bits : 16 - 18 (3 bit)

DMADOUBLE2 : DAC Channel2 DMA double data mode
bits : 24 - 24 (1 bit)

SINFORMAT2 : Enable signed format for DAC channel2
bits : 25 - 25 (1 bit)


DAC_SWTRGR

DAC software trigger register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DAC_SWTRGR DAC_SWTRGR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWTRIG1 SWTRIG2 SWTRIGB1 SWTRIGB2

SWTRIG1 : DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register.
bits : 0 - 0 (1 bit)

SWTRIG2 : DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register.
bits : 1 - 1 (1 bit)

SWTRIGB1 : DAC channel1 software trigger B
bits : 16 - 16 (1 bit)

SWTRIGB2 : DAC channel2 software trigger B
bits : 17 - 17 (1 bit)


DAC_SHSR1

DAC Sample and Hold sample time register 1
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_SHSR1 DAC_SHSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSAMPLE1

TSAMPLE1 : DAC Channel 1 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored.
bits : 0 - 9 (10 bit)


DAC_SHSR2

DAC Sample and Hold sample time register 2
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_SHSR2 DAC_SHSR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSAMPLE2

TSAMPLE2 : DAC Channel 2 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, if BWSTx=1, the write operation is ignored.
bits : 0 - 9 (10 bit)


DAC_SHHR

DAC Sample and Hold hold time register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_SHHR DAC_SHHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 THOLD1 THOLD2

THOLD1 : DAC Channel 1 hold Time (only valid in sample & hold mode) Hold time= (THOLD[9:0]) x T LSI
bits : 0 - 9 (10 bit)

THOLD2 : DAC Channel 2 hold time (only valid in sample & hold mode). Hold time= (THOLD[9:0]) x T LSI
bits : 16 - 25 (10 bit)


DAC_SHRR

DAC Sample and Hold refresh time register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_SHRR DAC_SHRR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TREFRESH1 TREFRESH2

TREFRESH1 : DAC Channel 1 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI
bits : 0 - 7 (8 bit)

TREFRESH2 : DAC Channel 2 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI
bits : 16 - 23 (8 bit)


DAC_STR1

Sawtooth register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_STR1 DAC_STR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STRSTDATA1 STDIR1 STINCDATA1

STRSTDATA1 : DAC Channel 1 Sawtooth reset value
bits : 0 - 11 (12 bit)

STDIR1 : DAC Channel1 Sawtooth direction setting
bits : 12 - 12 (1 bit)

STINCDATA1 : DAC CH1 Sawtooth increment value (12.4 bit format)
bits : 16 - 31 (16 bit)


DAC_STR2

Sawtooth register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_STR2 DAC_STR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STRSTDATA2 STDIR2 STINCDATA2

STRSTDATA2 : DAC Channel 2 Sawtooth reset value
bits : 0 - 11 (12 bit)

STDIR2 : DAC Channel2 Sawtooth direction setting
bits : 12 - 12 (1 bit)

STINCDATA2 : DAC CH2 Sawtooth increment value (12.4 bit format)
bits : 16 - 31 (16 bit)


DAC_STMODR

Sawtooth Mode register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_STMODR DAC_STMODR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STRSTTRIGSEL1 STINCTRIGSEL1 STRSTTRIGSEL2 STINCTRIGSEL2

STRSTTRIGSEL1 : DAC Channel 1 Sawtooth Reset trigger selection
bits : 0 - 3 (4 bit)

STINCTRIGSEL1 : DAC Channel 1 Sawtooth Increment trigger selection
bits : 8 - 11 (4 bit)

STRSTTRIGSEL2 : DAC Channel 1 Sawtooth Reset trigger selection
bits : 16 - 19 (4 bit)

STINCTRIGSEL2 : DAC Channel 2 Sawtooth Increment trigger selection
bits : 24 - 27 (4 bit)


DAC_DHR12R1

DAC channel1 12-bit right-aligned data holding register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_DHR12R1 DAC_DHR12R1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC1DHR DACC1DHRB

DACC1DHR : DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.
bits : 0 - 11 (12 bit)

DACC1DHRB : DAC channel1 12-bit right-aligned data B
bits : 16 - 27 (12 bit)


DAC_DHR12L1

DAC channel1 12-bit left aligned data holding register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_DHR12L1 DAC_DHR12L1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC1DHR DACC1DHRB

DACC1DHR : DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.
bits : 4 - 15 (12 bit)

DACC1DHRB : DAC channel1 12-bit left-aligned data B
bits : 20 - 31 (12 bit)



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