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SCB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x41 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CPUID

SCR

CCR

SHPR1

SHPR2

SHPR3

SHCSR

SHCRS

CFSR_UFSR_BFSR_MMFSR

HFSR

MMFAR

BFAR

AFSR

ICSR

VTOR

AIRCR


CPUID

CPUID base register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CPUID CPUID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Revision PartNo Constant Variant Implementer

Revision : Revision number
bits : 0 - 3 (4 bit)

PartNo : Part number of the processor
bits : 4 - 15 (12 bit)

Constant : Reads as 0xF
bits : 16 - 19 (4 bit)

Variant : Variant number
bits : 20 - 23 (4 bit)

Implementer : Implementer code
bits : 24 - 31 (8 bit)


SCR

System control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCR SCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLEEPONEXIT SLEEPDEEP SEVEONPEND

SLEEPONEXIT : SLEEPONEXIT
bits : 1 - 1 (1 bit)

SLEEPDEEP : SLEEPDEEP
bits : 2 - 2 (1 bit)

SEVEONPEND : Send Event on Pending bit
bits : 4 - 4 (1 bit)


CCR

Configuration and control register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NONBASETHRDENA USERSETMPEND UNALIGN__TRP DIV_0_TRP BFHFNMIGN STKALIGN

NONBASETHRDENA : Configures how the processor enters Thread mode
bits : 0 - 0 (1 bit)

USERSETMPEND : USERSETMPEND
bits : 1 - 1 (1 bit)

UNALIGN__TRP : UNALIGN_ TRP
bits : 3 - 3 (1 bit)

DIV_0_TRP : DIV_0_TRP
bits : 4 - 4 (1 bit)

BFHFNMIGN : BFHFNMIGN
bits : 8 - 8 (1 bit)

STKALIGN : STKALIGN
bits : 9 - 9 (1 bit)


SHPR1

System handler priority registers
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHPR1 SHPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_4 PRI_5 PRI_6

PRI_4 : Priority of system handler 4
bits : 0 - 7 (8 bit)

PRI_5 : Priority of system handler 5
bits : 8 - 15 (8 bit)

PRI_6 : Priority of system handler 6
bits : 16 - 23 (8 bit)


SHPR2

System handler priority registers
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHPR2 SHPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_11

PRI_11 : Priority of system handler 11
bits : 24 - 31 (8 bit)


SHPR3

System handler priority registers
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHPR3 SHPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_14 PRI_15

PRI_14 : Priority of system handler 14
bits : 16 - 23 (8 bit)

PRI_15 : Priority of system handler 15
bits : 24 - 31 (8 bit)


SHCSR

System handler control and state register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHCSR SHCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEMFAULTACT BUSFAULTACT USGFAULTACT SVCALLACT MONITORACT PENDSVACT SYSTICKACT USGFAULTPENDED MEMFAULTPENDED BUSFAULTPENDED SVCALLPENDED MEMFAULTENA BUSFAULTENA USGFAULTENA

MEMFAULTACT : Memory management fault exception active bit
bits : 0 - 0 (1 bit)

BUSFAULTACT : Bus fault exception active bit
bits : 1 - 1 (1 bit)

USGFAULTACT : Usage fault exception active bit
bits : 3 - 3 (1 bit)

SVCALLACT : SVC call active bit
bits : 7 - 7 (1 bit)

MONITORACT : Debug monitor active bit
bits : 8 - 8 (1 bit)

PENDSVACT : PendSV exception active bit
bits : 10 - 10 (1 bit)

SYSTICKACT : SysTick exception active bit
bits : 11 - 11 (1 bit)

USGFAULTPENDED : Usage fault exception pending bit
bits : 12 - 12 (1 bit)

MEMFAULTPENDED : Memory management fault exception pending bit
bits : 13 - 13 (1 bit)

BUSFAULTPENDED : Bus fault exception pending bit
bits : 14 - 14 (1 bit)

SVCALLPENDED : SVC call pending bit
bits : 15 - 15 (1 bit)

MEMFAULTENA : Memory management fault enable bit
bits : 16 - 16 (1 bit)

BUSFAULTENA : Bus fault enable bit
bits : 17 - 17 (1 bit)

USGFAULTENA : Usage fault enable bit
bits : 18 - 18 (1 bit)


SHCRS

System handler control and state register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHCRS SHCRS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEMFAULTACT BUSFAULTACT USGFAULTACT SVCALLACT MONITORACT PENDSVACT SYSTICKACT USGFAULTPENDED MEMFAULTPENDED BUSFAULTPENDED SVCALLPENDED MEMFAULTENA BUSFAULTENA USGFAULTENA

MEMFAULTACT : Memory management fault exception active bit
bits : 0 - 0 (1 bit)

BUSFAULTACT : Bus fault exception active bit
bits : 1 - 1 (1 bit)

USGFAULTACT : Usage fault exception active bit
bits : 3 - 3 (1 bit)

SVCALLACT : SVC call active bit
bits : 7 - 7 (1 bit)

MONITORACT : Debug monitor active bit
bits : 8 - 8 (1 bit)

PENDSVACT : PendSV exception active bit
bits : 10 - 10 (1 bit)

SYSTICKACT : SysTick exception active bit
bits : 11 - 11 (1 bit)

USGFAULTPENDED : Usage fault exception pending bit
bits : 12 - 12 (1 bit)

MEMFAULTPENDED : Memory management fault exception pending bit
bits : 13 - 13 (1 bit)

BUSFAULTPENDED : Bus fault exception pending bit
bits : 14 - 14 (1 bit)

SVCALLPENDED : SVC call pending bit
bits : 15 - 15 (1 bit)

MEMFAULTENA : Memory management fault enable bit
bits : 16 - 16 (1 bit)

BUSFAULTENA : Bus fault enable bit
bits : 17 - 17 (1 bit)

USGFAULTENA : Usage fault enable bit
bits : 18 - 18 (1 bit)


CFSR_UFSR_BFSR_MMFSR

Configurable fault status register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFSR_UFSR_BFSR_MMFSR CFSR_UFSR_BFSR_MMFSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IACCVIOL MUNSTKERR MSTKERR MLSPERR MMARVALID IBUSERR PRECISERR IMPRECISERR UNSTKERR STKERR LSPERR BFARVALID UNDEFINSTR INVSTATE INVPC NOCP UNALIGNED DIVBYZERO

IACCVIOL : Instruction access violation flag
bits : 1 - 1 (1 bit)

MUNSTKERR : Memory manager fault on unstacking for a return from exception
bits : 3 - 3 (1 bit)

MSTKERR : Memory manager fault on stacking for exception entry.
bits : 4 - 4 (1 bit)

MLSPERR : MLSPERR
bits : 5 - 5 (1 bit)

MMARVALID : Memory Management Fault Address Register (MMAR) valid flag
bits : 7 - 7 (1 bit)

IBUSERR : Instruction bus error
bits : 8 - 8 (1 bit)

PRECISERR : Precise data bus error
bits : 9 - 9 (1 bit)

IMPRECISERR : Imprecise data bus error
bits : 10 - 10 (1 bit)

UNSTKERR : Bus fault on unstacking for a return from exception
bits : 11 - 11 (1 bit)

STKERR : Bus fault on stacking for exception entry
bits : 12 - 12 (1 bit)

LSPERR : Bus fault on floating-point lazy state preservation
bits : 13 - 13 (1 bit)

BFARVALID : Bus Fault Address Register (BFAR) valid flag
bits : 15 - 15 (1 bit)

UNDEFINSTR : Undefined instruction usage fault
bits : 16 - 16 (1 bit)

INVSTATE : Invalid state usage fault
bits : 17 - 17 (1 bit)

INVPC : Invalid PC load usage fault
bits : 18 - 18 (1 bit)

NOCP : No coprocessor usage fault.
bits : 19 - 19 (1 bit)

UNALIGNED : Unaligned access usage fault
bits : 24 - 24 (1 bit)

DIVBYZERO : Divide by zero usage fault
bits : 25 - 25 (1 bit)


HFSR

Hard fault status register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFSR HFSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VECTTBL FORCED DEBUG_VT

VECTTBL : Vector table hard fault
bits : 1 - 1 (1 bit)

FORCED : Forced hard fault
bits : 30 - 30 (1 bit)

DEBUG_VT : Reserved for Debug use
bits : 31 - 31 (1 bit)


MMFAR

Memory management fault address register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMFAR MMFAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMFAR

MMFAR : Memory management fault address
bits : 0 - 31 (32 bit)


BFAR

Bus fault address register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BFAR BFAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BFAR

BFAR : Bus fault address
bits : 0 - 31 (32 bit)


AFSR

Auxiliary fault status register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AFSR AFSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMPDEF

IMPDEF : Implementation defined
bits : 0 - 31 (32 bit)


ICSR

Interrupt control and state register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICSR ICSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VECTACTIVE RETTOBASE VECTPENDING ISRPENDING PENDSTCLR PENDSTSET PENDSVCLR PENDSVSET NMIPENDSET

VECTACTIVE : Active vector
bits : 0 - 8 (9 bit)

RETTOBASE : Return to base level
bits : 11 - 11 (1 bit)

VECTPENDING : Pending vector
bits : 12 - 18 (7 bit)

ISRPENDING : Interrupt pending flag
bits : 22 - 22 (1 bit)

PENDSTCLR : SysTick exception clear-pending bit
bits : 25 - 25 (1 bit)

PENDSTSET : SysTick exception set-pending bit
bits : 26 - 26 (1 bit)

PENDSVCLR : PendSV clear-pending bit
bits : 27 - 27 (1 bit)

PENDSVSET : PendSV set-pending bit
bits : 28 - 28 (1 bit)

NMIPENDSET : NMI set-pending bit.
bits : 31 - 31 (1 bit)


VTOR

Vector table offset register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VTOR VTOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBLOFF

TBLOFF : Vector table base offset field
bits : 9 - 29 (21 bit)


AIRCR

Application interrupt and reset control register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AIRCR AIRCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VECTRESET VECTCLRACTIVE SYSRESETREQ PRIGROUP ENDIANESS VECTKEYSTAT

VECTRESET : VECTRESET
bits : 0 - 0 (1 bit)

VECTCLRACTIVE : VECTCLRACTIVE
bits : 1 - 1 (1 bit)

SYSRESETREQ : SYSRESETREQ
bits : 2 - 2 (1 bit)

PRIGROUP : PRIGROUP
bits : 8 - 10 (3 bit)

ENDIANESS : ENDIANESS
bits : 15 - 15 (1 bit)

VECTKEYSTAT : Register key
bits : 16 - 31 (16 bit)



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