\n
address_offset : 0x0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x34 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x44 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x8 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x14 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x18 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x28 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x2C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x38 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x3C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x24 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x26 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x48 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x50 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
A/D Status Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCS : Scan conversion status flag
bits : 0 - -1 (0 bit)
access : read-write
PCS : Priority conversion status flag
bits : 1 - 0 (0 bit)
access : read-write
PCNS : Priority conversion pending flag
bits : 2 - 1 (0 bit)
access : read-write
FDAS : FIFO data placement selection bit
bits : 6 - 5 (0 bit)
access : read-write
ADSTP : A/D conversion forced stop bit
bits : 7 - 6 (0 bit)
access : read-write
A/D Control Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVRIE : FIFO overrun interrupt enable bit
bits : 0 - -1 (0 bit)
access : read-write
CMPIE : Conversion result comparison interrupt enable bit
bits : 1 - 0 (0 bit)
access : read-write
PCIE : Priority conversion interrupt enable bit
bits : 2 - 1 (0 bit)
access : read-write
SCIE : Scan conversion interrupt enable bit
bits : 3 - 2 (0 bit)
access : read-write
CMPIF : Conversion result comparison interrupt request bit
bits : 5 - 4 (0 bit)
access : read-write
PCIF : Priority conversion interrupt request bit
bits : 6 - 5 (0 bit)
access : read-write
SCIF : Scan conversion interrupt request bit
bits : 7 - 6 (0 bit)
access : read-write
Scan Conversion Input Selection Register 2
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AN16 : Bit0 of SCIS2
bits : 0 - -1 (0 bit)
access : read-write
AN17 : Bit1 of SCIS2
bits : 1 - 0 (0 bit)
access : read-write
AN18 : Bit2 of SCIS2
bits : 2 - 1 (0 bit)
access : read-write
AN19 : Bit3 of SCIS2
bits : 3 - 2 (0 bit)
access : read-write
AN20 : Bit4 of SCIS2
bits : 4 - 3 (0 bit)
access : read-write
AN21 : Bit5 of SCIS2
bits : 5 - 4 (0 bit)
access : read-write
AN22 : Bit6 of SCIS2
bits : 6 - 5 (0 bit)
access : read-write
AN23 : Bit7 of SCIS2
bits : 7 - 6 (0 bit)
access : read-write
Scan Conversion Input Selection Register 3
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AN24 : Bit0 of SCIS3
bits : 0 - -1 (0 bit)
access : read-write
AN25 : Bit1 of SCIS3
bits : 1 - 0 (0 bit)
access : read-write
AN26 : Bit2 of SCIS3
bits : 2 - 1 (0 bit)
access : read-write
AN27 : Bit3 of SCIS3
bits : 3 - 2 (0 bit)
access : read-write
AN28 : Bit4 of SCIS3
bits : 4 - 3 (0 bit)
access : read-write
AN29 : Bit5 of SCIS3
bits : 5 - 4 (0 bit)
access : read-write
AN30 : Bit6 of SCIS3
bits : 6 - 5 (0 bit)
access : read-write
AN31 : Bit7 of SCIS3
bits : 7 - 6 (0 bit)
access : read-write
Scan Conversion Input Selection Register 0
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AN0 : Bit0 of SCIS0
bits : 0 - -1 (0 bit)
access : read-write
AN1 : Bit1 of SCIS0
bits : 1 - 0 (0 bit)
access : read-write
AN2 : Bit2 of SCIS0
bits : 2 - 1 (0 bit)
access : read-write
AN3 : Bit3 of SCIS0
bits : 3 - 2 (0 bit)
access : read-write
AN4 : Bit4 of SCIS0
bits : 4 - 3 (0 bit)
access : read-write
AN5 : Bit5 of SCIS0
bits : 5 - 4 (0 bit)
access : read-write
AN6 : Bit6 of SCIS0
bits : 6 - 5 (0 bit)
access : read-write
AN7 : Bit7 of SCIS0
bits : 7 - 6 (0 bit)
access : read-write
Scan Conversion Input Selection Register 1
address_offset : 0x15 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AN8 : Bit0 of SCIS1
bits : 0 - -1 (0 bit)
access : read-write
AN9 : Bit1 of SCIS1
bits : 1 - 0 (0 bit)
access : read-write
AN10 : Bit2 of SCIS1
bits : 2 - 1 (0 bit)
access : read-write
AN11 : Bit3 of SCIS1
bits : 3 - 2 (0 bit)
access : read-write
AN12 : Bit4 of SCIS1
bits : 4 - 3 (0 bit)
access : read-write
AN13 : Bit5 of SCIS1
bits : 5 - 4 (0 bit)
access : read-write
AN14 : Bit6 of SCIS1
bits : 6 - 5 (0 bit)
access : read-write
AN15 : Bit7 of SCIS1
bits : 7 - 6 (0 bit)
access : read-write
Priority Conversion FIFO Stage Count Setup Register
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PFS : Priority conversion FIFO stage count setting bits
bits : 0 - 0 (1 bit)
access : read-write
TEST : Test bits
bits : 4 - 4 (1 bit)
access : read-only
Priority Conversion Control Register
address_offset : 0x19 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSTR : Priority conversion start bit
bits : 0 - -1 (0 bit)
access : read-write
PHEN : Priority conversion timer start enable bit
bits : 1 - 0 (0 bit)
access : read-write
PEEN : Priority conversion external start enable bit
bits : 2 - 1 (0 bit)
access : read-write
ESCE : External trigger analog input selection bit
bits : 3 - 2 (0 bit)
access : read-write
PFCLR : Priority conversion FIFO clear bit
bits : 4 - 3 (0 bit)
access : read-write
POVR : Priority conversion overrun flag
bits : 5 - 4 (0 bit)
access : read-write
PFUL : Priority conversion FIFO full bit
bits : 6 - 5 (0 bit)
access : read-only
PEMP : Priority conversion FIFO empty bit
bits : 7 - 6 (0 bit)
access : read-only
Priority Conversion FIFO Data Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PC : Conversion input channel bits
bits : 0 - 3 (4 bit)
access : read-only
RS : Scan conversion start factor
bits : 8 - 9 (2 bit)
access : read-only
INVL : A/D conversion result disable bit
bits : 12 - 11 (0 bit)
access : read-only
PD : Priority conversion result
bits : 20 - 30 (11 bit)
access : read-only
Priority Conversion Input Selection Register
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1A : Priority level 1 analog input selection
bits : 0 - 1 (2 bit)
access : read-write
P2A : Priority level 2 analog input selection
bits : 3 - 6 (4 bit)
access : read-write
A/D Comparison Control Register
address_offset : 0x24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCH : Comparison target analog input channel
bits : 0 - 3 (4 bit)
access : read-write
CMD0 : Comparison mode 0
bits : 5 - 4 (0 bit)
access : read-write
CMD1 : Comparison mode 1
bits : 6 - 5 (0 bit)
access : read-write
CMPEN : Conversion result comparison function operation enable bit
bits : 7 - 6 (0 bit)
access : read-write
A/D Comparison Value Setup Register
address_offset : 0x26 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMAD : A/D conversion result value setting bits
bits : 6 - 14 (9 bit)
access : read-write
Sampling Time Selection Register 2
address_offset : 0x28 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TS16 : Bit0 of ADSS2
bits : 0 - -1 (0 bit)
access : read-write
TS17 : Bit1 of ADSS2
bits : 1 - 0 (0 bit)
access : read-write
TS18 : Bit2 of ADSS2
bits : 2 - 1 (0 bit)
access : read-write
TS19 : Bit3 of ADSS2
bits : 3 - 2 (0 bit)
access : read-write
TS20 : Bit4 of ADSS2
bits : 4 - 3 (0 bit)
access : read-write
TS21 : Bit5 of ADSS2
bits : 5 - 4 (0 bit)
access : read-write
TS22 : Bit6 of ADSS2
bits : 6 - 5 (0 bit)
access : read-write
TS23 : Bit7 of ADSS2
bits : 7 - 6 (0 bit)
access : read-write
Sampling Time Selection Register 3
address_offset : 0x29 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TS24 : Bit0 of ADSS3
bits : 0 - -1 (0 bit)
access : read-write
TS25 : Bit1 of ADSS3
bits : 1 - 0 (0 bit)
access : read-write
TS26 : Bit2 of ADSS3
bits : 2 - 1 (0 bit)
access : read-write
TS27 : Bit3 of ADSS3
bits : 3 - 2 (0 bit)
access : read-write
TS28 : Bit4 of ADSS3
bits : 4 - 3 (0 bit)
access : read-write
TS29 : Bit5 of ADSS3
bits : 5 - 4 (0 bit)
access : read-write
TS30 : Bit6 of ADSS3
bits : 6 - 5 (0 bit)
access : read-write
TS31 : Bit7 of ADSS3
bits : 7 - 6 (0 bit)
access : read-write
Sampling Time Selection Register 0
address_offset : 0x2C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TS0 : Bit0 of ADSS0
bits : 0 - -1 (0 bit)
access : read-write
TS1 : Bit1 of ADSS0
bits : 1 - 0 (0 bit)
access : read-write
TS2 : Bit2 of ADSS0
bits : 2 - 1 (0 bit)
access : read-write
TS3 : Bit3 of ADSS0
bits : 3 - 2 (0 bit)
access : read-write
TS4 : Bit4 of ADSS0
bits : 4 - 3 (0 bit)
access : read-write
TS5 : Bit5 of ADSS0
bits : 5 - 4 (0 bit)
access : read-write
TS6 : Bit6 of ADSS0
bits : 6 - 5 (0 bit)
access : read-write
TS7 : Bit7 of ADSS0
bits : 7 - 6 (0 bit)
access : read-write
Sampling Time Selection Register 1
address_offset : 0x2D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TS8 : Bit0 of ADSS1
bits : 0 - -1 (0 bit)
access : read-write
TS9 : Bit1 of ADSS1
bits : 1 - 0 (0 bit)
access : read-write
TS10 : Bit2 of ADSS1
bits : 2 - 1 (0 bit)
access : read-write
TS11 : Bit3 of ADSS1
bits : 3 - 2 (0 bit)
access : read-write
TS12 : Bit4 of ADSS1
bits : 4 - 3 (0 bit)
access : read-write
TS13 : Bit5 of ADSS1
bits : 5 - 4 (0 bit)
access : read-write
TS14 : Bit6 of ADSS1
bits : 6 - 5 (0 bit)
access : read-write
TS15 : Bit7 of ADSS1
bits : 7 - 6 (0 bit)
access : read-write
Sampling Time Setup Register 1
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ST1 : Sampling time setting bits
bits : 0 - 3 (4 bit)
access : read-write
STX1 : Sampling time N times setting bits
bits : 5 - 6 (2 bit)
access : read-write
Sampling Time Setup Register 0
address_offset : 0x31 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ST0 : Sampling time setting bits
bits : 0 - 3 (4 bit)
access : read-write
STX0 : Sampling time N times setting bits
bits : 5 - 6 (2 bit)
access : read-write
Frequency Division Ratio Setup Register
address_offset : 0x34 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CT : Frequency division ratio setting bits
bits : 0 - 6 (7 bit)
access : read-write
Priority Conversion Timer Trigger Selection Register
address_offset : 0x38 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRTSL : Priority conversion timer trigger selection bit
bits : 0 - 2 (3 bit)
access : read-write
Scan Conversion Timer Trigger Selection Register
address_offset : 0x39 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCTSL : Scan conversion timer trigger selection bit
bits : 0 - 2 (3 bit)
access : read-write
A/D Operation Enable Setup Register
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBL : A/D operation enable bit
bits : 0 - -1 (0 bit)
access : read-write
READY : A/D operation enable state bit
bits : 1 - 0 (0 bit)
access : read-only
ENBLTIME : Operation enable state transition cycle selection bits
bits : 8 - 14 (7 bit)
access : read-write
Range Comparison Threshold Excess Flag Register
address_offset : 0x44 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RCOOF : Threshold excess flag bit
bits : 0 - -1 (0 bit)
access : read-write
Range Comparison Flag Register
address_offset : 0x48 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RCINT : Range comparison interrupt factor flag
bits : 0 - -1 (0 bit)
access : read-write
Range Comparison Control Register
address_offset : 0x4C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RCOE : Range comparison execution enable bit
bits : 2 - 1 (0 bit)
access : read-write
RCOIE : Range comparison interrupt request enable bit
bits : 3 - 2 (0 bit)
access : read-write
RCOIRS : Selection bit of within-range and out-of- range confirmation
bits : 4 - 3 (0 bit)
access : read-write
RCOCD : Continuous detection specification count/state indication bits
bits : 5 - 6 (2 bit)
access : read-write
Range Comparison Channel Select Register
address_offset : 0x4D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WCCH : Comparison target analog input channel
bits : 0 - 3 (4 bit)
access : read-write
WCMD : Comparison mode select bit
bits : 5 - 4 (0 bit)
access : read-write
Lower Limit Threshold Setup Register
address_offset : 0x50 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMLD : Lower limit threshold bits
bits : 6 - 14 (9 bit)
access : read-write
Upper Limit Setup Register
address_offset : 0x52 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMHD : Upper limit threshold bits
bits : 6 - 14 (9 bit)
access : read-write
Scan Conversion FIFO Stage Count Setup Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFS : Scan conversion FIFO stage count setting bit
bits : 0 - 2 (3 bit)
access : read-write
Scan Conversion Control Register
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSTR : Scan conversion start bit
bits : 0 - -1 (0 bit)
access : read-write
SHEN : Scan conversion timer start enable bit
bits : 1 - 0 (0 bit)
access : read-write
RPT : Scan conversion repeat bit
bits : 2 - 1 (0 bit)
access : read-write
SFCLR : Scan conversion FIFO clear bit
bits : 4 - 3 (0 bit)
access : read-write
SOVR : Scan conversion overrun flag
bits : 5 - 4 (0 bit)
access : read-write
SFUL : Scan conversion FIFO full bit
bits : 6 - 5 (0 bit)
access : read-only
SEMP : Scan conversion FIFO empty bit
bits : 7 - 6 (0 bit)
access : read-only
Scan Conversion FIFO Data Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SC : Conversion input channel bits
bits : 0 - 3 (4 bit)
access : read-only
RS : Scan conversion start factor
bits : 8 - 8 (1 bit)
access : read-only
INVL : A/D conversion result disable bit
bits : 12 - 11 (0 bit)
access : read-only
SD : Scan conversion result
bits : 20 - 30 (11 bit)
access : read-only
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