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GPIO

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x740 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PFR0

PFR4

PCR0

PCR1

PCR2

PCR3

PCR4

PCR5

PCR6

PCRE

PFR5

PFR6

PFR8

DDR0

DDR1

DDR2

DDR3

DDR4

DDR5

DDR6

DDR8

DDRE

PDIR0

PDIR1

PDIR2

PDIR3

PDIR4

PDIR5

PDIR6

PDIR8

PDIRE

PFRE

PFR1

PDOR0

PDOR1

PDOR2

PDOR3

PDOR4

PDOR5

PDOR6

PDOR8

PDORE

ADE

SPSR

EPFR00

EPFR01

EPFR04

EPFR05

EPFR06

EPFR07

EPFR08

EPFR09

EPFR10

EPFR11

EPFR12

EPFR13

EPFR14

EPFR15

EPFR16

EPFR17

EPFR18

PZR6

PFR2

PFR3


PFR0

Port function setting register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PFR0 PFR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 PF

P0 : Bit0 of PFR0
bits : 0 - -1 (0 bit)
access : read-write

P1 : Bit1 of PFR0
bits : 1 - 0 (0 bit)
access : read-write

P2 : Bit2 of PFR0
bits : 2 - 1 (0 bit)
access : read-write

P3 : Bit3 of PFR0
bits : 3 - 2 (0 bit)
access : read-write

P4 : Bit4 of PFR0
bits : 4 - 3 (0 bit)
access : read-write

PF : Bit15 of PFR0
bits : 15 - 14 (0 bit)
access : read-write


PFR4

Port function setting register 4
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PFR4 PFR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P6 P7 P9 PA

P6 : Bit6 of PFR4
bits : 6 - 5 (0 bit)
access : read-write

P7 : Bit7 of PFR4
bits : 7 - 6 (0 bit)
access : read-write

P9 : Bit9 of PFR4
bits : 9 - 8 (0 bit)
access : read-write

PA : Bit10 of PFR4
bits : 10 - 9 (0 bit)
access : read-write


PCR0

Pull-up Setting Register 0
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR0 PCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PCR1

Pull-up Setting Register 1
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR1 PCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PCR2

Pull-up Setting Register 2
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR2 PCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PCR3

Pull-up Setting Register 3
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR3 PCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PCR4

Pull-up Setting Register 4
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR4 PCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PCR5

Pull-up Setting Register 5
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR5 PCR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PCR6

Pull-up Setting Register 6
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR6 PCR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PCRE

Pull-up Setting Register E
address_offset : 0x138 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCRE PCRE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PFR5

Port function setting register 5
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PFR5 PFR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2

P0 : Bit0 of PFR5
bits : 0 - -1 (0 bit)
access : read-write

P1 : Bit1 of PFR5
bits : 1 - 0 (0 bit)
access : read-write

P2 : Bit2 of PFR5
bits : 2 - 1 (0 bit)
access : read-write


PFR6

Port function setting register 6
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PFR6 PFR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1

P0 : Bit0 of PFR6
bits : 0 - -1 (0 bit)
access : read-write

P1 : Bit1 of PFR6
bits : 1 - 0 (0 bit)
access : read-write


PFR8

Port function setting register 8
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PFR8 PFR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1

P0 : Bit0 of PFR8
bits : 0 - -1 (0 bit)
access : read-write

P1 : Bit1 of PFR8
bits : 1 - 0 (0 bit)
access : read-write


DDR0

Port input/output direction setting register 0
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDR0 DDR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 PF

P0 : Bit0 of DDR0
bits : 0 - -1 (0 bit)
access : read-write

P1 : Bit1 of DDR0
bits : 1 - 0 (0 bit)
access : read-write

P2 : Bit2 of DDR0
bits : 2 - 1 (0 bit)
access : read-write

P3 : Bit3 of DDR0
bits : 3 - 2 (0 bit)
access : read-write

P4 : Bit4 of DDR0
bits : 4 - 3 (0 bit)
access : read-write

PF : Bit15 of DDR0
bits : 15 - 14 (0 bit)
access : read-write


DDR1

Port input/output direction setting register 1
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDR1 DDR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DDR2

Port input/output direction setting register 2
address_offset : 0x208 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDR2 DDR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DDR3

Port input/output direction setting register 3
address_offset : 0x20C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDR3 DDR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DDR4

Port input/output direction setting register 4
address_offset : 0x210 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDR4 DDR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DDR5

Port input/output direction setting register 5
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDR5 DDR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DDR6

Port input/output direction setting register 6
address_offset : 0x218 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDR6 DDR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DDR8

Port input/output direction setting register 8
address_offset : 0x220 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDR8 DDR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DDRE

Port input/output direction setting register E
address_offset : 0x238 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DDRE DDRE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDIR0

Port input data register 0
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDIR0 PDIR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDIR1

Port input data register 1
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDIR1 PDIR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDIR2

Port input data register 2
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDIR2 PDIR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDIR3

Port input data register 3
address_offset : 0x30C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDIR3 PDIR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDIR4

Port input data register 4
address_offset : 0x310 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDIR4 PDIR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDIR5

Port input data register 5
address_offset : 0x314 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDIR5 PDIR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDIR6

Port input data register 6
address_offset : 0x318 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDIR6 PDIR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDIR8

Port input data register 8
address_offset : 0x320 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDIR8 PDIR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDIRE

Port input data register E
address_offset : 0x338 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDIRE PDIRE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PFRE

Port function setting register E
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PFRE PFRE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P2 P3

P0 : Bit0 of PFRE
bits : 0 - -1 (0 bit)
access : read-write

P2 : Bit2 of PFRE
bits : 2 - 1 (0 bit)
access : read-write

P3 : Bit3 of PFRE
bits : 3 - 2 (0 bit)
access : read-write


PFR1

Port function setting register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PFR1 PFR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P4 P5

P0 : Bit0 of PFR1
bits : 0 - -1 (0 bit)
access : read-write

P1 : Bit1 of PFR1
bits : 1 - 0 (0 bit)
access : read-write

P2 : Bit2 of PFR1
bits : 2 - 1 (0 bit)
access : read-write

P4 : Bit4 of PFR1
bits : 4 - 3 (0 bit)
access : read-write

P5 : Bit5 of PFR1
bits : 5 - 4 (0 bit)
access : read-write


PDOR0

Port output data register 0
address_offset : 0x400 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDOR0 PDOR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDOR1

Port output data register 1
address_offset : 0x404 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDOR1 PDOR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDOR2

Port output data register 2
address_offset : 0x408 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDOR2 PDOR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDOR3

Port output data register 3
address_offset : 0x40C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDOR3 PDOR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDOR4

Port output data register 4
address_offset : 0x410 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDOR4 PDOR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDOR5

Port output data register 5
address_offset : 0x414 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDOR5 PDOR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDOR6

Port output data register 6
address_offset : 0x418 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDOR6 PDOR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDOR8

Port output data register 8
address_offset : 0x420 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDOR8 PDOR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDORE

Port output data register E
address_offset : 0x438 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDORE PDORE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADE

Analog input setting register
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADE ADE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AN0 AN1 AN2 AN4 AN5 AN12 AN13 AN14 AN18 AN20 AN21 AN22 AN23 AN24

AN0 : Bit0 of ADE
bits : 0 - -1 (0 bit)
access : read-write

AN1 : Bit1 of ADE
bits : 1 - 0 (0 bit)
access : read-write

AN2 : Bit2 of ADE
bits : 2 - 1 (0 bit)
access : read-write

AN4 : Bit4 of ADE
bits : 4 - 3 (0 bit)
access : read-write

AN5 : Bit5 of ADE
bits : 5 - 4 (0 bit)
access : read-write

AN12 : Bit12 of ADE
bits : 12 - 11 (0 bit)
access : read-write

AN13 : Bit13 of ADE
bits : 13 - 12 (0 bit)
access : read-write

AN14 : Bit14 of ADE
bits : 14 - 13 (0 bit)
access : read-write

AN18 : Bit18 of ADE
bits : 18 - 17 (0 bit)
access : read-write

AN20 : Bit20 of ADE
bits : 20 - 19 (0 bit)
access : read-write

AN21 : Bit21 of ADE
bits : 21 - 20 (0 bit)
access : read-write

AN22 : Bit22 of ADE
bits : 22 - 21 (0 bit)
access : read-write

AN23 : Bit23 of ADE
bits : 23 - 22 (0 bit)
access : read-write

AN24 : Bit24 of ADE
bits : 24 - 23 (0 bit)
access : read-write


SPSR

Special port setting register
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPSR SPSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBXC MAINXC USB0C

SUBXC : Sub clock(oscillation) pin setting bit
bits : 0 - 0 (1 bit)
access : read-write

MAINXC : Main clock(oscillation) pin setting bit
bits : 2 - 2 (1 bit)
access : read-write

USB0C : USBch0 pin setting bit
bits : 4 - 3 (0 bit)
access : read-write


EPFR00

Extended pin function setting register 00
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPFR00 EPFR00 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NMIS CROUTE RTCCOE SUBOUTE USBP0E JTAGEN0B JTAGEN1S

NMIS : NMIX function select bit
bits : 0 - -1 (0 bit)
access : read-write

CROUTE : Internal high-speed CR oscillation output function select bit
bits : 1 - 1 (1 bit)
access : read-write

RTCCOE : RTC clock output select bit
bits : 4 - 4 (1 bit)
access : read-write

SUBOUTE : Sub clock divide output function select bit
bits : 6 - 6 (1 bit)
access : read-write

USBP0E : USBch0 function select bit
bits : 9 - 8 (0 bit)
access : read-write

JTAGEN0B : JTAG function select bit0
bits : 16 - 15 (0 bit)
access : read-write

JTAGEN1S : JTAG function select bit1
bits : 17 - 16 (0 bit)
access : read-write


EPFR01

Extended pin function setting register 01
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPFR01 EPFR01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTO00E RTO01E RTO02E RTO03E RTO04E RTO05E DTTI0C DTTI0S FRCK0S IC00S IC01S IC02S IC03S

RTO00E : RTO00E output select bit
bits : 0 - 0 (1 bit)
access : read-write

RTO01E : RTO01E output select bit
bits : 2 - 2 (1 bit)
access : read-write

RTO02E : RTO02E output select bit
bits : 4 - 4 (1 bit)
access : read-write

RTO03E : RTO03E output select bit
bits : 6 - 6 (1 bit)
access : read-write

RTO04E : RTO04E output select bit
bits : 8 - 8 (1 bit)
access : read-write

RTO05E : RTO05E output select bit
bits : 10 - 10 (1 bit)
access : read-write

DTTI0C : DTTIX0 function select bit
bits : 12 - 11 (0 bit)
access : read-write

DTTI0S : DTTIX0 input select bit
bits : 16 - 16 (1 bit)
access : read-write

FRCK0S : FRCK0 input select bit
bits : 18 - 18 (1 bit)
access : read-write

IC00S : IC00 input select bit
bits : 20 - 21 (2 bit)
access : read-write

IC01S : IC01 input select bit
bits : 23 - 24 (2 bit)
access : read-write

IC02S : IC02 input select bit
bits : 26 - 27 (2 bit)
access : read-write

IC03S : IC03 input select bit
bits : 29 - 30 (2 bit)
access : read-write


EPFR04

Extended pin function setting register 04
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPFR04 EPFR04 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIOA0E TIOB0S TIOA1S TIOA1E TIOB1S TIOA2E TIOB2S TIOA3S TIOA3E TIOB3S

TIOA0E : TIOA0 output select bit
bits : 2 - 2 (1 bit)
access : read-write

TIOB0S : TIOB0 input select bit
bits : 4 - 5 (2 bit)
access : read-write

TIOA1S : TIOA1 input select bit
bits : 8 - 8 (1 bit)
access : read-write

TIOA1E : TIOA1E output select bit
bits : 10 - 10 (1 bit)
access : read-write

TIOB1S : TIOB1 input select bit
bits : 12 - 12 (1 bit)
access : read-write

TIOA2E : TIOA2 output select bit
bits : 18 - 18 (1 bit)
access : read-write

TIOB2S : TIOB2 input select bit
bits : 20 - 20 (1 bit)
access : read-write

TIOA3S : TIOA3 input select bit
bits : 24 - 24 (1 bit)
access : read-write

TIOA3E : TIOA3E output select bit
bits : 26 - 26 (1 bit)
access : read-write

TIOB3S : TIOB3 input select bit
bits : 28 - 28 (1 bit)
access : read-write


EPFR05

Extended pin function setting register 05
address_offset : 0x614 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPFR05 EPFR05 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIOA4E TIOB4S TIOA5S TIOA5E TIOB5S TIOA6E TIOB6S TIOA7S TIOA7E TIOB7S

TIOA4E : TIOA4 output select bit
bits : 2 - 2 (1 bit)
access : read-write

TIOB4S : TIOB4 input select bit
bits : 4 - 4 (1 bit)
access : read-write

TIOA5S : TIOA5 input select bit
bits : 8 - 8 (1 bit)
access : read-write

TIOA5E : TIOA5E output select bit
bits : 10 - 10 (1 bit)
access : read-write

TIOB5S : TIOB5 input select bit
bits : 12 - 12 (1 bit)
access : read-write

TIOA6E : TIOA6 output select bit
bits : 18 - 18 (1 bit)
access : read-write

TIOB6S : TIOB6 input select bit
bits : 20 - 20 (1 bit)
access : read-write

TIOA7S : TIOA7 input select bit
bits : 24 - 24 (1 bit)
access : read-write

TIOA7E : TIOA7E output select bit
bits : 26 - 26 (1 bit)
access : read-write

TIOB7S : TIOB7 input select Bit
bits : 28 - 28 (1 bit)
access : read-write


EPFR06

Extended pin function setting register 06
address_offset : 0x618 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPFR06 EPFR06 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EINT00S EINT01S EINT02S EINT03S EINT06S EINT07S EINT14S EINT15S

EINT00S : External interrupt 0 input select bit
bits : 0 - 0 (1 bit)
access : read-write

EINT01S : External interrupt 1 input select bit
bits : 2 - 2 (1 bit)
access : read-write

EINT02S : External interrupt 2 input select bit
bits : 4 - 4 (1 bit)
access : read-write

EINT03S : External interrupt 3 input select bit
bits : 6 - 6 (1 bit)
access : read-write

EINT06S : External interrupt 6 input select bit
bits : 12 - 12 (1 bit)
access : read-write

EINT07S : External interrupt 7 input select bit
bits : 14 - 14 (1 bit)
access : read-write

EINT14S : External interrupt 14 input select bit
bits : 28 - 28 (1 bit)
access : read-write

EINT15S : External interrupt 15 input select bit
bits : 30 - 30 (1 bit)
access : read-write


EPFR07

Extended pin function setting register 07
address_offset : 0x61C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPFR07 EPFR07 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIN0S SOT0B SCK0B SIN1S SOT1B SCK1B SIN3S SOT3B SCK3B

SIN0S : SIN0S input select bit
bits : 4 - 4 (1 bit)
access : read-write

SOT0B : SOT0B input/output select bit
bits : 6 - 6 (1 bit)
access : read-write

SCK0B : SCK0 input/output select bit
bits : 8 - 8 (1 bit)
access : read-write

SIN1S : SIN1S input select bit
bits : 10 - 10 (1 bit)
access : read-write

SOT1B : SCK1B input/output select bit
bits : 12 - 12 (1 bit)
access : read-write

SCK1B : SCK1 input/output select bit
bits : 14 - 14 (1 bit)
access : read-write

SIN3S : SIN3S input select bit
bits : 22 - 22 (1 bit)
access : read-write

SOT3B : SOT3B input/output select bit
bits : 24 - 24 (1 bit)
access : read-write

SCK3B : SCK3 input/output select bit
bits : 26 - 26 (1 bit)
access : read-write


EPFR08

Extended pin function setting register 08
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPFR08 EPFR08 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIN5S SOT5B SCK5B

SIN5S : SIN5S input select bit
bits : 10 - 10 (1 bit)
access : read-write

SOT5B : SOT5B input/output select bit
bits : 12 - 12 (1 bit)
access : read-write

SCK5B : SCK5 input/output select bit
bits : 14 - 14 (1 bit)
access : read-write


EPFR09

Extended pin function setting register 09
address_offset : 0x624 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPFR09 EPFR09 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QAIN0S QBIN0S QZIN0S ADTRG0S ADTRG1S CRX1S CTX1E

QAIN0S : QAIN0S input select bit
bits : 0 - 0 (1 bit)
access : read-write

QBIN0S : QBIN0S input select bit
bits : 2 - 2 (1 bit)
access : read-write

QZIN0S : QZIN0S input select bit
bits : 4 - 4 (1 bit)
access : read-write

ADTRG0S : ADTRG0 input select bit
bits : 12 - 14 (3 bit)
access : read-write

ADTRG1S : ADTRG1 input select bit
bits : 16 - 18 (3 bit)
access : read-write

CRX1S : CAN RX1 Input Select bits
bits : 28 - 28 (1 bit)
access : read-write

CTX1E : CAN TX1 Output Select bits
bits : 30 - 30 (1 bit)
access : read-write


EPFR10

Extended pin function setting register 10
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPFR10 EPFR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EPFR11

Extended pin function setting register 11
address_offset : 0x62C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPFR11 EPFR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EPFR12

Extended pin function setting register 12
address_offset : 0x630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPFR12 EPFR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EPFR13

Extended pin function setting register 13
address_offset : 0x634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPFR13 EPFR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EPFR14

Extended pin function setting register 14
address_offset : 0x638 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPFR14 EPFR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EPFR15

Extended pin function setting register 15
address_offset : 0x63C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPFR15 EPFR15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EINT16S EINT17S EINT18S EINT19S EINT20S EINT21S

EINT16S : External interrupt 16 input select bit
bits : 0 - 0 (1 bit)
access : read-write

EINT17S : External interrupt 17 input select bit
bits : 2 - 2 (1 bit)
access : read-write

EINT18S : External interrupt 18 input select bit
bits : 4 - 4 (1 bit)
access : read-write

EINT19S : External interrupt 19 input select bit
bits : 6 - 6 (1 bit)
access : read-write

EINT20S : External interrupt 20 input select bit
bits : 8 - 8 (1 bit)
access : read-write

EINT21S : External interrupt 21 input select bit
bits : 10 - 10 (1 bit)
access : read-write


EPFR16

Extended pin function setting register 16
address_offset : 0x640 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPFR16 EPFR16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EPFR17

Extended pin function setting register 17
address_offset : 0x644 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPFR17 EPFR17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EPFR18

Extended pin function setting register 18
address_offset : 0x648 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPFR18 EPFR18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PZR6

Port Pseudo Open Drain Setting Register 6
address_offset : 0x718 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PZR6 PZR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0

P0 : Bit0 of PZR6
bits : 0 - -1 (0 bit)
access : read-write


PFR2

Port function setting register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PFR2 PFR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P1 P2 P3

P1 : Bit1 of PFR2
bits : 1 - 0 (0 bit)
access : read-write

P2 : Bit2 of PFR2
bits : 2 - 1 (0 bit)
access : read-write

P3 : Bit3 of PFR2
bits : 3 - 2 (0 bit)
access : read-write


PFR3

Port function setting register 3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PFR3 PFR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P9 PA PB PC PD PE PF

P9 : Bit9 of PFR3
bits : 9 - 8 (0 bit)
access : read-write

PA : Bit10 of PFR3
bits : 10 - 9 (0 bit)
access : read-write

PB : Bit11 of PFR3
bits : 11 - 10 (0 bit)
access : read-write

PC : Bit12 of PFR3
bits : 12 - 11 (0 bit)
access : read-write

PD : Bit13 of PFR3
bits : 13 - 12 (0 bit)
access : read-write

PE : Bit14 of PFR3
bits : 14 - 13 (0 bit)
access : read-write

PF : Bit15 of PFR3
bits : 15 - 14 (0 bit)
access : read-write



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