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BT0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x4 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x8 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PWM_PCSR

PPG_PRLL

RT_PCSR

PWM_STC

PPG_STC

RT_STC

PWC_STC

PWM_TMCR2

PPG_TMCR2

RT_TMCR2

PWC_TMCR2

PWM_PDUT

PPG_PRLH

PWC_DTBF

PWM_TMR

PPG_TMR

RT_TMR

PWM_TMCR

PPG_TMCR

RT_TMCR

PWC_TMCR


PWM_PCSR

register PWM_PCSR
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : PWM
reset_Mask : 0x0

PWM_PCSR PWM_PCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PPG_PRLL

register PPG_PRLL
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : PPG
reset_Mask : 0x0

PPG_PRLL PPG_PRLL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RT_PCSR

register RT_PCSR
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : RT
reset_Mask : 0x0

RT_PCSR RT_PCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM_STC

register PWM_STC
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : PWM
reset_Mask : 0x0

PWM_STC PWM_STC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 UDIR DTIR TGIR UDIE DTIE TGIE

UDIR : bitfield UDIR
bits : 0 - -1 (0 bit)
access : read-write

DTIR : bitfield DTIR
bits : 1 - 0 (0 bit)
access : read-write

TGIR : bitfield TGIR
bits : 2 - 1 (0 bit)
access : read-write

UDIE : bitfield UDIE
bits : 4 - 3 (0 bit)
access : read-write

DTIE : bitfield DTIE
bits : 5 - 4 (0 bit)
access : read-write

TGIE : bitfield TGIE
bits : 6 - 5 (0 bit)
access : read-write


PPG_STC

register PPG_STC
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : PPG
reset_Mask : 0x0

PPG_STC PPG_STC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 UDIR TGIR UDIE TGIE

UDIR : bitfield UDIR
bits : 0 - -1 (0 bit)
access : read-write

TGIR : bitfield TGIR
bits : 2 - 1 (0 bit)
access : read-write

UDIE : bitfield UDIE
bits : 4 - 3 (0 bit)
access : read-write

TGIE : bitfield TGIE
bits : 6 - 5 (0 bit)
access : read-write


RT_STC

register RT_STC
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : RT
reset_Mask : 0x0

RT_STC RT_STC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 UDIR TGIR UDIE TGIE

UDIR : bitfield UDIR
bits : 0 - -1 (0 bit)
access : read-write

TGIR : bitfield TGIR
bits : 2 - 1 (0 bit)
access : read-write

UDIE : bitfield UDIE
bits : 4 - 3 (0 bit)
access : read-write

TGIE : bitfield TGIE
bits : 6 - 5 (0 bit)
access : read-write


PWC_STC

register PWC_STC
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : PWC
reset_Mask : 0x0

PWC_STC PWC_STC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVIR EDIR OVIE EDIE ERR

OVIR : bitfield OVIR
bits : 0 - -1 (0 bit)
access : read-write

EDIR : bitfield EDIR
bits : 2 - 1 (0 bit)
access : read-only

OVIE : bitfield OVIE
bits : 4 - 3 (0 bit)
access : read-write

EDIE : bitfield EDIE
bits : 6 - 5 (0 bit)
access : read-write

ERR : bitfield ERR
bits : 7 - 6 (0 bit)
access : read-only


PWM_TMCR2

register PWM_TMCR2
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : PWM
reset_Mask : 0x0

PWM_TMCR2 PWM_TMCR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CKS3

CKS3 : bitfield CKS3
bits : 0 - -1 (0 bit)
access : read-write


PPG_TMCR2

register PPG_TMCR2
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : PPG
reset_Mask : 0x0

PPG_TMCR2 PPG_TMCR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CKS3

CKS3 : bitfield CKS3
bits : 1 - 0 (0 bit)
access : read-write


RT_TMCR2

register RT_TMCR2
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : RT
reset_Mask : 0x0

RT_TMCR2 RT_TMCR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CKS3

CKS3 : bitfield CKS3
bits : 0 - -1 (0 bit)
access : read-write


PWC_TMCR2

register PWC_TMCR2
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : PWC
reset_Mask : 0x0

PWC_TMCR2 PWC_TMCR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CKS3

CKS3 : bitfield CKS3
bits : 0 - -1 (0 bit)
access : read-write


PWM_PDUT

register PWM_PDUT
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : PWM
reset_Mask : 0x0

PWM_PDUT PWM_PDUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PPG_PRLH

register PPG_PRLH
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : PPG
reset_Mask : 0x0

PPG_PRLH PPG_PRLH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWC_DTBF

register PWC_DTBF
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
alternate_register : PWC
reset_Mask : 0x0

PWC_DTBF PWC_DTBF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM_TMR

register PWM_TMR
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
alternate_register : PWM
reset_Mask : 0x0

PWM_TMR PWM_TMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PPG_TMR

register PPG_TMR
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
alternate_register : PPG
reset_Mask : 0x0

PPG_TMR PPG_TMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RT_TMR

register RT_TMR
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
alternate_register : RT
reset_Mask : 0x0

RT_TMR RT_TMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWM_TMCR

register PWM_TMCR
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : PWM
reset_Mask : 0x0

PWM_TMCR PWM_TMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STRG CTEN MDSE OSEL FMD EGS PMSK RTGEN CKS2_0

STRG : bitfield STRG
bits : 0 - -1 (0 bit)
access : read-write

CTEN : bitfield CTEN
bits : 1 - 0 (0 bit)
access : read-write

MDSE : bitfield MDSE
bits : 2 - 1 (0 bit)
access : read-write

OSEL : bitfield OSEL
bits : 3 - 2 (0 bit)
access : read-write

FMD : bitfield FMD
bits : 4 - 5 (2 bit)
access : read-write

EGS : bitfield EGS
bits : 8 - 8 (1 bit)
access : read-write

PMSK : bitfield PMSK
bits : 10 - 9 (0 bit)
access : read-write

RTGEN : bitfield RTGEN
bits : 11 - 10 (0 bit)
access : read-write

CKS2_0 : bitfield CKS2_0
bits : 12 - 13 (2 bit)
access : read-write


PPG_TMCR

register PPG_TMCR
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : PPG
reset_Mask : 0x0

PPG_TMCR PPG_TMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STRG CTEN MDSE OSEL FMD EGS PMSK RTGEN CKS2_0

STRG : bitfield STRG
bits : 0 - -1 (0 bit)
access : read-write

CTEN : bitfield CTEN
bits : 1 - 0 (0 bit)
access : read-write

MDSE : bitfield MDSE
bits : 2 - 1 (0 bit)
access : read-write

OSEL : bitfield OSEL
bits : 3 - 2 (0 bit)
access : read-write

FMD : bitfield FMD
bits : 4 - 5 (2 bit)
access : read-write

EGS : bitfield EGS
bits : 8 - 8 (1 bit)
access : read-write

PMSK : bitfield PMSK
bits : 10 - 9 (0 bit)
access : read-write

RTGEN : bitfield RTGEN
bits : 11 - 10 (0 bit)
access : read-write

CKS2_0 : bitfield CKS2_0
bits : 12 - 13 (2 bit)
access : read-write


RT_TMCR

register RT_TMCR
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : RT
reset_Mask : 0x0

RT_TMCR RT_TMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STRG CTEN MDSE OSEL FMD T32 EGS CKS2_0

STRG : bitfield STRG
bits : 0 - -1 (0 bit)
access : read-write

CTEN : bitfield CTEN
bits : 1 - 0 (0 bit)
access : read-write

MDSE : bitfield MDSE
bits : 2 - 1 (0 bit)
access : read-write

OSEL : bitfield OSEL
bits : 3 - 2 (0 bit)
access : read-write

FMD : bitfield FMD
bits : 4 - 5 (2 bit)
access : read-write

T32 : bitfield T32
bits : 7 - 6 (0 bit)
access : read-write

EGS : bitfield EGS
bits : 8 - 8 (1 bit)
access : read-write

CKS2_0 : bitfield CKS2_0
bits : 12 - 13 (2 bit)
access : read-write


PWC_TMCR

register PWC_TMCR
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : PWC
reset_Mask : 0x0

PWC_TMCR PWC_TMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTEN MDSE FMD T32 EGS CKS2_0

CTEN : bitfield CTEN
bits : 1 - 0 (0 bit)
access : read-write

MDSE : bitfield MDSE
bits : 2 - 1 (0 bit)
access : read-write

FMD : bitfield FMD
bits : 4 - 5 (2 bit)
access : read-write

T32 : bitfield T32
bits : 7 - 6 (0 bit)
access : read-write

EGS : bitfield EGS
bits : 8 - 9 (2 bit)
access : read-write

CKS2_0 : bitfield CKS2_0
bits : 12 - 13 (2 bit)
access : read-write



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