\n
address_offset : 0x0 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x14 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x18 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x34 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x38 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x3C Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x44 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x48 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x50 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x54 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x60 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x64 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x68 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection :
System Clock Mode Control Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCRE : High-speed CR clock oscillation enable bit
bits : 0 - -1 (0 bit)
access : read-write
MOSCE : Main clock oscillation enable bit
bits : 1 - 0 (0 bit)
access : read-write
SOSCE : Sub clock oscillation enable bit
bits : 3 - 2 (0 bit)
access : read-write
PLLE : PLL oscillation enable bit
bits : 4 - 3 (0 bit)
access : read-write
RCS : Master clock switch control bits
bits : 5 - 6 (2 bit)
access : read-write
Base Clock Prescaler Register
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BSR : Base clock frequency division ratio setting bits
bits : 0 - 1 (2 bit)
access : read-write
APB0 Prescaler Register
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APBC0 : APB0 bus clock frequency division ratio setting bits
bits : 0 - 0 (1 bit)
access : read-write
APB1 Prescaler Register
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APBC1 : APB1 bus clock frequency division ratio setting bits
bits : 0 - 0 (1 bit)
access : read-write
APBC1RST : APB1 bus reset control bit
bits : 4 - 3 (0 bit)
access : read-write
APBC1EN : APB1 clock enable bit
bits : 7 - 6 (0 bit)
access : read-write
Software Watchdog Clock Prescaler Register
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWDS : Software watchdog clock frequency division ratio setting bits
bits : 0 - 0 (1 bit)
access : read-write
TESTB : TEST bit
bits : 7 - 6 (0 bit)
access : read-write
Clock Stabilization Wait Time Register
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOWT : Main clock stabilization wait time setup bits
bits : 0 - 2 (3 bit)
access : read-write
SOWT : Sub clock stabilization wait time setup bits
bits : 4 - 6 (3 bit)
access : read-write
PLL Clock Stabilization Wait Time Setup Register
address_offset : 0x34 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POWT : Main PLL clock stabilization wait time setup bits
bits : 0 - 1 (2 bit)
access : read-write
PINC : PLL input clock select bit
bits : 4 - 3 (0 bit)
access : read-write
PLL Control Register 1
address_offset : 0x38 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLLM : PLL VCO clock frequency division ratio setting bits
bits : 0 - 2 (3 bit)
access : read-write
PLLK : PLL input clock frequency division ratio setting bits
bits : 4 - 6 (3 bit)
access : read-write
PLL Control Register 2
address_offset : 0x3C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLLN : PLL feedback frequency division ratio setting bits
bits : 0 - 4 (5 bit)
access : read-write
System Clock Mode Status Register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HCRDY : High-speed CR clock oscillation stable bit
bits : 0 - -1 (0 bit)
access : read-only
MORDY : Main clock oscillation stable bit
bits : 1 - 0 (0 bit)
access : read-only
SORDY : Sub clock oscillation stable bit
bits : 3 - 2 (0 bit)
access : read-only
PLRDY : PLL oscillation stable bit
bits : 4 - 3 (0 bit)
access : read-only
RCM : Master clock selection bits
bits : 5 - 6 (2 bit)
access : read-only
CSV Control Register
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCSVE : Main CSV function enable bit
bits : 0 - -1 (0 bit)
access : read-write
SCSVE : Sub CSV function enable bit
bits : 1 - 0 (0 bit)
access : read-write
FCSDE : FCS function enable bit
bits : 8 - 7 (0 bit)
access : read-write
FCSRE : FCS reset output enable bit
bits : 9 - 8 (0 bit)
access : read-write
FCD : FCS count cycle setting bits
bits : 12 - 13 (2 bit)
access : read-write
CSV Status Register
address_offset : 0x44 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MCMF : Main clock failure detection flag
bits : 0 - -1 (0 bit)
access : read-only
SCMF : Sub clock failure detection flag
bits : 1 - 0 (0 bit)
access : read-only
Frequency Detection Window Setting Register (Upper)
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FWH : Frequency detection window setting bits (Upper)
bits : 0 - 14 (15 bit)
access : read-write
Frequency Detection Window Setting Register (Lower)
address_offset : 0x4C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FWL : Frequency detection window setting bits (Lower)
bits : 0 - 14 (15 bit)
access : read-write
Frequency Detection Counter Register
address_offset : 0x50 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FWD : Frequency detection count data
bits : 0 - 14 (15 bit)
access : read-only
Debug Break Watchdog Timer Control Register
address_offset : 0x54 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPSWBE : SW-WDG debug mode break bit
bits : 5 - 4 (0 bit)
access : read-write
DPHWBE : HW-WDG debug mode break bit
bits : 7 - 6 (0 bit)
access : read-write
Interrupt Enable Register
address_offset : 0x60 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCSE : Main clock oscillation stabilization wait completion interrupt enable bit
bits : 0 - -1 (0 bit)
access : read-write
SCSE : Sub clock oscillation stabilization wait completion interrupt enable bit
bits : 1 - 0 (0 bit)
access : read-write
PCSE : PLL oscillation stabilization wait completion interrupt enable bit
bits : 2 - 1 (0 bit)
access : read-write
FCSE : Anomalous frequency detection interrupt enable bit
bits : 5 - 4 (0 bit)
access : read-write
Interrupt Status Register
address_offset : 0x64 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MCSI : Main clock oscillation stabilization wait completion interrupt status bit
bits : 0 - -1 (0 bit)
access : read-only
SCSI : Sub clock oscillation stabilization wait completion interrupt status bit
bits : 1 - 0 (0 bit)
access : read-only
PCSI : PLL oscillation stabilization wait completion interrupt status bit
bits : 2 - 1 (0 bit)
access : read-only
FCSI : Anomalous frequency detection interrupt status bit
bits : 5 - 4 (0 bit)
access : read-only
Interrupt Clear Register
address_offset : 0x68 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
MCSC : Main clock oscillation stabilization wait completion interrupt factor clear bit
bits : 0 - -1 (0 bit)
access : write-only
SCSC : Sub clock oscillation stabilization wait completion interrupt factor clear bit
bits : 1 - 0 (0 bit)
access : write-only
PCSC : PLL oscillation stabilization wait completion interrupt factor clear bit
bits : 2 - 1 (0 bit)
access : write-only
FCSC : Anomalous frequency detection interrupt factor clear bit
bits : 5 - 4 (0 bit)
access : write-only
Standby Mode Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STM : Standby mode select bits
bits : 0 - 0 (1 bit)
access : read-write
DSTM : Deep standby mode select bit
bits : 2 - 1 (0 bit)
access : read-write
SPL : Standby pin level setting bit
bits : 4 - 3 (0 bit)
access : read-write
KEY : Standby mode control write control bits
bits : 16 - 30 (15 bit)
access : read-write
Reset Factor Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PONR : Power-on reset/low-voltage detection reset flag
bits : 0 - -1 (0 bit)
access : read-only
INITX : INITX pin input reset flag
bits : 1 - 0 (0 bit)
access : read-only
SWDT : Software watchdog reset flag
bits : 4 - 3 (0 bit)
access : read-only
HWDT : Hardware watchdog reset flag
bits : 5 - 4 (0 bit)
access : read-only
CSVR : Clock failure detection reset flag
bits : 6 - 5 (0 bit)
access : read-only
FCSR : Flag for anomalous frequency detection reset
bits : 7 - 6 (0 bit)
access : read-only
SRST : Software reset flag
bits : 8 - 7 (0 bit)
access : read-only
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