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HRTIM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x91 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR1

IER

OENR

ODISR

ODSR

BMCR

BMTRG

BMCMPR

BMPER

EECR1

EECR2

EECR3

ADC1R

CR2

ADC2R

ADC3R

ADC4R

DLLCR

FLTINR1

FLTINR2

BDMUPDR

BDTAUPR

BDTBUPR

BDTCUPR

BDTDUPR

BDTEUPR

BDMADR

BDTFUPR

ADCER

ADCUR

ISR

ADCPS1

ADCPS2

FLTINR3

FLTINR4

ICR


CR1

Control Register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MUDIS TAUDIS TBUDIS TCUDIS TDUDIS TEUDIS TFUDIS AD1USRC AD2USRC AD3USRC AD4USRC

MUDIS : Master Update Disable
bits : 0 - 0 (1 bit)

TAUDIS : Timer A Update Disable
bits : 1 - 1 (1 bit)

TBUDIS : Timer B Update Disable
bits : 2 - 2 (1 bit)

TCUDIS : Timer C Update Disable
bits : 3 - 3 (1 bit)

TDUDIS : Timer D Update Disable
bits : 4 - 4 (1 bit)

TEUDIS : Timer E Update Disable
bits : 5 - 5 (1 bit)

TFUDIS : Timer f Update Disable
bits : 6 - 6 (1 bit)

AD1USRC : ADC Trigger 1 Update Source
bits : 16 - 18 (3 bit)

AD2USRC : ADC Trigger 2 Update Source
bits : 19 - 21 (3 bit)

AD3USRC : ADC Trigger 3 Update Source
bits : 22 - 24 (3 bit)

AD4USRC : ADC Trigger 4 Update Source
bits : 25 - 27 (3 bit)


IER

Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLT1IE FLT2IE FLT3IE FLT4IE FLT5IE SYSFLTE FLT6IE DLLRDYIE BMPERIE

FLT1IE : Fault 1 Interrupt Enable
bits : 0 - 0 (1 bit)

FLT2IE : Fault 2 Interrupt Enable
bits : 1 - 1 (1 bit)

FLT3IE : Fault 3 Interrupt Enable
bits : 2 - 2 (1 bit)

FLT4IE : Fault 4 Interrupt Enable
bits : 3 - 3 (1 bit)

FLT5IE : Fault 5 Interrupt Enable
bits : 4 - 4 (1 bit)

SYSFLTE : System Fault Interrupt Enable
bits : 5 - 5 (1 bit)

FLT6IE : Fault 6 Interrupt Enable
bits : 6 - 6 (1 bit)

DLLRDYIE : DLL Ready Interrupt Enable
bits : 16 - 16 (1 bit)

BMPERIE : Burst mode period Interrupt Enable
bits : 17 - 17 (1 bit)


OENR

Output Enable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OENR OENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TA1OEN TA2OEN TB1OEN TB2OEN TC1OEN TC2OEN TD1OEN TD2OEN TE1OEN TE2OEN TF1ODS TF2ODS

TA1OEN : Timer A Output 1 Enable
bits : 0 - 0 (1 bit)

TA2OEN : Timer A Output 2 Enable
bits : 1 - 1 (1 bit)

TB1OEN : Timer B Output 1 Enable
bits : 2 - 2 (1 bit)

TB2OEN : Timer B Output 2 Enable
bits : 3 - 3 (1 bit)

TC1OEN : Timer C Output 1 Enable
bits : 4 - 4 (1 bit)

TC2OEN : Timer C Output 2 Enable
bits : 5 - 5 (1 bit)

TD1OEN : Timer D Output 1 Enable
bits : 6 - 6 (1 bit)

TD2OEN : Timer D Output 2 Enable
bits : 7 - 7 (1 bit)

TE1OEN : Timer E Output 1 Enable
bits : 8 - 8 (1 bit)

TE2OEN : Timer E Output 2 Enable
bits : 9 - 9 (1 bit)

TF1ODS : Timer F Output 1 disable status
bits : 10 - 10 (1 bit)

TF2ODS : Timer F Output 2 disable status
bits : 11 - 11 (1 bit)


ODISR

ODISR
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ODISR ODISR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TA1ODIS TA2ODIS TB1ODIS TB2ODIS TC1ODIS TC2ODIS TD1ODIS TD2ODIS TE1ODIS TE2ODIS TF1ODIS TF2ODIS

TA1ODIS : TA1ODIS
bits : 0 - 0 (1 bit)

TA2ODIS : TA2ODIS
bits : 1 - 1 (1 bit)

TB1ODIS : TB1ODIS
bits : 2 - 2 (1 bit)

TB2ODIS : TB2ODIS
bits : 3 - 3 (1 bit)

TC1ODIS : TC1ODIS
bits : 4 - 4 (1 bit)

TC2ODIS : TC2ODIS
bits : 5 - 5 (1 bit)

TD1ODIS : TD1ODIS
bits : 6 - 6 (1 bit)

TD2ODIS : TD2ODIS
bits : 7 - 7 (1 bit)

TE1ODIS : TE1ODIS
bits : 8 - 8 (1 bit)

TE2ODIS : TE2ODIS
bits : 9 - 9 (1 bit)

TF1ODIS : TF1ODIS
bits : 10 - 10 (1 bit)

TF2ODIS : TF2ODIS
bits : 11 - 11 (1 bit)


ODSR

Output Disable Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ODSR ODSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TA1ODS TA2ODS TB1ODS TB2ODS TC1ODS TC2ODS TD1ODS TD2ODS TE1ODS TE2ODS TF1ODS TF2ODS

TA1ODS : Timer A Output 1 disable status
bits : 0 - 0 (1 bit)

TA2ODS : Timer A Output 2 disable status
bits : 1 - 1 (1 bit)

TB1ODS : Timer B Output 1 disable status
bits : 2 - 2 (1 bit)

TB2ODS : Timer B Output 2 disable status
bits : 3 - 3 (1 bit)

TC1ODS : Timer C Output 1 disable status
bits : 4 - 4 (1 bit)

TC2ODS : Timer C Output 2 disable status
bits : 5 - 5 (1 bit)

TD1ODS : Timer D Output 1 disable status
bits : 6 - 6 (1 bit)

TD2ODS : Timer D Output 2 disable status
bits : 7 - 7 (1 bit)

TE1ODS : Timer E Output 1 disable status
bits : 8 - 8 (1 bit)

TE2ODS : Timer E Output 2 disable status
bits : 9 - 9 (1 bit)

TF1ODS : TF1ODS
bits : 10 - 10 (1 bit)

TF2ODS : TF2ODS
bits : 11 - 11 (1 bit)


BMCR

Burst Mode Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BMCR BMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BME BMOM BMCLK BMPRSC BMPREN MTBM TABM TBBM TCBM TDBM TEBM TFBM BMSTAT

BME : Burst Mode enable
bits : 0 - 0 (1 bit)

BMOM : Burst Mode operating mode
bits : 1 - 1 (1 bit)

BMCLK : Burst Mode Clock source
bits : 2 - 5 (4 bit)

BMPRSC : Burst Mode Prescaler
bits : 6 - 9 (4 bit)

BMPREN : Burst Mode Preload Enable
bits : 10 - 10 (1 bit)

MTBM : Master Timer Burst Mode
bits : 16 - 16 (1 bit)

TABM : Timer A Burst Mode
bits : 17 - 17 (1 bit)

TBBM : Timer B Burst Mode
bits : 18 - 18 (1 bit)

TCBM : Timer C Burst Mode
bits : 19 - 19 (1 bit)

TDBM : Timer D Burst Mode
bits : 20 - 20 (1 bit)

TEBM : Timer E Burst Mode
bits : 21 - 21 (1 bit)

TFBM : Timer f Burst Mode
bits : 22 - 22 (1 bit)

BMSTAT : Burst Mode Status
bits : 31 - 31 (1 bit)


BMTRG

BMTRG
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BMTRG BMTRG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW MSTRST MSTREP MSTCMP1 MSTCMP2 MSTCMP3 MSTCMP4 TARST TAREP TACMP1 TACMP2 TBRST TBREP TBCMP1 TBCMP2 TCRST TCREP TCCMP1 TCCMP2 TDRST TDREP TDCMP1 TDCMP2 TERST TEREP TECMP1 TECMP2 TDEEV7 TDEEV8 EEV7 EEV8 OCHPEV

SW : SW
bits : 0 - 0 (1 bit)

MSTRST : MSTRST
bits : 1 - 1 (1 bit)

MSTREP : MSTREP
bits : 2 - 2 (1 bit)

MSTCMP1 : MSTCMP1
bits : 3 - 3 (1 bit)

MSTCMP2 : MSTCMP2
bits : 4 - 4 (1 bit)

MSTCMP3 : MSTCMP3
bits : 5 - 5 (1 bit)

MSTCMP4 : MSTCMP4
bits : 6 - 6 (1 bit)

TARST : TARST
bits : 7 - 7 (1 bit)

TAREP : TAREP
bits : 8 - 8 (1 bit)

TACMP1 : TACMP1
bits : 9 - 9 (1 bit)

TACMP2 : TACMP2
bits : 10 - 10 (1 bit)

TBRST : TBRST
bits : 11 - 11 (1 bit)

TBREP : TBREP
bits : 12 - 12 (1 bit)

TBCMP1 : TBCMP1
bits : 13 - 13 (1 bit)

TBCMP2 : TBCMP2
bits : 14 - 14 (1 bit)

TCRST : TCRST
bits : 15 - 15 (1 bit)

TCREP : TCREP
bits : 16 - 16 (1 bit)

TCCMP1 : TCCMP1
bits : 17 - 17 (1 bit)

TCCMP2 : TCCMP2
bits : 18 - 18 (1 bit)

TDRST : TDRST
bits : 19 - 19 (1 bit)

TDREP : TDREP
bits : 20 - 20 (1 bit)

TDCMP1 : TDCMP1
bits : 21 - 21 (1 bit)

TDCMP2 : TDCMP2
bits : 22 - 22 (1 bit)

TERST : TERST
bits : 23 - 23 (1 bit)

TEREP : TEREP
bits : 24 - 24 (1 bit)

TECMP1 : TECMP1
bits : 25 - 25 (1 bit)

TECMP2 : TECMP2
bits : 26 - 26 (1 bit)

TDEEV7 : TDEEV7
bits : 27 - 27 (1 bit)

TDEEV8 : TDEEV8
bits : 28 - 28 (1 bit)

EEV7 : EEV7
bits : 29 - 29 (1 bit)

EEV8 : EEV8
bits : 30 - 30 (1 bit)

OCHPEV : OCHPEV
bits : 31 - 31 (1 bit)


BMCMPR

BMCMPR
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BMCMPR BMCMPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BMCMP

BMCMP : BMCMP
bits : 0 - 15 (16 bit)


BMPER

Burst Mode Period Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BMPER BMPER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BMPER

BMPER : Burst mode Period
bits : 0 - 15 (16 bit)


EECR1

Timer External Event Control Register 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EECR1 EECR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EE1SRC EE1POL EE1SNS EE1FAST EE2SRC EE2POL EE2SNS EE2FAST EE3SRC EE3POL EE3SNS EE3FAST EE4SRC EE4POL EE4SNS EE4FAST EE5SRC EE5POL EE5SNS EE5FAST

EE1SRC : External Event 1 Source
bits : 0 - 1 (2 bit)

EE1POL : External Event 1 Polarity
bits : 2 - 2 (1 bit)

EE1SNS : External Event 1 Sensitivity
bits : 3 - 4 (2 bit)

EE1FAST : External Event 1 Fast mode
bits : 5 - 5 (1 bit)

EE2SRC : External Event 2 Source
bits : 6 - 7 (2 bit)

EE2POL : External Event 2 Polarity
bits : 8 - 8 (1 bit)

EE2SNS : External Event 2 Sensitivity
bits : 9 - 10 (2 bit)

EE2FAST : External Event 2 Fast mode
bits : 11 - 11 (1 bit)

EE3SRC : External Event 3 Source
bits : 12 - 13 (2 bit)

EE3POL : External Event 3 Polarity
bits : 14 - 14 (1 bit)

EE3SNS : External Event 3 Sensitivity
bits : 15 - 16 (2 bit)

EE3FAST : External Event 3 Fast mode
bits : 17 - 17 (1 bit)

EE4SRC : External Event 4 Source
bits : 18 - 19 (2 bit)

EE4POL : External Event 4 Polarity
bits : 20 - 20 (1 bit)

EE4SNS : External Event 4 Sensitivity
bits : 21 - 22 (2 bit)

EE4FAST : External Event 4 Fast mode
bits : 23 - 23 (1 bit)

EE5SRC : External Event 5 Source
bits : 24 - 25 (2 bit)

EE5POL : External Event 5 Polarity
bits : 26 - 26 (1 bit)

EE5SNS : External Event 5 Sensitivity
bits : 27 - 28 (2 bit)

EE5FAST : External Event 5 Fast mode
bits : 29 - 29 (1 bit)


EECR2

Timer External Event Control Register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EECR2 EECR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EE6SRC EE6POL EE6SNS EE7SRC EE7POL EE7SNS EE8SRC EE8POL EE8SNS EE9SRC EE9POL EE9SNS EE10SRC EE10POL EE10SNS

EE6SRC : EE6SRC
bits : 0 - 1 (2 bit)

EE6POL : EE6POL
bits : 2 - 2 (1 bit)

EE6SNS : EE6SNS
bits : 3 - 4 (2 bit)

EE7SRC : EE7SRC
bits : 6 - 7 (2 bit)

EE7POL : EE7POL
bits : 8 - 8 (1 bit)

EE7SNS : EE7SNS
bits : 9 - 10 (2 bit)

EE8SRC : EE8SRC
bits : 12 - 13 (2 bit)

EE8POL : EE8POL
bits : 14 - 14 (1 bit)

EE8SNS : EE8SNS
bits : 15 - 16 (2 bit)

EE9SRC : EE9SRC
bits : 18 - 19 (2 bit)

EE9POL : EE9POL
bits : 20 - 20 (1 bit)

EE9SNS : EE9SNS
bits : 21 - 22 (2 bit)

EE10SRC : EE10SRC
bits : 24 - 25 (2 bit)

EE10POL : EE10POL
bits : 26 - 26 (1 bit)

EE10SNS : EE10SNS
bits : 27 - 28 (2 bit)


EECR3

Timer External Event Control Register 3
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EECR3 EECR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EE6F EE7F EE8F EE9F EE10F EEVSD

EE6F : EE6F
bits : 0 - 3 (4 bit)

EE7F : EE7F
bits : 6 - 9 (4 bit)

EE8F : EE8F
bits : 12 - 15 (4 bit)

EE9F : EE9F
bits : 18 - 21 (4 bit)

EE10F : EE10F
bits : 24 - 27 (4 bit)

EEVSD : EEVSD
bits : 30 - 31 (2 bit)


ADC1R

ADC Trigger 1 Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC1R ADC1R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AD1MC1 AD1MC2 AD1MC3 AD1MC4 AD1MPER AD1EEV1 AD1EEV2 AD1EEV3 AD1EEV4 AD1EEV5 AD1TAC2 AD1TAC3 AD1TAC4 AD1TAPER AD1TARST AD1TBC2 AD1TBC3 AD1TBC4 AD1TBPER AD1TBRST AD1TCC2 AD1TCC3 AD1TCC4 AD1TCPER AD1TDC2 AD1TDC3 AD1TDC4 AD1TDPER AD1TEC2 AD1TEC3 AD1TEC4 AD1TEPER

AD1MC1 : ADC trigger 1 on Master Compare 1
bits : 0 - 0 (1 bit)

AD1MC2 : ADC trigger 1 on Master Compare 2
bits : 1 - 1 (1 bit)

AD1MC3 : ADC trigger 1 on Master Compare 3
bits : 2 - 2 (1 bit)

AD1MC4 : ADC trigger 1 on Master Compare 4
bits : 3 - 3 (1 bit)

AD1MPER : ADC trigger 1 on Master Period
bits : 4 - 4 (1 bit)

AD1EEV1 : ADC trigger 1 on External Event 1
bits : 5 - 5 (1 bit)

AD1EEV2 : ADC trigger 1 on External Event 2
bits : 6 - 6 (1 bit)

AD1EEV3 : ADC trigger 1 on External Event 3
bits : 7 - 7 (1 bit)

AD1EEV4 : ADC trigger 1 on External Event 4
bits : 8 - 8 (1 bit)

AD1EEV5 : ADC trigger 1 on External Event 5
bits : 9 - 9 (1 bit)

AD1TAC2 : ADC trigger 1 on Timer A compare 2
bits : 10 - 10 (1 bit)

AD1TAC3 : ADC trigger 1 on Timer A compare 3
bits : 11 - 11 (1 bit)

AD1TAC4 : ADC trigger 1 on Timer A compare 4
bits : 12 - 12 (1 bit)

AD1TAPER : ADC trigger 1 on Timer A Period
bits : 13 - 13 (1 bit)

AD1TARST : ADC trigger 1 on Timer A Reset
bits : 14 - 14 (1 bit)

AD1TBC2 : ADC trigger 1 on Timer B compare 2
bits : 15 - 15 (1 bit)

AD1TBC3 : ADC trigger 1 on Timer B compare 3
bits : 16 - 16 (1 bit)

AD1TBC4 : ADC trigger 1 on Timer B compare 4
bits : 17 - 17 (1 bit)

AD1TBPER : ADC trigger 1 on Timer B Period
bits : 18 - 18 (1 bit)

AD1TBRST : ADC trigger 1 on Timer B Reset
bits : 19 - 19 (1 bit)

AD1TCC2 : ADC trigger 1 on Timer C compare 2
bits : 20 - 20 (1 bit)

AD1TCC3 : ADC trigger 1 on Timer C compare 3
bits : 21 - 21 (1 bit)

AD1TCC4 : ADC trigger 1 on Timer C compare 4
bits : 22 - 22 (1 bit)

AD1TCPER : ADC trigger 1 on Timer C Period
bits : 23 - 23 (1 bit)

AD1TDC2 : ADC trigger 1 on Timer D compare 2
bits : 24 - 24 (1 bit)

AD1TDC3 : ADC trigger 1 on Timer D compare 3
bits : 25 - 25 (1 bit)

AD1TDC4 : ADC trigger 1 on Timer D compare 4
bits : 26 - 26 (1 bit)

AD1TDPER : ADC trigger 1 on Timer D Period
bits : 27 - 27 (1 bit)

AD1TEC2 : ADC trigger 1 on Timer E compare 2
bits : 28 - 28 (1 bit)

AD1TEC3 : ADC trigger 1 on Timer E compare 3
bits : 29 - 29 (1 bit)

AD1TEC4 : ADC trigger 1 on Timer E compare 4
bits : 30 - 30 (1 bit)

AD1TEPER : ADC trigger 1 on Timer E Period
bits : 31 - 31 (1 bit)


CR2

Control Register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSWU TASWU TBSWU TCSWU TDSWU TESWU TFSWU MRST TARST TBRST TCRST TDRST TERST TFRST SWPA SWPB SWPC SWPD SWPE SWPF

MSWU : Master Timer Software update
bits : 0 - 0 (1 bit)

TASWU : Timer A Software update
bits : 1 - 1 (1 bit)

TBSWU : Timer B Software Update
bits : 2 - 2 (1 bit)

TCSWU : Timer C Software Update
bits : 3 - 3 (1 bit)

TDSWU : Timer D Software Update
bits : 4 - 4 (1 bit)

TESWU : Timer E Software Update
bits : 5 - 5 (1 bit)

TFSWU : Timer f Software Update
bits : 6 - 6 (1 bit)

MRST : Master Counter software reset
bits : 8 - 8 (1 bit)

TARST : Timer A counter software reset
bits : 9 - 9 (1 bit)

TBRST : Timer B counter software reset
bits : 10 - 10 (1 bit)

TCRST : Timer C counter software reset
bits : 11 - 11 (1 bit)

TDRST : Timer D counter software reset
bits : 12 - 12 (1 bit)

TERST : Timer E counter software reset
bits : 13 - 13 (1 bit)

TFRST : Timer f counter software reset
bits : 14 - 14 (1 bit)

SWPA : Swap Timer A outputs
bits : 16 - 16 (1 bit)

SWPB : Swap Timer B outputs
bits : 17 - 17 (1 bit)

SWPC : Swap Timer C outputs
bits : 18 - 18 (1 bit)

SWPD : Swap Timer D outputs
bits : 19 - 19 (1 bit)

SWPE : Swap Timer E outputs
bits : 20 - 20 (1 bit)

SWPF : Swap Timer F outputs
bits : 21 - 21 (1 bit)


ADC2R

ADC Trigger 2 Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC2R ADC2R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AD2MC1 AD2MC2 AD2MC3 AD2MC4 AD2MPER AD2EEV6 AD2EEV7 AD2EEV8 AD2EEV9 AD2EEV10 AD2TAC2 AD2TAC3 AD2TAC4 AD2TAPER AD2TBC2 AD2TBC3 AD2TBC4 AD2TBPER AD2TCC2 AD2TCC3 AD2TCC4 AD2TCPER AD2TCRST AD2TDC2 AD2TDC3 AD2TDC4 AD2TDPER AD2TDRST AD2TEC2 AD2TEC3 AD2TEC4 AD2TERST

AD2MC1 : ADC trigger 2 on Master Compare 1
bits : 0 - 0 (1 bit)

AD2MC2 : ADC trigger 2 on Master Compare 2
bits : 1 - 1 (1 bit)

AD2MC3 : ADC trigger 2 on Master Compare 3
bits : 2 - 2 (1 bit)

AD2MC4 : ADC trigger 2 on Master Compare 4
bits : 3 - 3 (1 bit)

AD2MPER : ADC trigger 2 on Master Period
bits : 4 - 4 (1 bit)

AD2EEV6 : ADC trigger 2 on External Event 6
bits : 5 - 5 (1 bit)

AD2EEV7 : ADC trigger 2 on External Event 7
bits : 6 - 6 (1 bit)

AD2EEV8 : ADC trigger 2 on External Event 8
bits : 7 - 7 (1 bit)

AD2EEV9 : ADC trigger 2 on External Event 9
bits : 8 - 8 (1 bit)

AD2EEV10 : ADC trigger 2 on External Event 10
bits : 9 - 9 (1 bit)

AD2TAC2 : ADC trigger 2 on Timer A compare 2
bits : 10 - 10 (1 bit)

AD2TAC3 : ADC trigger 2 on Timer A compare 3
bits : 11 - 11 (1 bit)

AD2TAC4 : ADC trigger 2 on Timer A compare 4
bits : 12 - 12 (1 bit)

AD2TAPER : ADC trigger 2 on Timer A Period
bits : 13 - 13 (1 bit)

AD2TBC2 : ADC trigger 2 on Timer B compare 2
bits : 14 - 14 (1 bit)

AD2TBC3 : ADC trigger 2 on Timer B compare 3
bits : 15 - 15 (1 bit)

AD2TBC4 : ADC trigger 2 on Timer B compare 4
bits : 16 - 16 (1 bit)

AD2TBPER : ADC trigger 2 on Timer B Period
bits : 17 - 17 (1 bit)

AD2TCC2 : ADC trigger 2 on Timer C compare 2
bits : 18 - 18 (1 bit)

AD2TCC3 : ADC trigger 2 on Timer C compare 3
bits : 19 - 19 (1 bit)

AD2TCC4 : ADC trigger 2 on Timer C compare 4
bits : 20 - 20 (1 bit)

AD2TCPER : ADC trigger 2 on Timer C Period
bits : 21 - 21 (1 bit)

AD2TCRST : ADC trigger 2 on Timer C Reset
bits : 22 - 22 (1 bit)

AD2TDC2 : ADC trigger 2 on Timer D compare 2
bits : 23 - 23 (1 bit)

AD2TDC3 : ADC trigger 2 on Timer D compare 3
bits : 24 - 24 (1 bit)

AD2TDC4 : ADC trigger 2 on Timer D compare 4
bits : 25 - 25 (1 bit)

AD2TDPER : ADC trigger 2 on Timer D Period
bits : 26 - 26 (1 bit)

AD2TDRST : ADC trigger 2 on Timer D Reset
bits : 27 - 27 (1 bit)

AD2TEC2 : ADC trigger 2 on Timer E compare 2
bits : 28 - 28 (1 bit)

AD2TEC3 : ADC trigger 2 on Timer E compare 3
bits : 29 - 29 (1 bit)

AD2TEC4 : ADC trigger 2 on Timer E compare 4
bits : 30 - 30 (1 bit)

AD2TERST : ADC trigger 2 on Timer E Reset
bits : 31 - 31 (1 bit)


ADC3R

ADC Trigger 3 Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC3R ADC3R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AD1MC1 AD1MC2 AD1MC3 AD1MC4 AD1MPER AD1EEV1 AD1EEV2 AD1EEV3 AD1EEV4 AD1EEV5 AD1TAC2 AD1TAC3 AD1TAC4 AD1TAPER AD1TARST AD1TBC2 AD1TBC3 AD1TBC4 AD1TBPER AD1TBRST AD1TCC2 AD1TCC3 AD1TCC4 AD1TCPER AD1TDC2 AD1TDC3 AD1TDC4 AD1TDPER AD1TEC2 AD1TEC3 AD1TEC4 AD1TEPER

AD1MC1 : AD1MC1
bits : 0 - 0 (1 bit)

AD1MC2 : AD1MC2
bits : 1 - 1 (1 bit)

AD1MC3 : AD1MC3
bits : 2 - 2 (1 bit)

AD1MC4 : AD1MC4
bits : 3 - 3 (1 bit)

AD1MPER : AD1MPER
bits : 4 - 4 (1 bit)

AD1EEV1 : AD1EEV1
bits : 5 - 5 (1 bit)

AD1EEV2 : AD1EEV2
bits : 6 - 6 (1 bit)

AD1EEV3 : AD1EEV3
bits : 7 - 7 (1 bit)

AD1EEV4 : AD1EEV4
bits : 8 - 8 (1 bit)

AD1EEV5 : AD1EEV5
bits : 9 - 9 (1 bit)

AD1TAC2 : AD1TAC2
bits : 10 - 10 (1 bit)

AD1TAC3 : AD1TAC3
bits : 11 - 11 (1 bit)

AD1TAC4 : AD1TAC4
bits : 12 - 12 (1 bit)

AD1TAPER : AD1TAPER
bits : 13 - 13 (1 bit)

AD1TARST : AD1TARST
bits : 14 - 14 (1 bit)

AD1TBC2 : AD1TBC2
bits : 15 - 15 (1 bit)

AD1TBC3 : AD1TBC3
bits : 16 - 16 (1 bit)

AD1TBC4 : AD1TBC4
bits : 17 - 17 (1 bit)

AD1TBPER : AD1TBPER
bits : 18 - 18 (1 bit)

AD1TBRST : AD1TBRST
bits : 19 - 19 (1 bit)

AD1TCC2 : AD1TCC2
bits : 20 - 20 (1 bit)

AD1TCC3 : AD1TCC3
bits : 21 - 21 (1 bit)

AD1TCC4 : AD1TCC4
bits : 22 - 22 (1 bit)

AD1TCPER : AD1TCPER
bits : 23 - 23 (1 bit)

AD1TDC2 : AD1TDC2
bits : 24 - 24 (1 bit)

AD1TDC3 : AD1TDC3
bits : 25 - 25 (1 bit)

AD1TDC4 : AD1TDC4
bits : 26 - 26 (1 bit)

AD1TDPER : AD1TDPER
bits : 27 - 27 (1 bit)

AD1TEC2 : AD1TEC2
bits : 28 - 28 (1 bit)

AD1TEC3 : AD1TEC3
bits : 29 - 29 (1 bit)

AD1TEC4 : AD1TEC4
bits : 30 - 30 (1 bit)

AD1TEPER : AD1TEPER
bits : 31 - 31 (1 bit)


ADC4R

ADC Trigger 4 Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC4R ADC4R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AD2MC1 AD2MC2 AD2MC3 AD2MC4 AD2MPER AD2EEV6 AD2EEV7 AD2EEV8 AD2EEV9 AD2EEV10 AD2TAC2 AD2TAC3 AD2TAC4 AD2TAPER AD2TBC2 AD2TBC3 AD2TBC4 AD2TBPER AD2TCC2 AD2TCC3 AD2TCC4 AD2TCPER AD2TCRST AD2TDC2 AD2TDC3 AD2TDC4 AD2TDPER AD2TDRST AD2TEC2 AD2TEC3 AD2TEC4 AD2TERST

AD2MC1 : AD2MC1
bits : 0 - 0 (1 bit)

AD2MC2 : AD2MC2
bits : 1 - 1 (1 bit)

AD2MC3 : AD2MC3
bits : 2 - 2 (1 bit)

AD2MC4 : AD2MC4
bits : 3 - 3 (1 bit)

AD2MPER : AD2MPER
bits : 4 - 4 (1 bit)

AD2EEV6 : AD2EEV6
bits : 5 - 5 (1 bit)

AD2EEV7 : AD2EEV7
bits : 6 - 6 (1 bit)

AD2EEV8 : AD2EEV8
bits : 7 - 7 (1 bit)

AD2EEV9 : AD2EEV9
bits : 8 - 8 (1 bit)

AD2EEV10 : AD2EEV10
bits : 9 - 9 (1 bit)

AD2TAC2 : AD2TAC2
bits : 10 - 10 (1 bit)

AD2TAC3 : AD2TAC3
bits : 11 - 11 (1 bit)

AD2TAC4 : AD2TAC4
bits : 12 - 12 (1 bit)

AD2TAPER : AD2TAPER
bits : 13 - 13 (1 bit)

AD2TBC2 : AD2TBC2
bits : 14 - 14 (1 bit)

AD2TBC3 : AD2TBC3
bits : 15 - 15 (1 bit)

AD2TBC4 : AD2TBC4
bits : 16 - 16 (1 bit)

AD2TBPER : AD2TBPER
bits : 17 - 17 (1 bit)

AD2TCC2 : AD2TCC2
bits : 18 - 18 (1 bit)

AD2TCC3 : AD2TCC3
bits : 19 - 19 (1 bit)

AD2TCC4 : AD2TCC4
bits : 20 - 20 (1 bit)

AD2TCPER : AD2TCPER
bits : 21 - 21 (1 bit)

AD2TCRST : AD2TCRST
bits : 22 - 22 (1 bit)

AD2TDC2 : AD2TDC2
bits : 23 - 23 (1 bit)

AD2TDC3 : AD2TDC3
bits : 24 - 24 (1 bit)

AD2TDC4 : AD2TDC4
bits : 25 - 25 (1 bit)

AD2TDPER : AD2TDPER
bits : 26 - 26 (1 bit)

AD2TDRST : AD2TDRST
bits : 27 - 27 (1 bit)

AD2TEC2 : AD2TEC2
bits : 28 - 28 (1 bit)

AD2TEC3 : AD2TEC3
bits : 29 - 29 (1 bit)

AD2TEC4 : AD2TEC4
bits : 30 - 30 (1 bit)

AD2TERST : AD2TERST
bits : 31 - 31 (1 bit)


DLLCR

DLL Control Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLLCR DLLCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAL CALEN CALRTE

CAL : DLL Calibration Start
bits : 0 - 0 (1 bit)

CALEN : DLL Calibration Enable
bits : 1 - 1 (1 bit)

CALRTE : DLL Calibration rate
bits : 2 - 3 (2 bit)


FLTINR1

HRTIM Fault Input Register 1
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLTINR1 FLTINR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLT1E FLT1P FLT1SRC FLT1F FLT1LCK FLT2E FLT2P FLT2SRC FLT2F FLT2LCK FLT3E FLT3P FLT3SRC FLT3F FLT3LCK FLT4E FLT4P FLT4SRC FLT4F FLT4LCK

FLT1E : FLT1E
bits : 0 - 0 (1 bit)

FLT1P : FLT1P
bits : 1 - 1 (1 bit)

FLT1SRC : FLT1SRC
bits : 2 - 2 (1 bit)

FLT1F : FLT1F
bits : 3 - 6 (4 bit)

FLT1LCK : FLT1LCK
bits : 7 - 7 (1 bit)

FLT2E : FLT2E
bits : 8 - 8 (1 bit)

FLT2P : FLT2P
bits : 9 - 9 (1 bit)

FLT2SRC : FLT2SRC
bits : 10 - 10 (1 bit)

FLT2F : FLT2F
bits : 11 - 14 (4 bit)

FLT2LCK : FLT2LCK
bits : 15 - 15 (1 bit)

FLT3E : FLT3E
bits : 16 - 16 (1 bit)

FLT3P : FLT3P
bits : 17 - 17 (1 bit)

FLT3SRC : FLT3SRC
bits : 18 - 18 (1 bit)

FLT3F : FLT3F
bits : 19 - 22 (4 bit)

FLT3LCK : FLT3LCK
bits : 23 - 23 (1 bit)

FLT4E : FLT4E
bits : 24 - 24 (1 bit)

FLT4P : FLT4P
bits : 25 - 25 (1 bit)

FLT4SRC : FLT4SRC
bits : 26 - 26 (1 bit)

FLT4F : FLT4F
bits : 27 - 30 (4 bit)

FLT4LCK : FLT4LCK
bits : 31 - 31 (1 bit)


FLTINR2

HRTIM Fault Input Register 2
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLTINR2 FLTINR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLT5E FLT5P FLT5SRC FLT5F FLT5LCK FLT6E FLT6P FLT6SRC_0 FLT6F FLT6LCK FLT1SRC_1 FLT2SRC_1 FLT3SRC_1 FLT4SRC_1 FLT5SRC_1 FLT6SRC_1 FLTSD

FLT5E : FLT5E
bits : 0 - 0 (1 bit)

FLT5P : FLT5P
bits : 1 - 1 (1 bit)

FLT5SRC : FLT5SRC
bits : 2 - 2 (1 bit)

FLT5F : FLT5F
bits : 3 - 6 (4 bit)

FLT5LCK : FLT5LCK
bits : 7 - 7 (1 bit)

FLT6E : FLT6E
bits : 8 - 8 (1 bit)

FLT6P : FLT6P
bits : 9 - 9 (1 bit)

FLT6SRC_0 : FLT6F
bits : 10 - 10 (1 bit)

FLT6F : FLT6F
bits : 11 - 14 (4 bit)

FLT6LCK : FLT6LCK
bits : 15 - 15 (1 bit)

FLT1SRC_1 : FLT1SRC_1
bits : 16 - 16 (1 bit)

FLT2SRC_1 : FLT2SRC_1
bits : 17 - 17 (1 bit)

FLT3SRC_1 : FLT3SRC_1
bits : 18 - 18 (1 bit)

FLT4SRC_1 : FLT4SRC_1
bits : 19 - 19 (1 bit)

FLT5SRC_1 : FLT5SRC_1
bits : 20 - 20 (1 bit)

FLT6SRC_1 : FLT6SRC
bits : 21 - 21 (1 bit)

FLTSD : FLTSD
bits : 24 - 25 (2 bit)


BDMUPDR

BDMUPDR
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDMUPDR BDMUPDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCR MICR MDIER MCNT MPER MREP MCMP1 MCMP2 MCMP3 MCMP4

MCR : MCR
bits : 0 - 0 (1 bit)

MICR : MICR
bits : 1 - 1 (1 bit)

MDIER : MDIER
bits : 2 - 2 (1 bit)

MCNT : MCNT
bits : 3 - 3 (1 bit)

MPER : MPER
bits : 4 - 4 (1 bit)

MREP : MREP
bits : 5 - 5 (1 bit)

MCMP1 : MCMP1
bits : 6 - 6 (1 bit)

MCMP2 : MCMP2
bits : 7 - 7 (1 bit)

MCMP3 : MCMP3
bits : 8 - 8 (1 bit)

MCMP4 : MCMP4
bits : 9 - 9 (1 bit)


BDTAUPR

Burst DMA Timerx update Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDTAUPR BDTAUPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMxCR TIMxICR TIMxDIER TIMxCNT TIMxPER TIMxREP TIMxCMP1 TIMxCMP2 TIMxCMP3 TIMxCMP4 TIMx_DTxR TIMxSET1R TIMxRST1R TIMxSET2R TIMxRST2R TIMxEEFR1 TIMxEEFR2 TIMxRSTR TIMxCHPR TIMxOUTR TIMxFLTR TIMxCR2 TIMxEEFR3

TIMxCR : HRTIM_TIMxCR register update enable
bits : 0 - 0 (1 bit)

TIMxICR : HRTIM_TIMxICR register update enable
bits : 1 - 1 (1 bit)

TIMxDIER : HRTIM_TIMxDIER register update enable
bits : 2 - 2 (1 bit)

TIMxCNT : HRTIM_CNTxR register update enable
bits : 3 - 3 (1 bit)

TIMxPER : HRTIM_PERxR register update enable
bits : 4 - 4 (1 bit)

TIMxREP : HRTIM_REPxR register update enable
bits : 5 - 5 (1 bit)

TIMxCMP1 : HRTIM_CMP1xR register update enable
bits : 6 - 6 (1 bit)

TIMxCMP2 : HRTIM_CMP2xR register update enable
bits : 7 - 7 (1 bit)

TIMxCMP3 : HRTIM_CMP3xR register update enable
bits : 8 - 8 (1 bit)

TIMxCMP4 : HRTIM_CMP4xR register update enable
bits : 9 - 9 (1 bit)

TIMx_DTxR : HRTIM_DTxR register update enable
bits : 10 - 10 (1 bit)

TIMxSET1R : HRTIM_SET1xR register update enable
bits : 11 - 11 (1 bit)

TIMxRST1R : HRTIM_RST1xR register update enable
bits : 12 - 12 (1 bit)

TIMxSET2R : HRTIM_SET2xR register update enable
bits : 13 - 13 (1 bit)

TIMxRST2R : HRTIM_RST2xR register update enable
bits : 14 - 14 (1 bit)

TIMxEEFR1 : HRTIM_EEFxR1 register update enable
bits : 15 - 15 (1 bit)

TIMxEEFR2 : HRTIM_EEFxR2 register update enable
bits : 16 - 16 (1 bit)

TIMxRSTR : HRTIM_RSTxR register update enable
bits : 17 - 17 (1 bit)

TIMxCHPR : HRTIM_CHPxR register update enable
bits : 18 - 18 (1 bit)

TIMxOUTR : HRTIM_OUTxR register update enable
bits : 19 - 19 (1 bit)

TIMxFLTR : HRTIM_FLTxR register update enable
bits : 20 - 20 (1 bit)

TIMxCR2 : TIMxCR2
bits : 21 - 21 (1 bit)

TIMxEEFR3 : TIMxEEFR3
bits : 22 - 22 (1 bit)


BDTBUPR

Burst DMA Timerx update Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDTBUPR BDTBUPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMxCR TIMxICR TIMxDIER TIMxCNT TIMxPER TIMxREP TIMxCMP1 TIMxCMP2 TIMxCMP3 TIMxCMP4 TIMx_DTxR TIMxSET1R TIMxRST1R TIMxSET2R TIMxRST2R TIMxEEFR1 TIMxEEFR2 TIMxRSTR TIMxCHPR TIMxOUTR TIMxFLTR TIMxCR2 TIMxEEFR3

TIMxCR : HRTIM_TIMxCR register update enable
bits : 0 - 0 (1 bit)

TIMxICR : HRTIM_TIMxICR register update enable
bits : 1 - 1 (1 bit)

TIMxDIER : HRTIM_TIMxDIER register update enable
bits : 2 - 2 (1 bit)

TIMxCNT : HRTIM_CNTxR register update enable
bits : 3 - 3 (1 bit)

TIMxPER : HRTIM_PERxR register update enable
bits : 4 - 4 (1 bit)

TIMxREP : HRTIM_REPxR register update enable
bits : 5 - 5 (1 bit)

TIMxCMP1 : HRTIM_CMP1xR register update enable
bits : 6 - 6 (1 bit)

TIMxCMP2 : HRTIM_CMP2xR register update enable
bits : 7 - 7 (1 bit)

TIMxCMP3 : HRTIM_CMP3xR register update enable
bits : 8 - 8 (1 bit)

TIMxCMP4 : HRTIM_CMP4xR register update enable
bits : 9 - 9 (1 bit)

TIMx_DTxR : HRTIM_DTxR register update enable
bits : 10 - 10 (1 bit)

TIMxSET1R : HRTIM_SET1xR register update enable
bits : 11 - 11 (1 bit)

TIMxRST1R : HRTIM_RST1xR register update enable
bits : 12 - 12 (1 bit)

TIMxSET2R : HRTIM_SET2xR register update enable
bits : 13 - 13 (1 bit)

TIMxRST2R : HRTIM_RST2xR register update enable
bits : 14 - 14 (1 bit)

TIMxEEFR1 : HRTIM_EEFxR1 register update enable
bits : 15 - 15 (1 bit)

TIMxEEFR2 : HRTIM_EEFxR2 register update enable
bits : 16 - 16 (1 bit)

TIMxRSTR : HRTIM_RSTxR register update enable
bits : 17 - 17 (1 bit)

TIMxCHPR : HRTIM_CHPxR register update enable
bits : 18 - 18 (1 bit)

TIMxOUTR : HRTIM_OUTxR register update enable
bits : 19 - 19 (1 bit)

TIMxFLTR : HRTIM_FLTxR register update enable
bits : 20 - 20 (1 bit)

TIMxCR2 : TIMxCR2
bits : 21 - 21 (1 bit)

TIMxEEFR3 : TIMxEEFR3
bits : 22 - 22 (1 bit)


BDTCUPR

Burst DMA Timerx update Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDTCUPR BDTCUPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMxCR TIMxICR TIMxDIER TIMxCNT TIMxPER TIMxREP TIMxCMP1 TIMxCMP2 TIMxCMP3 TIMxCMP4 TIMx_DTxR TIMxSET1R TIMxRST1R TIMxSET2R TIMxRST2R TIMxEEFR1 TIMxEEFR2 TIMxRSTR TIMxCHPR TIMxOUTR TIMxFLTR TIMxCR2 TIMxEEFR3

TIMxCR : HRTIM_TIMxCR register update enable
bits : 0 - 0 (1 bit)

TIMxICR : HRTIM_TIMxICR register update enable
bits : 1 - 1 (1 bit)

TIMxDIER : HRTIM_TIMxDIER register update enable
bits : 2 - 2 (1 bit)

TIMxCNT : HRTIM_CNTxR register update enable
bits : 3 - 3 (1 bit)

TIMxPER : HRTIM_PERxR register update enable
bits : 4 - 4 (1 bit)

TIMxREP : HRTIM_REPxR register update enable
bits : 5 - 5 (1 bit)

TIMxCMP1 : HRTIM_CMP1xR register update enable
bits : 6 - 6 (1 bit)

TIMxCMP2 : HRTIM_CMP2xR register update enable
bits : 7 - 7 (1 bit)

TIMxCMP3 : HRTIM_CMP3xR register update enable
bits : 8 - 8 (1 bit)

TIMxCMP4 : HRTIM_CMP4xR register update enable
bits : 9 - 9 (1 bit)

TIMx_DTxR : HRTIM_DTxR register update enable
bits : 10 - 10 (1 bit)

TIMxSET1R : HRTIM_SET1xR register update enable
bits : 11 - 11 (1 bit)

TIMxRST1R : HRTIM_RST1xR register update enable
bits : 12 - 12 (1 bit)

TIMxSET2R : HRTIM_SET2xR register update enable
bits : 13 - 13 (1 bit)

TIMxRST2R : HRTIM_RST2xR register update enable
bits : 14 - 14 (1 bit)

TIMxEEFR1 : HRTIM_EEFxR1 register update enable
bits : 15 - 15 (1 bit)

TIMxEEFR2 : HRTIM_EEFxR2 register update enable
bits : 16 - 16 (1 bit)

TIMxRSTR : HRTIM_RSTxR register update enable
bits : 17 - 17 (1 bit)

TIMxCHPR : HRTIM_CHPxR register update enable
bits : 18 - 18 (1 bit)

TIMxOUTR : HRTIM_OUTxR register update enable
bits : 19 - 19 (1 bit)

TIMxFLTR : HRTIM_FLTxR register update enable
bits : 20 - 20 (1 bit)

TIMxCR2 : TIMxCR2
bits : 21 - 21 (1 bit)

TIMxEEFR3 : TIMxEEFR3
bits : 22 - 22 (1 bit)


BDTDUPR

Burst DMA Timerx update Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDTDUPR BDTDUPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMxCR TIMxICR TIMxDIER TIMxCNT TIMxPER TIMxREP TIMxCMP1 TIMxCMP2 TIMxCMP3 TIMxCMP4 TIMx_DTxR TIMxSET1R TIMxRST1R TIMxSET2R TIMxRST2R TIMxEEFR1 TIMxEEFR2 TIMxRSTR TIMxCHPR TIMxOUTR TIMxFLTR TIMxCR2 TIMxEEFR3

TIMxCR : HRTIM_TIMxCR register update enable
bits : 0 - 0 (1 bit)

TIMxICR : HRTIM_TIMxICR register update enable
bits : 1 - 1 (1 bit)

TIMxDIER : HRTIM_TIMxDIER register update enable
bits : 2 - 2 (1 bit)

TIMxCNT : HRTIM_CNTxR register update enable
bits : 3 - 3 (1 bit)

TIMxPER : HRTIM_PERxR register update enable
bits : 4 - 4 (1 bit)

TIMxREP : HRTIM_REPxR register update enable
bits : 5 - 5 (1 bit)

TIMxCMP1 : HRTIM_CMP1xR register update enable
bits : 6 - 6 (1 bit)

TIMxCMP2 : HRTIM_CMP2xR register update enable
bits : 7 - 7 (1 bit)

TIMxCMP3 : HRTIM_CMP3xR register update enable
bits : 8 - 8 (1 bit)

TIMxCMP4 : HRTIM_CMP4xR register update enable
bits : 9 - 9 (1 bit)

TIMx_DTxR : HRTIM_DTxR register update enable
bits : 10 - 10 (1 bit)

TIMxSET1R : HRTIM_SET1xR register update enable
bits : 11 - 11 (1 bit)

TIMxRST1R : HRTIM_RST1xR register update enable
bits : 12 - 12 (1 bit)

TIMxSET2R : HRTIM_SET2xR register update enable
bits : 13 - 13 (1 bit)

TIMxRST2R : HRTIM_RST2xR register update enable
bits : 14 - 14 (1 bit)

TIMxEEFR1 : HRTIM_EEFxR1 register update enable
bits : 15 - 15 (1 bit)

TIMxEEFR2 : HRTIM_EEFxR2 register update enable
bits : 16 - 16 (1 bit)

TIMxRSTR : HRTIM_RSTxR register update enable
bits : 17 - 17 (1 bit)

TIMxCHPR : HRTIM_CHPxR register update enable
bits : 18 - 18 (1 bit)

TIMxOUTR : HRTIM_OUTxR register update enable
bits : 19 - 19 (1 bit)

TIMxFLTR : HRTIM_FLTxR register update enable
bits : 20 - 20 (1 bit)

TIMxCR2 : TIMxCR2
bits : 21 - 21 (1 bit)

TIMxEEFR3 : TIMxEEFR3
bits : 22 - 22 (1 bit)


BDTEUPR

Burst DMA Timerx update Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDTEUPR BDTEUPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMxCR TIMxICR TIMxDIER TIMxCNT TIMxPER TIMxREP TIMxCMP1 TIMxCMP2 TIMxCMP3 TIMxCMP4 TIMx_DTxR TIMxSET1R TIMxRST1R TIMxSET2R TIMxRST2R TIMxEEFR1 TIMxEEFR2 TIMxRSTR TIMxCHPR TIMxOUTR TIMxFLTR TIMxCR2 TIMxEEFR3

TIMxCR : HRTIM_TIMxCR register update enable
bits : 0 - 0 (1 bit)

TIMxICR : HRTIM_TIMxICR register update enable
bits : 1 - 1 (1 bit)

TIMxDIER : HRTIM_TIMxDIER register update enable
bits : 2 - 2 (1 bit)

TIMxCNT : HRTIM_CNTxR register update enable
bits : 3 - 3 (1 bit)

TIMxPER : HRTIM_PERxR register update enable
bits : 4 - 4 (1 bit)

TIMxREP : HRTIM_REPxR register update enable
bits : 5 - 5 (1 bit)

TIMxCMP1 : HRTIM_CMP1xR register update enable
bits : 6 - 6 (1 bit)

TIMxCMP2 : HRTIM_CMP2xR register update enable
bits : 7 - 7 (1 bit)

TIMxCMP3 : HRTIM_CMP3xR register update enable
bits : 8 - 8 (1 bit)

TIMxCMP4 : HRTIM_CMP4xR register update enable
bits : 9 - 9 (1 bit)

TIMx_DTxR : HRTIM_DTxR register update enable
bits : 10 - 10 (1 bit)

TIMxSET1R : HRTIM_SET1xR register update enable
bits : 11 - 11 (1 bit)

TIMxRST1R : HRTIM_RST1xR register update enable
bits : 12 - 12 (1 bit)

TIMxSET2R : HRTIM_SET2xR register update enable
bits : 13 - 13 (1 bit)

TIMxRST2R : HRTIM_RST2xR register update enable
bits : 14 - 14 (1 bit)

TIMxEEFR1 : HRTIM_EEFxR1 register update enable
bits : 15 - 15 (1 bit)

TIMxEEFR2 : HRTIM_EEFxR2 register update enable
bits : 16 - 16 (1 bit)

TIMxRSTR : HRTIM_RSTxR register update enable
bits : 17 - 17 (1 bit)

TIMxCHPR : HRTIM_CHPxR register update enable
bits : 18 - 18 (1 bit)

TIMxOUTR : HRTIM_OUTxR register update enable
bits : 19 - 19 (1 bit)

TIMxFLTR : HRTIM_FLTxR register update enable
bits : 20 - 20 (1 bit)

TIMxCR2 : TIMxCR2
bits : 21 - 21 (1 bit)

TIMxEEFR3 : TIMxEEFR3
bits : 22 - 22 (1 bit)


BDMADR

Burst DMA Data Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

BDMADR BDMADR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BDMADR

BDMADR : Burst DMA Data register
bits : 0 - 31 (32 bit)


BDTFUPR

Burst DMA Timerx update Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDTFUPR BDTFUPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMxCR TIMxICR TIMxDIER TIMxCNT TIMxPER TIMxREP TIMxCMP1 TIMxCMP2 TIMxCMP3 TIMxCMP4 TIMx_DTxR TIMxSET1R TIMxRST1R TIMxSET2R TIMxRST2R TIMxEEFR1 TIMxEEFR2 TIMxRSTR TIMxCHPR TIMxOUTR TIMxFLTR TIMxCR2 TIMxEEFR3

TIMxCR : HRTIM_TIMxCR register update enable
bits : 0 - 0 (1 bit)

TIMxICR : HRTIM_TIMxICR register update enable
bits : 1 - 1 (1 bit)

TIMxDIER : HRTIM_TIMxDIER register update enable
bits : 2 - 2 (1 bit)

TIMxCNT : HRTIM_CNTxR register update enable
bits : 3 - 3 (1 bit)

TIMxPER : HRTIM_PERxR register update enable
bits : 4 - 4 (1 bit)

TIMxREP : HRTIM_REPxR register update enable
bits : 5 - 5 (1 bit)

TIMxCMP1 : HRTIM_CMP1xR register update enable
bits : 6 - 6 (1 bit)

TIMxCMP2 : HRTIM_CMP2xR register update enable
bits : 7 - 7 (1 bit)

TIMxCMP3 : HRTIM_CMP3xR register update enable
bits : 8 - 8 (1 bit)

TIMxCMP4 : HRTIM_CMP4xR register update enable
bits : 9 - 9 (1 bit)

TIMx_DTxR : HRTIM_DTxR register update enable
bits : 10 - 10 (1 bit)

TIMxSET1R : HRTIM_SET1xR register update enable
bits : 11 - 11 (1 bit)

TIMxRST1R : HRTIM_RST1xR register update enable
bits : 12 - 12 (1 bit)

TIMxSET2R : HRTIM_SET2xR register update enable
bits : 13 - 13 (1 bit)

TIMxRST2R : HRTIM_RST2xR register update enable
bits : 14 - 14 (1 bit)

TIMxEEFR1 : HRTIM_EEFxR1 register update enable
bits : 15 - 15 (1 bit)

TIMxEEFR2 : HRTIM_EEFxR2 register update enable
bits : 16 - 16 (1 bit)

TIMxRSTR : HRTIM_RSTxR register update enable
bits : 17 - 17 (1 bit)

TIMxCHPR : HRTIM_CHPxR register update enable
bits : 18 - 18 (1 bit)

TIMxOUTR : HRTIM_OUTxR register update enable
bits : 19 - 19 (1 bit)

TIMxFLTR : HRTIM_FLTxR register update enable
bits : 20 - 20 (1 bit)

TIMxCR2 : TIMxCR2
bits : 21 - 21 (1 bit)

TIMxEEFR3 : TIMxEEFR3
bits : 22 - 22 (1 bit)


ADCER

HRTIM ADC Extended Trigger Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCER ADCER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC5TRG ADC6TRG ADC7TRG ADC8TRG ADC9TRG ADC10TRG

ADC5TRG : ADC5TRG
bits : 0 - 4 (5 bit)

ADC6TRG : ADC6TRG
bits : 5 - 9 (5 bit)

ADC7TRG : ADC7TRG
bits : 10 - 14 (5 bit)

ADC8TRG : ADC8TRG
bits : 16 - 20 (5 bit)

ADC9TRG : ADC9TRG
bits : 21 - 25 (5 bit)

ADC10TRG : ADC10TRG
bits : 26 - 30 (5 bit)


ADCUR

HRTIM ADC Trigger Update Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCUR ADCUR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AD5USRC AD6USRC AD7USRC AD8USRC AD9USRC AD10USRC

AD5USRC : AD5USRC
bits : 0 - 2 (3 bit)

AD6USRC : AD6USRC
bits : 4 - 6 (3 bit)

AD7USRC : AD7USRC
bits : 8 - 10 (3 bit)

AD8USRC : AD8USRC
bits : 12 - 14 (3 bit)

AD9USRC : AD9USRC
bits : 16 - 18 (3 bit)

AD10USRC : AD10USRC
bits : 20 - 22 (3 bit)


ISR

Interrupt Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLT1 FLT2 FLT3 FLT4 FLT5 SYSFLT FLT6 DLLRDY BMPER

FLT1 : Fault 1 Interrupt Flag
bits : 0 - 0 (1 bit)

FLT2 : Fault 2 Interrupt Flag
bits : 1 - 1 (1 bit)

FLT3 : Fault 3 Interrupt Flag
bits : 2 - 2 (1 bit)

FLT4 : Fault 4 Interrupt Flag
bits : 3 - 3 (1 bit)

FLT5 : Fault 5 Interrupt Flag
bits : 4 - 4 (1 bit)

SYSFLT : System Fault Interrupt Flag
bits : 5 - 5 (1 bit)

FLT6 : Fault 6 Interrupt Flag
bits : 6 - 6 (1 bit)

DLLRDY : DLL Ready Interrupt Flag
bits : 16 - 16 (1 bit)

BMPER : Burst mode Period Interrupt Flag
bits : 17 - 17 (1 bit)


ADCPS1

HRTIM ADC Post Scaler Register 1
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCPS1 ADCPS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC1PSC ADC2PSC ADC3PSC ADC4PSC ADC5PSC

ADC1PSC : ADC1PSC
bits : 0 - 4 (5 bit)

ADC2PSC : ADC2PSC
bits : 6 - 10 (5 bit)

ADC3PSC : ADC3PSC
bits : 12 - 16 (5 bit)

ADC4PSC : ADC4PSC
bits : 18 - 22 (5 bit)

ADC5PSC : ADC5PSC
bits : 24 - 28 (5 bit)


ADCPS2

HRTIM ADC Post Scaler Register 2
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCPS2 ADCPS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC6PSC ADC7PSC ADC8PSC ADC9PSC ADC10PSC

ADC6PSC : ADC6PSC
bits : 0 - 4 (5 bit)

ADC7PSC : ADC7PSC
bits : 6 - 10 (5 bit)

ADC8PSC : ADC8PSC
bits : 12 - 16 (5 bit)

ADC9PSC : ADC9PSC
bits : 18 - 22 (5 bit)

ADC10PSC : ADC10PSC
bits : 24 - 28 (5 bit)


FLTINR3

HRTIM Fault Input Register 3
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLTINR3 FLTINR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLT1BLKE FLT1BLKS FLT1CNT FLT1CRES FLT1RSTM FLT2BLKE FLT2BLKS FLT2CNT FLT2CRES FLT2RSTM FLT3BLKE FLT3BLKS FLT3CNT FLT3CRES FLT3RSTM FLT4BLKE FLT4BLKS FLT4CNT FLT4CRES FLT4RSTM

FLT1BLKE : FLT1BLKE
bits : 0 - 0 (1 bit)

FLT1BLKS : FLT1BLKS
bits : 1 - 1 (1 bit)

FLT1CNT : FLT1CNT
bits : 2 - 5 (4 bit)

FLT1CRES : FLT1CRES
bits : 6 - 6 (1 bit)

FLT1RSTM : FLT1RSTM
bits : 7 - 7 (1 bit)

FLT2BLKE : FLT2BLKE
bits : 8 - 8 (1 bit)

FLT2BLKS : FLT2BLKS
bits : 9 - 9 (1 bit)

FLT2CNT : FLT2CNT
bits : 10 - 13 (4 bit)

FLT2CRES : FLT2CRES
bits : 14 - 14 (1 bit)

FLT2RSTM : FLT2RSTM
bits : 15 - 15 (1 bit)

FLT3BLKE : FLT3BLKE
bits : 16 - 16 (1 bit)

FLT3BLKS : FLT3BLKS
bits : 17 - 17 (1 bit)

FLT3CNT : FLT3CNT
bits : 18 - 21 (4 bit)

FLT3CRES : FLT3CRES
bits : 22 - 22 (1 bit)

FLT3RSTM : FLT3RSTM
bits : 23 - 23 (1 bit)

FLT4BLKE : FLT4BLKE
bits : 24 - 24 (1 bit)

FLT4BLKS : FLT4BLKS
bits : 25 - 25 (1 bit)

FLT4CNT : FLT4CNT
bits : 26 - 29 (4 bit)

FLT4CRES : FLT4CRES
bits : 30 - 30 (1 bit)

FLT4RSTM : FLT4RSTM
bits : 31 - 31 (1 bit)


FLTINR4

HRTIM Fault Input Register 4
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLTINR4 FLTINR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLT5BLKE FLT5BLKS FLT5CNT FLT5CRES FLT5RSTM FLT6BLKE FLT6BLKS FLT6CNT FLT6CRES FLT6RSTM

FLT5BLKE : FLT5BLKE
bits : 0 - 0 (1 bit)

FLT5BLKS : FLT5BLKS
bits : 1 - 1 (1 bit)

FLT5CNT : FLT5CNT
bits : 2 - 5 (4 bit)

FLT5CRES : FLT5CRES
bits : 6 - 6 (1 bit)

FLT5RSTM : FLT5RSTM
bits : 7 - 7 (1 bit)

FLT6BLKE : FLT6BLKE
bits : 8 - 8 (1 bit)

FLT6BLKS : FLT6BLKS
bits : 9 - 9 (1 bit)

FLT6CNT : FLT6CNT
bits : 10 - 13 (4 bit)

FLT6CRES : FLT6CRES
bits : 14 - 14 (1 bit)

FLT6RSTM : FLT6RSTM
bits : 15 - 15 (1 bit)


ICR

Interrupt Clear Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ICR ICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLT1C FLT2C FLT3C FLT4C FLT5C SYSFLTC FLT6C DLLRDYC BMPERC

FLT1C : Fault 1 Interrupt Flag Clear
bits : 0 - 0 (1 bit)

FLT2C : Fault 2 Interrupt Flag Clear
bits : 1 - 1 (1 bit)

FLT3C : Fault 3 Interrupt Flag Clear
bits : 2 - 2 (1 bit)

FLT4C : Fault 4 Interrupt Flag Clear
bits : 3 - 3 (1 bit)

FLT5C : Fault 5 Interrupt Flag Clear
bits : 4 - 4 (1 bit)

SYSFLTC : System Fault Interrupt Flag Clear
bits : 5 - 5 (1 bit)

FLT6C : Fault 6 Interrupt Flag Clear
bits : 6 - 6 (1 bit)

DLLRDYC : DLL Ready Interrupt flag Clear
bits : 16 - 16 (1 bit)

BMPERC : Burst mode period flag Clear
bits : 17 - 17 (1 bit)



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