\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Unspecified - - Pin select for SCK
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIN : Pin number
bits : 0 - 3 (4 bit)
CONNECT : Connection
bits : 31 - 30 (0 bit)
Enumeration:
1 : Disconnected
Disconnect
0 : Connected
Connect
End of enumeration elements list.
TXD byte sent and RXD byte received
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVENTS_READY : TXD byte sent and RXD byte received
bits : 0 - -1 (0 bit)
Enumeration:
0 : NotGenerated
Event not generated
1 : Generated
Event generated
End of enumeration elements list.
Enable interrupt
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READY : Write '1' to enable interrupt for event READY
bits : 2 - 1 (0 bit)
Enumeration: ( write )
1 : Set
Enable
End of enumeration elements list.
Disable interrupt
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READY : Write '1' to disable interrupt for event READY
bits : 2 - 1 (0 bit)
Enumeration: ( write )
1 : Clear
Disable
End of enumeration elements list.
Unspecified - - Pin select for MOSI signal
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIN : Pin number
bits : 0 - 3 (4 bit)
CONNECT : Connection
bits : 31 - 30 (0 bit)
Enumeration:
1 : Disconnected
Disconnect
0 : Connected
Connect
End of enumeration elements list.
Enable SPI
address_offset : 0x500 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Enable or disable SPI
bits : 0 - 2 (3 bit)
Enumeration:
0 : Disabled
Disable SPI
1 : Enabled
Enable SPI
End of enumeration elements list.
RXD register
address_offset : 0x518 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXD : RX data received. Double buffered
bits : 0 - 6 (7 bit)
TXD register
address_offset : 0x51C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXD : TX data to send. Double buffered
bits : 0 - 6 (7 bit)
SPI frequency. Accuracy depends on the HFCLK source selected.
address_offset : 0x524 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQUENCY : SPI master data rate
bits : 0 - 30 (31 bit)
Enumeration:
0x02000000 : K125
125 kbps
0x04000000 : K250
250 kbps
0x08000000 : K500
500 kbps
0x10000000 : M1
1 Mbps
0x20000000 : M2
2 Mbps
0x40000000 : M4
4 Mbps
0x80000000 : M8
8 Mbps
End of enumeration elements list.
Configuration register
address_offset : 0x554 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ORDER : Bit order
bits : 0 - -1 (0 bit)
Enumeration:
0 : MsbFirst
Most significant bit shifted out first
1 : LsbFirst
Least significant bit shifted out first
End of enumeration elements list.
CPHA : Serial clock (SCK) phase
bits : 1 - 0 (0 bit)
Enumeration:
0 : Leading
Sample on leading edge of clock, shift serial data on trailing edge
1 : Trailing
Sample on trailing edge of clock, shift serial data on leading edge
End of enumeration elements list.
CPOL : Serial clock (SCK) polarity
bits : 2 - 1 (0 bit)
Enumeration:
0 : ActiveHigh
Active high
1 : ActiveLow
Active low
End of enumeration elements list.
Unspecified - - Pin select for MISO signal
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIN : Pin number
bits : 0 - 3 (4 bit)
CONNECT : Connection
bits : 31 - 30 (0 bit)
Enumeration:
1 : Disconnected
Disconnect
0 : Connected
Connect
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.