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UARTE

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TASKS_STARTRX

PSEL - RTS

RXD - PTR

TXD - PTR

EVENTS_CTS

EVENTS_NCTS

EVENTS_RXDRDY

EVENTS_ENDRX

EVENTS_TXDRDY

EVENTS_ENDTX

EVENTS_ERROR

EVENTS_RXTO

EVENTS_RXSTARTED

EVENTS_TXSTARTED

EVENTS_TXSTOPPED

SHORTS

TASKS_FLUSHRX

INTEN

INTENSET

INTENCLR

TASKS_STOPRX

PSEL - TXD

RXD - MAXCNT

TXD - MAXCNT

ERRORSRC

ENABLE

BAUDRATE

CONFIG

TASKS_STARTTX

PSEL - CTS

RXD - AMOUNT

TXD - AMOUNT

TASKS_STOPTX

PSEL - RXD


TASKS_STARTRX

Start UART receiver
address_offset : 0x0 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_STARTRX TASKS_STARTRX write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_STARTRX

TASKS_STARTRX : Start UART receiver
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


PSEL - RTS

Unspecified - - Pin select for RTS signal
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSEL - RTS PSEL - RTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN CONNECT

PIN : Pin number
bits : 0 - 3 (4 bit)

CONNECT : Connection
bits : 31 - 30 (0 bit)

Enumeration:

1 : Disconnected

Disconnect

0 : Connected

Connect

End of enumeration elements list.


RXD - PTR

RXD EasyDMA channel - - Data pointer
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXD - PTR RXD - PTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTR

PTR : Data pointer
bits : 0 - 30 (31 bit)


TXD - PTR

TXD EasyDMA channel - - Data pointer
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXD - PTR TXD - PTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTR

PTR : Data pointer
bits : 0 - 30 (31 bit)


EVENTS_CTS

CTS is activated (set low). Clear To Send.
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_CTS EVENTS_CTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_CTS

EVENTS_CTS : CTS is activated (set low). Clear To Send.
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


EVENTS_NCTS

CTS is deactivated (set high). Not Clear To Send.
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_NCTS EVENTS_NCTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_NCTS

EVENTS_NCTS : CTS is deactivated (set high). Not Clear To Send.
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


EVENTS_RXDRDY

Data received in RXD (but potentially not yet transferred to Data RAM)
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_RXDRDY EVENTS_RXDRDY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_RXDRDY

EVENTS_RXDRDY : Data received in RXD (but potentially not yet transferred to Data RAM)
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


EVENTS_ENDRX

Receive buffer is filled up
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_ENDRX EVENTS_ENDRX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_ENDRX

EVENTS_ENDRX : Receive buffer is filled up
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


EVENTS_TXDRDY

Data sent from TXD
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_TXDRDY EVENTS_TXDRDY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_TXDRDY

EVENTS_TXDRDY : Data sent from TXD
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


EVENTS_ENDTX

Last TX byte transmitted
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_ENDTX EVENTS_ENDTX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_ENDTX

EVENTS_ENDTX : Last TX byte transmitted
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


EVENTS_ERROR

Error detected
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_ERROR EVENTS_ERROR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_ERROR

EVENTS_ERROR : Error detected
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


EVENTS_RXTO

Receiver timeout
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_RXTO EVENTS_RXTO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_RXTO

EVENTS_RXTO : Receiver timeout
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


EVENTS_RXSTARTED

UART receiver has started
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_RXSTARTED EVENTS_RXSTARTED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_RXSTARTED

EVENTS_RXSTARTED : UART receiver has started
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


EVENTS_TXSTARTED

UART transmitter has started
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_TXSTARTED EVENTS_TXSTARTED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_TXSTARTED

EVENTS_TXSTARTED : UART transmitter has started
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


EVENTS_TXSTOPPED

Transmitter stopped
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_TXSTOPPED EVENTS_TXSTOPPED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_TXSTOPPED

EVENTS_TXSTOPPED : Transmitter stopped
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


SHORTS

Shortcuts between local events and tasks
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHORTS SHORTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENDRX_STARTRX ENDRX_STOPRX

ENDRX_STARTRX : Shortcut between event ENDRX and task STARTRX
bits : 5 - 4 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.

ENDRX_STOPRX : Shortcut between event ENDRX and task STOPRX
bits : 6 - 5 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.


TASKS_FLUSHRX

Flush RX FIFO into RX buffer
address_offset : 0x2C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_FLUSHRX TASKS_FLUSHRX write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_FLUSHRX

TASKS_FLUSHRX : Flush RX FIFO into RX buffer
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


INTEN

Enable or disable interrupt
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTS NCTS RXDRDY ENDRX TXDRDY ENDTX ERROR RXTO RXSTARTED TXSTARTED TXSTOPPED

CTS : Enable or disable interrupt for event CTS
bits : 0 - -1 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

NCTS : Enable or disable interrupt for event NCTS
bits : 1 - 0 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

RXDRDY : Enable or disable interrupt for event RXDRDY
bits : 2 - 1 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

ENDRX : Enable or disable interrupt for event ENDRX
bits : 4 - 3 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

TXDRDY : Enable or disable interrupt for event TXDRDY
bits : 7 - 6 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

ENDTX : Enable or disable interrupt for event ENDTX
bits : 8 - 7 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

ERROR : Enable or disable interrupt for event ERROR
bits : 9 - 8 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

RXTO : Enable or disable interrupt for event RXTO
bits : 17 - 16 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

RXSTARTED : Enable or disable interrupt for event RXSTARTED
bits : 19 - 18 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

TXSTARTED : Enable or disable interrupt for event TXSTARTED
bits : 20 - 19 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

TXSTOPPED : Enable or disable interrupt for event TXSTOPPED
bits : 22 - 21 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.


INTENSET

Enable interrupt
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTS NCTS RXDRDY ENDRX TXDRDY ENDTX ERROR RXTO RXSTARTED TXSTARTED TXSTOPPED

CTS : Write '1' to enable interrupt for event CTS
bits : 0 - -1 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

NCTS : Write '1' to enable interrupt for event NCTS
bits : 1 - 0 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

RXDRDY : Write '1' to enable interrupt for event RXDRDY
bits : 2 - 1 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

ENDRX : Write '1' to enable interrupt for event ENDRX
bits : 4 - 3 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

TXDRDY : Write '1' to enable interrupt for event TXDRDY
bits : 7 - 6 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

ENDTX : Write '1' to enable interrupt for event ENDTX
bits : 8 - 7 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

ERROR : Write '1' to enable interrupt for event ERROR
bits : 9 - 8 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

RXTO : Write '1' to enable interrupt for event RXTO
bits : 17 - 16 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

RXSTARTED : Write '1' to enable interrupt for event RXSTARTED
bits : 19 - 18 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

TXSTARTED : Write '1' to enable interrupt for event TXSTARTED
bits : 20 - 19 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

TXSTOPPED : Write '1' to enable interrupt for event TXSTOPPED
bits : 22 - 21 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.


INTENCLR

Disable interrupt
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTS NCTS RXDRDY ENDRX TXDRDY ENDTX ERROR RXTO RXSTARTED TXSTARTED TXSTOPPED

CTS : Write '1' to disable interrupt for event CTS
bits : 0 - -1 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

NCTS : Write '1' to disable interrupt for event NCTS
bits : 1 - 0 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

RXDRDY : Write '1' to disable interrupt for event RXDRDY
bits : 2 - 1 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

ENDRX : Write '1' to disable interrupt for event ENDRX
bits : 4 - 3 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

TXDRDY : Write '1' to disable interrupt for event TXDRDY
bits : 7 - 6 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

ENDTX : Write '1' to disable interrupt for event ENDTX
bits : 8 - 7 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

ERROR : Write '1' to disable interrupt for event ERROR
bits : 9 - 8 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

RXTO : Write '1' to disable interrupt for event RXTO
bits : 17 - 16 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

RXSTARTED : Write '1' to disable interrupt for event RXSTARTED
bits : 19 - 18 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

TXSTARTED : Write '1' to disable interrupt for event TXSTARTED
bits : 20 - 19 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

TXSTOPPED : Write '1' to disable interrupt for event TXSTOPPED
bits : 22 - 21 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.


TASKS_STOPRX

Stop UART receiver
address_offset : 0x4 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_STOPRX TASKS_STOPRX write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_STOPRX

TASKS_STOPRX : Stop UART receiver
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


PSEL - TXD

Unspecified - - Pin select for TXD signal
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSEL - TXD PSEL - TXD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN CONNECT

PIN : Pin number
bits : 0 - 3 (4 bit)

CONNECT : Connection
bits : 31 - 30 (0 bit)

Enumeration:

1 : Disconnected

Disconnect

0 : Connected

Connect

End of enumeration elements list.


RXD - MAXCNT

RXD EasyDMA channel - - Maximum number of bytes in receive buffer
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXD - MAXCNT RXD - MAXCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAXCNT

MAXCNT : Maximum number of bytes in receive buffer
bits : 0 - 8 (9 bit)


TXD - MAXCNT

TXD EasyDMA channel - - Maximum number of bytes in transmit buffer
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXD - MAXCNT TXD - MAXCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAXCNT

MAXCNT : Maximum number of bytes in transmit buffer
bits : 0 - 8 (9 bit)


ERRORSRC

Error source Note : this register is read / write one to clear.
address_offset : 0x480 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ERRORSRC ERRORSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVERRUN PARITY FRAMING BREAK

OVERRUN : Overrun error
bits : 0 - -1 (0 bit)

Enumeration: ( read )

0 : NotPresent

Read: error not present

1 : Present

Read: error present

End of enumeration elements list.

PARITY : Parity error
bits : 1 - 0 (0 bit)

Enumeration: ( read )

0 : NotPresent

Read: error not present

1 : Present

Read: error present

End of enumeration elements list.

FRAMING : Framing error occurred
bits : 2 - 1 (0 bit)

Enumeration: ( read )

0 : NotPresent

Read: error not present

1 : Present

Read: error present

End of enumeration elements list.

BREAK : Break condition
bits : 3 - 2 (0 bit)

Enumeration: ( read )

0 : NotPresent

Read: error not present

1 : Present

Read: error present

End of enumeration elements list.


ENABLE

Enable UART
address_offset : 0x500 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENABLE ENABLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE

ENABLE : Enable or disable UARTE
bits : 0 - 2 (3 bit)

Enumeration:

0 : Disabled

Disable UARTE

8 : Enabled

Enable UARTE

End of enumeration elements list.


BAUDRATE

Baud rate. Accuracy depends on the HFCLK source selected.
address_offset : 0x524 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BAUDRATE BAUDRATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BAUDRATE

BAUDRATE : Baud rate
bits : 0 - 30 (31 bit)

Enumeration:

0x0004F000 : Baud1200

1200 baud (actual rate: 1205)

0x0009D000 : Baud2400

2400 baud (actual rate: 2396)

0x0013B000 : Baud4800

4800 baud (actual rate: 4808)

0x00275000 : Baud9600

9600 baud (actual rate: 9598)

0x003AF000 : Baud14400

14400 baud (actual rate: 14401)

0x004EA000 : Baud19200

19200 baud (actual rate: 19208)

0x0075C000 : Baud28800

28800 baud (actual rate: 28777)

0x00800000 : Baud31250

31250 baud

0x009D0000 : Baud38400

38400 baud (actual rate: 38369)

0x00E50000 : Baud56000

56000 baud (actual rate: 55944)

0x00EB0000 : Baud57600

57600 baud (actual rate: 57554)

0x013A9000 : Baud76800

76800 baud (actual rate: 76923)

0x01D60000 : Baud115200

115200 baud (actual rate: 115108)

0x03B00000 : Baud230400

230400 baud (actual rate: 231884)

0x04000000 : Baud250000

250000 baud

0x07400000 : Baud460800

460800 baud (actual rate: 457143)

0x0F000000 : Baud921600

921600 baud (actual rate: 941176)

0x10000000 : Baud1M

1Mega baud

End of enumeration elements list.


CONFIG

Configuration of parity and hardware flow control
address_offset : 0x56C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONFIG CONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HWFC PARITY STOP

HWFC : Hardware flow control
bits : 0 - -1 (0 bit)

Enumeration:

0 : Disabled

Disabled

1 : Enabled

Enabled

End of enumeration elements list.

PARITY : Parity
bits : 1 - 2 (2 bit)

Enumeration:

0x0 : Excluded

Exclude parity bit

0x7 : Included

Include even parity bit

End of enumeration elements list.

STOP : Stop bits
bits : 4 - 3 (0 bit)

Enumeration:

0 : One

One stop bit

1 : Two

Two stop bits

End of enumeration elements list.


TASKS_STARTTX

Start UART transmitter
address_offset : 0x8 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_STARTTX TASKS_STARTTX write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_STARTTX

TASKS_STARTTX : Start UART transmitter
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


PSEL - CTS

Unspecified - - Pin select for CTS signal
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSEL - CTS PSEL - CTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN CONNECT

PIN : Pin number
bits : 0 - 3 (4 bit)

CONNECT : Connection
bits : 31 - 30 (0 bit)

Enumeration:

1 : Disconnected

Disconnect

0 : Connected

Connect

End of enumeration elements list.


RXD - AMOUNT

RXD EasyDMA channel - - Number of bytes transferred in the last transaction
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXD - AMOUNT RXD - AMOUNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMOUNT

AMOUNT : Number of bytes transferred in the last transaction
bits : 0 - 8 (9 bit)


TXD - AMOUNT

TXD EasyDMA channel - - Number of bytes transferred in the last transaction
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXD - AMOUNT TXD - AMOUNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMOUNT

AMOUNT : Number of bytes transferred in the last transaction
bits : 0 - 8 (9 bit)


TASKS_STOPTX

Stop UART transmitter
address_offset : 0xC Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_STOPTX TASKS_STOPTX write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_STOPTX

TASKS_STOPTX : Stop UART transmitter
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


PSEL - RXD

Unspecified - - Pin select for RXD signal
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSEL - RXD PSEL - RXD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN CONNECT

PIN : Pin number
bits : 0 - 3 (4 bit)

CONNECT : Connection
bits : 31 - 30 (0 bit)

Enumeration:

1 : Disconnected

Disconnect

0 : Connected

Connect

End of enumeration elements list.



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