Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Ready flag
address_offset : 0x400 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
READY : NVMC is ready or busy
bits : 0 - -1 (0 bit)
Enumeration:
0 : Busy
NVMC is busy (on-going write or erase operation)
1 : Ready
NVMC is ready
End of enumeration elements list.
Ready flag
address_offset : 0x408 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
READYNEXT : NVMC can accept a new write operation
bits : 0 - -1 (0 bit)
Enumeration:
0 : Busy
NVMC cannot accept any write operation
1 : Ready
NVMC is ready
End of enumeration elements list.
Configuration register
address_offset : 0x504 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WEN : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated.
bits : 0 - 1 (2 bit)
Enumeration:
0 : Ren
Read only access
1 : Wen
Write enabled
2 : Een
Erase enabled
4 : PEen
Partial erase enabled
End of enumeration elements list.
Register for erasing all non-volatile user memory
address_offset : 0x50C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ERASEALL : Erase all non-volatile memory including UICR registers. Note that erasing must be enabled by setting CONFIG.WEN = Een before the non-volatile memory can be erased.
bits : 0 - -1 (0 bit)
Enumeration:
0 : NoOperation
No operation
1 : Erase
Start chip erase
End of enumeration elements list.
Register for partial erase configuration
address_offset : 0x51C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DURATION : Duration of the partial erase in milliseconds
bits : 0 - 5 (6 bit)
I-code cache configuration register
address_offset : 0x540 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CACHEEN : Cache enable
bits : 0 - -1 (0 bit)
Enumeration:
0 : Disabled
Disable cache. Invalidates all cache entries.
1 : Enabled
Enable cache
End of enumeration elements list.
CACHEPROFEN : Cache profiling enable
bits : 8 - 7 (0 bit)
Enumeration:
0 : Disabled
Disable cache profiling
1 : Enabled
Enable cache profiling
End of enumeration elements list.
I-code cache hit counter
address_offset : 0x548 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HITS : Number of cache hits Write zero to clear
bits : 0 - 30 (31 bit)
I-code cache miss counter
address_offset : 0x54C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MISSES : Number of cache misses Write zero to clear
bits : 0 - 30 (31 bit)
Unspecified
address_offset : 0x584 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WEN : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated.
bits : 0 - 0 (1 bit)
Enumeration:
0 : Ren
Read only access
1 : Wen
Write enabled
2 : Een
Erase enabled
End of enumeration elements list.
Non-secure APPROTECT enable register
address_offset : 0x588 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SET : Allow non-secure code to set APPROTECT
bits : 0 - -1 (0 bit)
Enumeration:
1 : Set
Set value
End of enumeration elements list.
KEY : Key to write in order to validate the write operation
bits : 4 - 30 (27 bit)
Enumeration:
0xAFBE5A7 : Keyvalid
Key value
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.