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TWIM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TASKS_STARTRX

PSEL - SCL

RXD - PTR

TXD - PTR

EVENTS_STOPPED

EVENTS_ERROR

TASKS_STOP

EVENTS_SUSPENDED

EVENTS_RXSTARTED

EVENTS_TXSTARTED

EVENTS_LASTRX

EVENTS_LASTTX

TASKS_SUSPEND

TASKS_RESUME

SHORTS

INTEN

INTENSET

INTENCLR

PSEL - SDA

RXD - MAXCNT

TXD - MAXCNT

ERRORSRC

ENABLE

FREQUENCY

ADDRESS

TASKS_STARTTX

RXD - AMOUNT

TXD - AMOUNT

RXD - LIST

TXD - LIST


TASKS_STARTRX

Start TWI receive sequence
address_offset : 0x0 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_STARTRX TASKS_STARTRX write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_STARTRX

TASKS_STARTRX : Start TWI receive sequence
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


PSEL - SCL

Unspecified - - Pin select for SCL signal
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSEL - SCL PSEL - SCL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN PORT CONNECT

PIN : Pin number
bits : 0 - 3 (4 bit)

PORT : Port number
bits : 5 - 4 (0 bit)

CONNECT : Connection
bits : 31 - 30 (0 bit)

Enumeration:

1 : Disconnected

Disconnect

0 : Connected

Connect

End of enumeration elements list.


RXD - PTR

RXD EasyDMA channel - - Data pointer
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXD - PTR RXD - PTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTR

PTR : Data pointer
bits : 0 - 30 (31 bit)


TXD - PTR

TXD EasyDMA channel - - Data pointer
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXD - PTR TXD - PTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTR

PTR : Data pointer
bits : 0 - 30 (31 bit)


EVENTS_STOPPED

TWI stopped
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_STOPPED EVENTS_STOPPED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_STOPPED

EVENTS_STOPPED : TWI stopped
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


EVENTS_ERROR

TWI error
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_ERROR EVENTS_ERROR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_ERROR

EVENTS_ERROR : TWI error
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


TASKS_STOP

Stop TWI transaction. Must be issued while the TWI master is not suspended.
address_offset : 0x14 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_STOP TASKS_STOP write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_STOP

TASKS_STOP : Stop TWI transaction. Must be issued while the TWI master is not suspended.
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


EVENTS_SUSPENDED

Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_SUSPENDED EVENTS_SUSPENDED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_SUSPENDED

EVENTS_SUSPENDED : Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


EVENTS_RXSTARTED

Receive sequence started
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_RXSTARTED EVENTS_RXSTARTED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_RXSTARTED

EVENTS_RXSTARTED : Receive sequence started
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


EVENTS_TXSTARTED

Transmit sequence started
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_TXSTARTED EVENTS_TXSTARTED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_TXSTARTED

EVENTS_TXSTARTED : Transmit sequence started
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


EVENTS_LASTRX

Byte boundary, starting to receive the last byte
address_offset : 0x15C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_LASTRX EVENTS_LASTRX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_LASTRX

EVENTS_LASTRX : Byte boundary, starting to receive the last byte
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


EVENTS_LASTTX

Byte boundary, starting to transmit the last byte
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_LASTTX EVENTS_LASTTX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_LASTTX

EVENTS_LASTTX : Byte boundary, starting to transmit the last byte
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


TASKS_SUSPEND

Suspend TWI transaction
address_offset : 0x1C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_SUSPEND TASKS_SUSPEND write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_SUSPEND

TASKS_SUSPEND : Suspend TWI transaction
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


TASKS_RESUME

Resume TWI transaction
address_offset : 0x20 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_RESUME TASKS_RESUME write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_RESUME

TASKS_RESUME : Resume TWI transaction
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


SHORTS

Shortcuts between local events and tasks
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHORTS SHORTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LASTTX_STARTRX LASTTX_SUSPEND LASTTX_STOP LASTRX_STARTTX LASTRX_SUSPEND LASTRX_STOP

LASTTX_STARTRX : Shortcut between event LASTTX and task STARTRX
bits : 7 - 6 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.

LASTTX_SUSPEND : Shortcut between event LASTTX and task SUSPEND
bits : 8 - 7 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.

LASTTX_STOP : Shortcut between event LASTTX and task STOP
bits : 9 - 8 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.

LASTRX_STARTTX : Shortcut between event LASTRX and task STARTTX
bits : 10 - 9 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.

LASTRX_SUSPEND : Shortcut between event LASTRX and task SUSPEND
bits : 11 - 10 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.

LASTRX_STOP : Shortcut between event LASTRX and task STOP
bits : 12 - 11 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.


INTEN

Enable or disable interrupt
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STOPPED ERROR SUSPENDED RXSTARTED TXSTARTED LASTRX LASTTX

STOPPED : Enable or disable interrupt for event STOPPED
bits : 1 - 0 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

ERROR : Enable or disable interrupt for event ERROR
bits : 9 - 8 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

SUSPENDED : Enable or disable interrupt for event SUSPENDED
bits : 18 - 17 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

RXSTARTED : Enable or disable interrupt for event RXSTARTED
bits : 19 - 18 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

TXSTARTED : Enable or disable interrupt for event TXSTARTED
bits : 20 - 19 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

LASTRX : Enable or disable interrupt for event LASTRX
bits : 23 - 22 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

LASTTX : Enable or disable interrupt for event LASTTX
bits : 24 - 23 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.


INTENSET

Enable interrupt
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STOPPED ERROR SUSPENDED RXSTARTED TXSTARTED LASTRX LASTTX

STOPPED : Write '1' to enable interrupt for event STOPPED
bits : 1 - 0 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

ERROR : Write '1' to enable interrupt for event ERROR
bits : 9 - 8 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

SUSPENDED : Write '1' to enable interrupt for event SUSPENDED
bits : 18 - 17 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

RXSTARTED : Write '1' to enable interrupt for event RXSTARTED
bits : 19 - 18 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

TXSTARTED : Write '1' to enable interrupt for event TXSTARTED
bits : 20 - 19 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

LASTRX : Write '1' to enable interrupt for event LASTRX
bits : 23 - 22 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

LASTTX : Write '1' to enable interrupt for event LASTTX
bits : 24 - 23 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.


INTENCLR

Disable interrupt
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STOPPED ERROR SUSPENDED RXSTARTED TXSTARTED LASTRX LASTTX

STOPPED : Write '1' to disable interrupt for event STOPPED
bits : 1 - 0 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

ERROR : Write '1' to disable interrupt for event ERROR
bits : 9 - 8 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

SUSPENDED : Write '1' to disable interrupt for event SUSPENDED
bits : 18 - 17 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

RXSTARTED : Write '1' to disable interrupt for event RXSTARTED
bits : 19 - 18 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

TXSTARTED : Write '1' to disable interrupt for event TXSTARTED
bits : 20 - 19 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

LASTRX : Write '1' to disable interrupt for event LASTRX
bits : 23 - 22 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

LASTTX : Write '1' to disable interrupt for event LASTTX
bits : 24 - 23 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.


PSEL - SDA

Unspecified - - Pin select for SDA signal
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSEL - SDA PSEL - SDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN PORT CONNECT

PIN : Pin number
bits : 0 - 3 (4 bit)

PORT : Port number
bits : 5 - 4 (0 bit)

CONNECT : Connection
bits : 31 - 30 (0 bit)

Enumeration:

1 : Disconnected

Disconnect

0 : Connected

Connect

End of enumeration elements list.


RXD - MAXCNT

RXD EasyDMA channel - - Maximum number of bytes in receive buffer
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXD - MAXCNT RXD - MAXCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAXCNT

MAXCNT : Maximum number of bytes in receive buffer
bits : 0 - 14 (15 bit)


TXD - MAXCNT

TXD EasyDMA channel - - Maximum number of bytes in transmit buffer
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXD - MAXCNT TXD - MAXCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAXCNT

MAXCNT : Maximum number of bytes in transmit buffer
bits : 0 - 14 (15 bit)


ERRORSRC

Error source
address_offset : 0x4C4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ERRORSRC ERRORSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVERRUN ANACK DNACK

OVERRUN : Overrun error
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotReceived

Error did not occur

1 : Received

Error occurred

End of enumeration elements list.

ANACK : NACK received after sending the address (write '1' to clear)
bits : 1 - 0 (0 bit)

Enumeration:

0 : NotReceived

Error did not occur

1 : Received

Error occurred

End of enumeration elements list.

DNACK : NACK received after sending a data byte (write '1' to clear)
bits : 2 - 1 (0 bit)

Enumeration:

0 : NotReceived

Error did not occur

1 : Received

Error occurred

End of enumeration elements list.


ENABLE

Enable TWIM
address_offset : 0x500 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENABLE ENABLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE

ENABLE : Enable or disable TWIM
bits : 0 - 2 (3 bit)

Enumeration:

0 : Disabled

Disable TWIM

6 : Enabled

Enable TWIM

End of enumeration elements list.


FREQUENCY

TWI frequency. Accuracy depends on the HFCLK source selected.
address_offset : 0x524 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FREQUENCY FREQUENCY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FREQUENCY

FREQUENCY : TWI master clock frequency
bits : 0 - 30 (31 bit)

Enumeration:

0x01980000 : K100

100 kbps

0x04000000 : K250

250 kbps

0x06400000 : K400

400 kbps

End of enumeration elements list.


ADDRESS

Address used in the TWI transfer
address_offset : 0x588 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDRESS ADDRESS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS

ADDRESS : Address used in the TWI transfer
bits : 0 - 5 (6 bit)


TASKS_STARTTX

Start TWI transmit sequence
address_offset : 0x8 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_STARTTX TASKS_STARTTX write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_STARTTX

TASKS_STARTTX : Start TWI transmit sequence
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


RXD - AMOUNT

RXD EasyDMA channel - - Number of bytes transferred in the last transaction
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXD - AMOUNT RXD - AMOUNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMOUNT

AMOUNT : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte.
bits : 0 - 14 (15 bit)


TXD - AMOUNT

TXD EasyDMA channel - - Number of bytes transferred in the last transaction
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXD - AMOUNT TXD - AMOUNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMOUNT

AMOUNT : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte.
bits : 0 - 14 (15 bit)


RXD - LIST

RXD EasyDMA channel - - EasyDMA list type
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXD - LIST RXD - LIST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIST

LIST : List type
bits : 0 - 1 (2 bit)

Enumeration:

0 : Disabled

Disable EasyDMA list

1 : ArrayList

Use array list

End of enumeration elements list.


TXD - LIST

TXD EasyDMA channel - - EasyDMA list type
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXD - LIST TXD - LIST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIST

LIST : List type
bits : 0 - 1 (2 bit)

Enumeration:

0 : Disabled

Disable EasyDMA list

1 : ArrayList

Use array list

End of enumeration elements list.



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