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NVMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

READY

READYNEXT

CONFIG

ERASEPAGE

ERASEPCR1

ERASEALL

ERASEPCR0

ERASEUICR

ERASEPAGEPARTIAL

ERASEPAGEPARTIALCFG

ICACHECNF

IHIT

IMISS


READY

Ready flag
address_offset : 0x400 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

READY READY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READY

READY : NVMC is ready or busy
bits : 0 - -1 (0 bit)

Enumeration:

0 : Busy

NVMC is busy (on-going write or erase operation)

1 : Ready

NVMC is ready

End of enumeration elements list.


READYNEXT

Ready flag
address_offset : 0x408 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

READYNEXT READYNEXT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READYNEXT

READYNEXT : NVMC can accept a new write operation
bits : 0 - -1 (0 bit)

Enumeration:

0 : Busy

NVMC cannot accept any write operation

1 : Ready

NVMC is ready

End of enumeration elements list.


CONFIG

Configuration register
address_offset : 0x504 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONFIG CONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WEN

WEN : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated.
bits : 0 - 0 (1 bit)

Enumeration:

0 : Ren

Read only access

1 : Wen

Write enabled

2 : Een

Erase enabled

End of enumeration elements list.


ERASEPAGE

Register for erasing a page in code area
address_offset : 0x508 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ERASEPAGE ERASEPAGE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERASEPAGE

ERASEPAGE : Register for starting erase of a page in code area
bits : 0 - 30 (31 bit)


ERASEPCR1

Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE.
address_offset : 0x508 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : ERASEPAGE
reset_Mask : 0x0

ERASEPCR1 ERASEPCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERASEPCR1

ERASEPCR1 : Register for erasing a page in code area. Equivalent to ERASEPAGE.
bits : 0 - 30 (31 bit)


ERASEALL

Register for erasing all non-volatile user memory
address_offset : 0x50C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ERASEALL ERASEALL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERASEALL

ERASEALL : Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased.
bits : 0 - -1 (0 bit)

Enumeration:

0 : NoOperation

No operation

1 : Erase

Start chip erase

End of enumeration elements list.


ERASEPCR0

Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE.
address_offset : 0x510 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ERASEPCR0 ERASEPCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERASEPCR0

ERASEPCR0 : Register for starting erase of a page in code area. Equivalent to ERASEPAGE.
bits : 0 - 30 (31 bit)


ERASEUICR

Register for erasing user information configuration registers
address_offset : 0x514 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ERASEUICR ERASEUICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERASEUICR

ERASEUICR : Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased.
bits : 0 - -1 (0 bit)

Enumeration:

0 : NoOperation

No operation

1 : Erase

Start erase of UICR

End of enumeration elements list.


ERASEPAGEPARTIAL

Register for partial erase of a page in code area
address_offset : 0x518 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ERASEPAGEPARTIAL ERASEPAGEPARTIAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERASEPAGEPARTIAL

ERASEPAGEPARTIAL : Register for starting partial erase of a page in code area
bits : 0 - 30 (31 bit)


ERASEPAGEPARTIALCFG

Register for partial erase configuration
address_offset : 0x51C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ERASEPAGEPARTIALCFG ERASEPAGEPARTIALCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DURATION

DURATION : Duration of the partial erase in milliseconds
bits : 0 - 5 (6 bit)


ICACHECNF

I-code cache configuration register.
address_offset : 0x540 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICACHECNF ICACHECNF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CACHEEN CACHEPROFEN

CACHEEN : Cache enable
bits : 0 - -1 (0 bit)

Enumeration:

0 : Disabled

Disable cache. Invalidates all cache entries.

1 : Enabled

Enable cache

End of enumeration elements list.

CACHEPROFEN : Cache profiling enable
bits : 8 - 7 (0 bit)

Enumeration:

0 : Disabled

Disable cache profiling

1 : Enabled

Enable cache profiling

End of enumeration elements list.


IHIT

I-code cache hit counter.
address_offset : 0x548 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IHIT IHIT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HITS

HITS : Number of cache hits
bits : 0 - 30 (31 bit)


IMISS

I-code cache miss counter.
address_offset : 0x54C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMISS IMISS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MISSES

MISSES : Number of cache misses
bits : 0 - 30 (31 bit)



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