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QDEC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TASKS_START

PSEL - LED

TASKS_RDCLRDBL

EVENTS_SAMPLERDY

EVENTS_REPORTRDY

EVENTS_ACCOF

EVENTS_DBLRDY

EVENTS_STOPPED

SHORTS

INTENSET

INTENCLR

TASKS_STOP

PSEL - A

ENABLE

LEDPOL

SAMPLEPER

SAMPLE

REPORTPER

ACC

ACCREAD

DBFEN

LEDPRE

ACCDBL

ACCDBLREAD

TASKS_READCLRACC

PSEL - B

TASKS_RDCLRACC


TASKS_START

Task starting the quadrature decoder
address_offset : 0x0 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_START TASKS_START write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PSEL - LED

Unspecified - - Pin select for LED signal
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSEL - LED PSEL - LED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN CONNECT

PIN : Pin number
bits : 0 - 3 (4 bit)

CONNECT : Connection
bits : 31 - 30 (0 bit)

Enumeration:

1 : Disconnected

Disconnect

0 : Connected

Connect

End of enumeration elements list.


TASKS_RDCLRDBL

Read and clear ACCDBL
address_offset : 0x10 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_RDCLRDBL TASKS_RDCLRDBL write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EVENTS_SAMPLERDY

Event being generated for every new sample value written to the SAMPLE register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_SAMPLERDY EVENTS_SAMPLERDY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EVENTS_REPORTRDY

Non-null report ready
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_REPORTRDY EVENTS_REPORTRDY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EVENTS_ACCOF

ACC or ACCDBL register overflow
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_ACCOF EVENTS_ACCOF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EVENTS_DBLRDY

Double displacement(s) detected
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_DBLRDY EVENTS_DBLRDY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EVENTS_STOPPED

QDEC has been stopped
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_STOPPED EVENTS_STOPPED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SHORTS

Shortcut register
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHORTS SHORTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REPORTRDY_READCLRACC SAMPLERDY_STOP REPORTRDY_RDCLRACC REPORTRDY_STOP DBLRDY_RDCLRDBL DBLRDY_STOP SAMPLERDY_READCLRACC

REPORTRDY_READCLRACC : Shortcut between REPORTRDY event and READCLRACC task
bits : 0 - -1 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.

SAMPLERDY_STOP : Shortcut between SAMPLERDY event and STOP task
bits : 1 - 0 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.

REPORTRDY_RDCLRACC : Shortcut between REPORTRDY event and RDCLRACC task
bits : 2 - 1 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.

REPORTRDY_STOP : Shortcut between REPORTRDY event and STOP task
bits : 3 - 2 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.

DBLRDY_RDCLRDBL : Shortcut between DBLRDY event and RDCLRDBL task
bits : 4 - 3 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.

DBLRDY_STOP : Shortcut between DBLRDY event and STOP task
bits : 5 - 4 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.

SAMPLERDY_READCLRACC : Shortcut between SAMPLERDY event and READCLRACC task
bits : 6 - 5 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.


INTENSET

Enable interrupt
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAMPLERDY REPORTRDY ACCOF DBLRDY STOPPED

SAMPLERDY : Write '1' to Enable interrupt for SAMPLERDY event
bits : 0 - -1 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

REPORTRDY : Write '1' to Enable interrupt for REPORTRDY event
bits : 1 - 0 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

ACCOF : Write '1' to Enable interrupt for ACCOF event
bits : 2 - 1 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

DBLRDY : Write '1' to Enable interrupt for DBLRDY event
bits : 3 - 2 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

STOPPED : Write '1' to Enable interrupt for STOPPED event
bits : 4 - 3 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.


INTENCLR

Disable interrupt
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAMPLERDY REPORTRDY ACCOF DBLRDY STOPPED

SAMPLERDY : Write '1' to Disable interrupt for SAMPLERDY event
bits : 0 - -1 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

REPORTRDY : Write '1' to Disable interrupt for REPORTRDY event
bits : 1 - 0 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

ACCOF : Write '1' to Disable interrupt for ACCOF event
bits : 2 - 1 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

DBLRDY : Write '1' to Disable interrupt for DBLRDY event
bits : 3 - 2 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

STOPPED : Write '1' to Disable interrupt for STOPPED event
bits : 4 - 3 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.


TASKS_STOP

Task stopping the quadrature decoder
address_offset : 0x4 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_STOP TASKS_STOP write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PSEL - A

Unspecified - - Pin select for A signal
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSEL - A PSEL - A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN CONNECT

PIN : Pin number
bits : 0 - 3 (4 bit)

CONNECT : Connection
bits : 31 - 30 (0 bit)

Enumeration:

1 : Disconnected

Disconnect

0 : Connected

Connect

End of enumeration elements list.


ENABLE

Enable the quadrature decoder
address_offset : 0x500 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENABLE ENABLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE

ENABLE : Enable or disable the quadrature decoder
bits : 0 - -1 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.


LEDPOL

LED output pin polarity
address_offset : 0x504 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LEDPOL LEDPOL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEDPOL

LEDPOL : LED output pin polarity
bits : 0 - -1 (0 bit)

Enumeration:

0 : ActiveLow

Led active on output pin low

1 : ActiveHigh

Led active on output pin high

End of enumeration elements list.


SAMPLEPER

Sample period
address_offset : 0x508 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAMPLEPER SAMPLEPER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAMPLEPER

SAMPLEPER : Sample period. The SAMPLE register will be updated for every new sample
bits : 0 - 2 (3 bit)

Enumeration:

0 : 128us

128 us

1 : 256us

256 us

2 : 512us

512 us

3 : 1024us

1024 us

4 : 2048us

2048 us

5 : 4096us

4096 us

6 : 8192us

8192 us

7 : 16384us

16384 us

8 : 32ms

32768 us

9 : 65ms

65536 us

10 : 131ms

131072 us

End of enumeration elements list.


SAMPLE

Motion sample value
address_offset : 0x50C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SAMPLE SAMPLE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAMPLE

SAMPLE : Last motion sample
bits : 0 - 30 (31 bit)


REPORTPER

Number of samples to be taken before REPORTRDY and DBLRDY events can be generated
address_offset : 0x510 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REPORTPER REPORTPER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REPORTPER

REPORTPER : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated
bits : 0 - 2 (3 bit)

Enumeration:

0 : 10Smpl

10 samples / report

1 : 40Smpl

40 samples / report

2 : 80Smpl

80 samples / report

3 : 120Smpl

120 samples / report

4 : 160Smpl

160 samples / report

5 : 200Smpl

200 samples / report

6 : 240Smpl

240 samples / report

7 : 280Smpl

280 samples / report

8 : 1Smpl

1 sample / report

End of enumeration elements list.


ACC

Register accumulating the valid transitions
address_offset : 0x514 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ACC ACC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACC

ACC : Register accumulating all valid samples (not double transition) read from the SAMPLE register
bits : 0 - 30 (31 bit)


ACCREAD

Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task
address_offset : 0x518 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ACCREAD ACCREAD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACCREAD

ACCREAD : Snapshot of the ACC register.
bits : 0 - 30 (31 bit)


DBFEN

Enable input debounce filters
address_offset : 0x528 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBFEN DBFEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBFEN

DBFEN : Enable input debounce filters
bits : 0 - -1 (0 bit)

Enumeration:

0 : Disabled

Debounce input filters disabled

1 : Enabled

Debounce input filters enabled

End of enumeration elements list.


LEDPRE

Time period the LED is switched ON prior to sampling
address_offset : 0x540 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LEDPRE LEDPRE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEDPRE

LEDPRE : Period in us the LED is switched on prior to sampling
bits : 0 - 7 (8 bit)


ACCDBL

Register accumulating the number of detected double transitions
address_offset : 0x544 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ACCDBL ACCDBL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACCDBL

ACCDBL : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ).
bits : 0 - 2 (3 bit)


ACCDBLREAD

Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task
address_offset : 0x548 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ACCDBLREAD ACCDBLREAD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACCDBLREAD

ACCDBLREAD : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered.
bits : 0 - 2 (3 bit)


TASKS_READCLRACC

Read and clear ACC and ACCDBL
address_offset : 0x8 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_READCLRACC TASKS_READCLRACC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PSEL - B

Unspecified - - Pin select for B signal
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSEL - B PSEL - B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN CONNECT

PIN : Pin number
bits : 0 - 3 (4 bit)

CONNECT : Connection
bits : 31 - 30 (0 bit)

Enumeration:

1 : Disconnected

Disconnect

0 : Connected

Connect

End of enumeration elements list.


TASKS_RDCLRACC

Read and clear ACC
address_offset : 0xC Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_RDCLRACC TASKS_RDCLRACC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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