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PWM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PSEL - OUT[0]

TASKS_SEQSTART[0]

TASKS_NEXTSTEP

EVENTS_STOPPED

EVENTS_PWMPERIODEND

EVENTS_LOOPSDONE

PSEL - OUT[3]

TASKS_SEQSTART[1]

SHORTS

EVENTS_SEQSTARTED[0]

EVENTS_SEQEND[0]

INTEN

INTENSET

INTENCLR

EVENTS_SEQSTARTED[1]

EVENTS_SEQEND[1]

TASKS_STOP

PSEL - OUT[1]

ENABLE

MODE

COUNTERTOP

PRESCALER

DECODER

LOOP

SEQ[0]-PTR

SEQ[0]-CNT

SEQ[0]-REFRESH

SEQ[0]-ENDDELAY

SEQ[1]-SEQ[0]-PTR

SEQ[1]-SEQ[0]-CNT

SEQ[1]-SEQ[0]-REFRESH

SEQ[1]-SEQ[0]-ENDDELAY

PSEL - OUT[2]


PSEL - OUT[0]

Unspecified - - Description collection[0]: Output pin select for PWM channel 0
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSEL - OUT[0] PSEL - OUT[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN CONNECT

PIN : Pin number
bits : 0 - 3 (4 bit)

CONNECT : Connection
bits : 31 - 30 (0 bit)

Enumeration:

1 : Disconnected

Disconnect

0 : Connected

Connect

End of enumeration elements list.


TASKS_SEQSTART[0]

Description collection[0]: Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running.
address_offset : 0x10 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_SEQSTART[0] TASKS_SEQSTART[0] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TASKS_NEXTSTEP

Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start it was not running.
address_offset : 0x10 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_NEXTSTEP TASKS_NEXTSTEP write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EVENTS_STOPPED

Response to STOP task, emitted when PWM pulses are no longer generated
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_STOPPED EVENTS_STOPPED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EVENTS_PWMPERIODEND

Emitted at the end of each PWM period
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_PWMPERIODEND EVENTS_PWMPERIODEND read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EVENTS_LOOPSDONE

Concatenated sequences have been played the amount of times defined in LOOP.CNT
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_LOOPSDONE EVENTS_LOOPSDONE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PSEL - OUT[3]

Unspecified - - Description collection[0]: Output pin select for PWM channel 0
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSEL - OUT[3] PSEL - OUT[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN CONNECT

PIN : Pin number
bits : 0 - 3 (4 bit)

CONNECT : Connection
bits : 31 - 30 (0 bit)

Enumeration:

1 : Disconnected

Disconnect

0 : Connected

Connect

End of enumeration elements list.


TASKS_SEQSTART[1]

Description collection[0]: Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running.
address_offset : 0x1C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_SEQSTART[1] TASKS_SEQSTART[1] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SHORTS

Shortcut register
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHORTS SHORTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEQEND0_STOP SEQEND1_STOP LOOPSDONE_SEQSTART0 LOOPSDONE_SEQSTART1 LOOPSDONE_STOP

SEQEND0_STOP : Shortcut between SEQEND[0] event and STOP task
bits : 0 - -1 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.

SEQEND1_STOP : Shortcut between SEQEND[1] event and STOP task
bits : 1 - 0 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.

LOOPSDONE_SEQSTART0 : Shortcut between LOOPSDONE event and SEQSTART[0] task
bits : 2 - 1 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.

LOOPSDONE_SEQSTART1 : Shortcut between LOOPSDONE event and SEQSTART[1] task
bits : 3 - 2 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.

LOOPSDONE_STOP : Shortcut between LOOPSDONE event and STOP task
bits : 4 - 3 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.


EVENTS_SEQSTARTED[0]

Description collection[0]: First PWM period started on sequence 0
address_offset : 0x210 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_SEQSTARTED[0] EVENTS_SEQSTARTED[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EVENTS_SEQEND[0]

Description collection[0]: Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter
address_offset : 0x220 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_SEQEND[0] EVENTS_SEQEND[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

INTEN

Enable or disable interrupt
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STOPPED SEQSTARTED0 SEQSTARTED1 SEQEND0 SEQEND1 PWMPERIODEND LOOPSDONE

STOPPED : Enable or disable interrupt for STOPPED event
bits : 1 - 0 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

SEQSTARTED0 : Enable or disable interrupt for SEQSTARTED[0] event
bits : 2 - 1 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

SEQSTARTED1 : Enable or disable interrupt for SEQSTARTED[1] event
bits : 3 - 2 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

SEQEND0 : Enable or disable interrupt for SEQEND[0] event
bits : 4 - 3 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

SEQEND1 : Enable or disable interrupt for SEQEND[1] event
bits : 5 - 4 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

PWMPERIODEND : Enable or disable interrupt for PWMPERIODEND event
bits : 6 - 5 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

LOOPSDONE : Enable or disable interrupt for LOOPSDONE event
bits : 7 - 6 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.


INTENSET

Enable interrupt
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STOPPED SEQSTARTED0 SEQSTARTED1 SEQEND0 SEQEND1 PWMPERIODEND LOOPSDONE

STOPPED : Write '1' to Enable interrupt for STOPPED event
bits : 1 - 0 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

SEQSTARTED0 : Write '1' to Enable interrupt for SEQSTARTED[0] event
bits : 2 - 1 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

SEQSTARTED1 : Write '1' to Enable interrupt for SEQSTARTED[1] event
bits : 3 - 2 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

SEQEND0 : Write '1' to Enable interrupt for SEQEND[0] event
bits : 4 - 3 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

SEQEND1 : Write '1' to Enable interrupt for SEQEND[1] event
bits : 5 - 4 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

PWMPERIODEND : Write '1' to Enable interrupt for PWMPERIODEND event
bits : 6 - 5 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

LOOPSDONE : Write '1' to Enable interrupt for LOOPSDONE event
bits : 7 - 6 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.


INTENCLR

Disable interrupt
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STOPPED SEQSTARTED0 SEQSTARTED1 SEQEND0 SEQEND1 PWMPERIODEND LOOPSDONE

STOPPED : Write '1' to Disable interrupt for STOPPED event
bits : 1 - 0 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

SEQSTARTED0 : Write '1' to Disable interrupt for SEQSTARTED[0] event
bits : 2 - 1 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

SEQSTARTED1 : Write '1' to Disable interrupt for SEQSTARTED[1] event
bits : 3 - 2 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

SEQEND0 : Write '1' to Disable interrupt for SEQEND[0] event
bits : 4 - 3 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

SEQEND1 : Write '1' to Disable interrupt for SEQEND[1] event
bits : 5 - 4 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

PWMPERIODEND : Write '1' to Disable interrupt for PWMPERIODEND event
bits : 6 - 5 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

LOOPSDONE : Write '1' to Disable interrupt for LOOPSDONE event
bits : 7 - 6 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.


EVENTS_SEQSTARTED[1]

Description collection[0]: First PWM period started on sequence 0
address_offset : 0x31C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_SEQSTARTED[1] EVENTS_SEQSTARTED[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EVENTS_SEQEND[1]

Description collection[0]: Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter
address_offset : 0x334 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_SEQEND[1] EVENTS_SEQEND[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TASKS_STOP

Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback
address_offset : 0x4 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_STOP TASKS_STOP write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PSEL - OUT[1]

Unspecified - - Description collection[0]: Output pin select for PWM channel 0
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSEL - OUT[1] PSEL - OUT[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN CONNECT

PIN : Pin number
bits : 0 - 3 (4 bit)

CONNECT : Connection
bits : 31 - 30 (0 bit)

Enumeration:

1 : Disconnected

Disconnect

0 : Connected

Connect

End of enumeration elements list.


ENABLE

PWM module enable register
address_offset : 0x500 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENABLE ENABLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE

ENABLE : Enable or disable PWM module
bits : 0 - -1 (0 bit)

Enumeration:

0 : Disabled

Disabled

1 : Enabled

Enable

End of enumeration elements list.


MODE

Selects operating mode of the wave counter
address_offset : 0x504 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPDOWN

UPDOWN : Selects up or up and down as wave counter mode
bits : 0 - -1 (0 bit)

Enumeration:

0 : Up

Up counter - edge aligned PWM duty-cycle

1 : UpAndDown

Up and down counter - center aligned PWM duty cycle

End of enumeration elements list.


COUNTERTOP

Value up to which the pulse generator counter counts
address_offset : 0x508 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COUNTERTOP COUNTERTOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNTERTOP

COUNTERTOP : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used.
bits : 0 - 13 (14 bit)


PRESCALER

Configuration for PWM_CLK
address_offset : 0x50C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRESCALER PRESCALER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRESCALER

PRESCALER : Pre-scaler of PWM_CLK
bits : 0 - 1 (2 bit)

Enumeration:

0 : DIV_1

Divide by 1 (16MHz)

1 : DIV_2

Divide by 2 ( 8MHz)

2 : DIV_4

Divide by 4 ( 4MHz)

3 : DIV_8

Divide by 8 ( 2MHz)

4 : DIV_16

Divide by 16 ( 1MHz)

5 : DIV_32

Divide by 32 ( 500kHz)

6 : DIV_64

Divide by 64 ( 250kHz)

7 : DIV_128

Divide by 128 ( 125kHz)

End of enumeration elements list.


DECODER

Configuration of the decoder
address_offset : 0x510 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DECODER DECODER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOAD MODE

LOAD : How a sequence is read from RAM and spread to the compare register
bits : 0 - 0 (1 bit)

Enumeration:

0 : Common

1st half word (16-bit) used in all PWM channels 0..3

1 : Grouped

1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3

2 : Individual

1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3

3 : WaveForm

1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP

End of enumeration elements list.

MODE : Selects source for advancing the active sequence
bits : 8 - 7 (0 bit)

Enumeration:

0 : RefreshCount

SEQ[n].REFRESH is used to determine loading internal compare registers

1 : NextStep

NEXTSTEP task causes a new value to be loaded to internal compare registers

End of enumeration elements list.


LOOP

Amount of playback of a loop
address_offset : 0x514 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOOP LOOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Amount of playback of pattern cycles
bits : 0 - 14 (15 bit)

Enumeration:

0 : Disabled

Looping disabled (stop at the end of the sequence)

End of enumeration elements list.


SEQ[0]-PTR

Description cluster[0]: Beginning address in Data RAM of this sequence
address_offset : 0x520 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEQ[0]-PTR SEQ[0]-PTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTR

PTR : Beginning address in Data RAM of this sequence
bits : 0 - 30 (31 bit)


SEQ[0]-CNT

Description cluster[0]: Amount of values (duty cycles) in this sequence
address_offset : 0x524 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEQ[0]-CNT SEQ[0]-CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Amount of values (duty cycles) in this sequence
bits : 0 - 13 (14 bit)

Enumeration:

0 : Disabled

Sequence is disabled, and shall not be started as it is empty

End of enumeration elements list.


SEQ[0]-REFRESH

Description cluster[0]: Amount of additional PWM periods between samples loaded into compare register
address_offset : 0x528 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEQ[0]-REFRESH SEQ[0]-REFRESH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods)
bits : 0 - 22 (23 bit)

Enumeration:

0 : Continuous

Update every PWM period

End of enumeration elements list.


SEQ[0]-ENDDELAY

Description cluster[0]: Time added after the sequence
address_offset : 0x52C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEQ[0]-ENDDELAY SEQ[0]-ENDDELAY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Time added after the sequence in PWM periods
bits : 0 - 22 (23 bit)


SEQ[1]-SEQ[0]-PTR

Description cluster[0]: Beginning address in Data RAM of this sequence
address_offset : 0xA60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEQ[1]-SEQ[0]-PTR SEQ[1]-SEQ[0]-PTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTR

PTR : Beginning address in Data RAM of this sequence
bits : 0 - 30 (31 bit)


SEQ[1]-SEQ[0]-CNT

Description cluster[0]: Amount of values (duty cycles) in this sequence
address_offset : 0xA64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEQ[1]-SEQ[0]-CNT SEQ[1]-SEQ[0]-CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Amount of values (duty cycles) in this sequence
bits : 0 - 13 (14 bit)

Enumeration:

0 : Disabled

Sequence is disabled, and shall not be started as it is empty

End of enumeration elements list.


SEQ[1]-SEQ[0]-REFRESH

Description cluster[0]: Amount of additional PWM periods between samples loaded into compare register
address_offset : 0xA68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEQ[1]-SEQ[0]-REFRESH SEQ[1]-SEQ[0]-REFRESH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods)
bits : 0 - 22 (23 bit)

Enumeration:

0 : Continuous

Update every PWM period

End of enumeration elements list.


SEQ[1]-SEQ[0]-ENDDELAY

Description cluster[0]: Time added after the sequence
address_offset : 0xA6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEQ[1]-SEQ[0]-ENDDELAY SEQ[1]-SEQ[0]-ENDDELAY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Time added after the sequence in PWM periods
bits : 0 - 22 (23 bit)


PSEL - OUT[2]

Unspecified - - Description collection[0]: Output pin select for PWM channel 0
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSEL - OUT[2] PSEL - OUT[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN CONNECT

PIN : Pin number
bits : 0 - 3 (4 bit)

CONNECT : Connection
bits : 31 - 30 (0 bit)

Enumeration:

1 : Disconnected

Disconnect

0 : Connected

Connect

End of enumeration elements list.



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