\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Unspecified - - Description collection[0]: Output pin select for PWM channel 0
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIN : Pin number
bits : 0 - 3 (4 bit)
CONNECT : Connection
bits : 31 - 30 (0 bit)
Enumeration:
1 : Disconnected
Disconnect
0 : Connected
Connect
End of enumeration elements list.
Description collection[0]: Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running.
address_offset : 0x10 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start it was not running.
address_offset : 0x10 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
Response to STOP task, emitted when PWM pulses are no longer generated
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Emitted at the end of each PWM period
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Concatenated sequences have been played the amount of times defined in LOOP.CNT
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Unspecified - - Description collection[0]: Output pin select for PWM channel 0
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIN : Pin number
bits : 0 - 3 (4 bit)
CONNECT : Connection
bits : 31 - 30 (0 bit)
Enumeration:
1 : Disconnected
Disconnect
0 : Connected
Connect
End of enumeration elements list.
Description collection[0]: Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running.
address_offset : 0x1C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
Shortcut register
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEQEND0_STOP : Shortcut between SEQEND[0] event and STOP task
bits : 0 - -1 (0 bit)
Enumeration:
0 : Disabled
Disable shortcut
1 : Enabled
Enable shortcut
End of enumeration elements list.
SEQEND1_STOP : Shortcut between SEQEND[1] event and STOP task
bits : 1 - 0 (0 bit)
Enumeration:
0 : Disabled
Disable shortcut
1 : Enabled
Enable shortcut
End of enumeration elements list.
LOOPSDONE_SEQSTART0 : Shortcut between LOOPSDONE event and SEQSTART[0] task
bits : 2 - 1 (0 bit)
Enumeration:
0 : Disabled
Disable shortcut
1 : Enabled
Enable shortcut
End of enumeration elements list.
LOOPSDONE_SEQSTART1 : Shortcut between LOOPSDONE event and SEQSTART[1] task
bits : 3 - 2 (0 bit)
Enumeration:
0 : Disabled
Disable shortcut
1 : Enabled
Enable shortcut
End of enumeration elements list.
LOOPSDONE_STOP : Shortcut between LOOPSDONE event and STOP task
bits : 4 - 3 (0 bit)
Enumeration:
0 : Disabled
Disable shortcut
1 : Enabled
Enable shortcut
End of enumeration elements list.
Description collection[0]: First PWM period started on sequence 0
address_offset : 0x210 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Description collection[0]: Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter
address_offset : 0x220 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Enable or disable interrupt
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STOPPED : Enable or disable interrupt for STOPPED event
bits : 1 - 0 (0 bit)
Enumeration:
0 : Disabled
Disable
1 : Enabled
Enable
End of enumeration elements list.
SEQSTARTED0 : Enable or disable interrupt for SEQSTARTED[0] event
bits : 2 - 1 (0 bit)
Enumeration:
0 : Disabled
Disable
1 : Enabled
Enable
End of enumeration elements list.
SEQSTARTED1 : Enable or disable interrupt for SEQSTARTED[1] event
bits : 3 - 2 (0 bit)
Enumeration:
0 : Disabled
Disable
1 : Enabled
Enable
End of enumeration elements list.
SEQEND0 : Enable or disable interrupt for SEQEND[0] event
bits : 4 - 3 (0 bit)
Enumeration:
0 : Disabled
Disable
1 : Enabled
Enable
End of enumeration elements list.
SEQEND1 : Enable or disable interrupt for SEQEND[1] event
bits : 5 - 4 (0 bit)
Enumeration:
0 : Disabled
Disable
1 : Enabled
Enable
End of enumeration elements list.
PWMPERIODEND : Enable or disable interrupt for PWMPERIODEND event
bits : 6 - 5 (0 bit)
Enumeration:
0 : Disabled
Disable
1 : Enabled
Enable
End of enumeration elements list.
LOOPSDONE : Enable or disable interrupt for LOOPSDONE event
bits : 7 - 6 (0 bit)
Enumeration:
0 : Disabled
Disable
1 : Enabled
Enable
End of enumeration elements list.
Enable interrupt
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STOPPED : Write '1' to Enable interrupt for STOPPED event
bits : 1 - 0 (0 bit)
Enumeration: ( write )
1 : Set
Enable
End of enumeration elements list.
SEQSTARTED0 : Write '1' to Enable interrupt for SEQSTARTED[0] event
bits : 2 - 1 (0 bit)
Enumeration: ( write )
1 : Set
Enable
End of enumeration elements list.
SEQSTARTED1 : Write '1' to Enable interrupt for SEQSTARTED[1] event
bits : 3 - 2 (0 bit)
Enumeration: ( write )
1 : Set
Enable
End of enumeration elements list.
SEQEND0 : Write '1' to Enable interrupt for SEQEND[0] event
bits : 4 - 3 (0 bit)
Enumeration: ( write )
1 : Set
Enable
End of enumeration elements list.
SEQEND1 : Write '1' to Enable interrupt for SEQEND[1] event
bits : 5 - 4 (0 bit)
Enumeration: ( write )
1 : Set
Enable
End of enumeration elements list.
PWMPERIODEND : Write '1' to Enable interrupt for PWMPERIODEND event
bits : 6 - 5 (0 bit)
Enumeration: ( write )
1 : Set
Enable
End of enumeration elements list.
LOOPSDONE : Write '1' to Enable interrupt for LOOPSDONE event
bits : 7 - 6 (0 bit)
Enumeration: ( write )
1 : Set
Enable
End of enumeration elements list.
Disable interrupt
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STOPPED : Write '1' to Disable interrupt for STOPPED event
bits : 1 - 0 (0 bit)
Enumeration: ( write )
1 : Clear
Disable
End of enumeration elements list.
SEQSTARTED0 : Write '1' to Disable interrupt for SEQSTARTED[0] event
bits : 2 - 1 (0 bit)
Enumeration: ( write )
1 : Clear
Disable
End of enumeration elements list.
SEQSTARTED1 : Write '1' to Disable interrupt for SEQSTARTED[1] event
bits : 3 - 2 (0 bit)
Enumeration: ( write )
1 : Clear
Disable
End of enumeration elements list.
SEQEND0 : Write '1' to Disable interrupt for SEQEND[0] event
bits : 4 - 3 (0 bit)
Enumeration: ( write )
1 : Clear
Disable
End of enumeration elements list.
SEQEND1 : Write '1' to Disable interrupt for SEQEND[1] event
bits : 5 - 4 (0 bit)
Enumeration: ( write )
1 : Clear
Disable
End of enumeration elements list.
PWMPERIODEND : Write '1' to Disable interrupt for PWMPERIODEND event
bits : 6 - 5 (0 bit)
Enumeration: ( write )
1 : Clear
Disable
End of enumeration elements list.
LOOPSDONE : Write '1' to Disable interrupt for LOOPSDONE event
bits : 7 - 6 (0 bit)
Enumeration: ( write )
1 : Clear
Disable
End of enumeration elements list.
Description collection[0]: First PWM period started on sequence 0
address_offset : 0x31C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Description collection[0]: Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter
address_offset : 0x334 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback
address_offset : 0x4 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
Unspecified - - Description collection[0]: Output pin select for PWM channel 0
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIN : Pin number
bits : 0 - 3 (4 bit)
CONNECT : Connection
bits : 31 - 30 (0 bit)
Enumeration:
1 : Disconnected
Disconnect
0 : Connected
Connect
End of enumeration elements list.
PWM module enable register
address_offset : 0x500 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Enable or disable PWM module
bits : 0 - -1 (0 bit)
Enumeration:
0 : Disabled
Disabled
1 : Enabled
Enable
End of enumeration elements list.
Selects operating mode of the wave counter
address_offset : 0x504 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPDOWN : Selects up or up and down as wave counter mode
bits : 0 - -1 (0 bit)
Enumeration:
0 : Up
Up counter - edge aligned PWM duty-cycle
1 : UpAndDown
Up and down counter - center aligned PWM duty cycle
End of enumeration elements list.
Value up to which the pulse generator counter counts
address_offset : 0x508 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTERTOP : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used.
bits : 0 - 13 (14 bit)
Configuration for PWM_CLK
address_offset : 0x50C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESCALER : Pre-scaler of PWM_CLK
bits : 0 - 1 (2 bit)
Enumeration:
0 : DIV_1
Divide by 1 (16MHz)
1 : DIV_2
Divide by 2 ( 8MHz)
2 : DIV_4
Divide by 4 ( 4MHz)
3 : DIV_8
Divide by 8 ( 2MHz)
4 : DIV_16
Divide by 16 ( 1MHz)
5 : DIV_32
Divide by 32 ( 500kHz)
6 : DIV_64
Divide by 64 ( 250kHz)
7 : DIV_128
Divide by 128 ( 125kHz)
End of enumeration elements list.
Configuration of the decoder
address_offset : 0x510 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOAD : How a sequence is read from RAM and spread to the compare register
bits : 0 - 0 (1 bit)
Enumeration:
0 : Common
1st half word (16-bit) used in all PWM channels 0..3
1 : Grouped
1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3
2 : Individual
1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3
3 : WaveForm
1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP
End of enumeration elements list.
MODE : Selects source for advancing the active sequence
bits : 8 - 7 (0 bit)
Enumeration:
0 : RefreshCount
SEQ[n].REFRESH is used to determine loading internal compare registers
1 : NextStep
NEXTSTEP task causes a new value to be loaded to internal compare registers
End of enumeration elements list.
Amount of playback of a loop
address_offset : 0x514 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Amount of playback of pattern cycles
bits : 0 - 14 (15 bit)
Enumeration:
0 : Disabled
Looping disabled (stop at the end of the sequence)
End of enumeration elements list.
Description cluster[0]: Beginning address in Data RAM of this sequence
address_offset : 0x520 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PTR : Beginning address in Data RAM of this sequence
bits : 0 - 30 (31 bit)
Description cluster[0]: Amount of values (duty cycles) in this sequence
address_offset : 0x524 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Amount of values (duty cycles) in this sequence
bits : 0 - 13 (14 bit)
Enumeration:
0 : Disabled
Sequence is disabled, and shall not be started as it is empty
End of enumeration elements list.
Description cluster[0]: Amount of additional PWM periods between samples loaded into compare register
address_offset : 0x528 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods)
bits : 0 - 22 (23 bit)
Enumeration:
0 : Continuous
Update every PWM period
End of enumeration elements list.
Description cluster[0]: Time added after the sequence
address_offset : 0x52C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Time added after the sequence in PWM periods
bits : 0 - 22 (23 bit)
Description cluster[0]: Beginning address in Data RAM of this sequence
address_offset : 0xA60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PTR : Beginning address in Data RAM of this sequence
bits : 0 - 30 (31 bit)
Description cluster[0]: Amount of values (duty cycles) in this sequence
address_offset : 0xA64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Amount of values (duty cycles) in this sequence
bits : 0 - 13 (14 bit)
Enumeration:
0 : Disabled
Sequence is disabled, and shall not be started as it is empty
End of enumeration elements list.
Description cluster[0]: Amount of additional PWM periods between samples loaded into compare register
address_offset : 0xA68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods)
bits : 0 - 22 (23 bit)
Enumeration:
0 : Continuous
Update every PWM period
End of enumeration elements list.
Description cluster[0]: Time added after the sequence
address_offset : 0xA6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Time added after the sequence in PWM periods
bits : 0 - 22 (23 bit)
Unspecified - - Description collection[0]: Output pin select for PWM channel 0
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIN : Pin number
bits : 0 - 3 (4 bit)
CONNECT : Connection
bits : 31 - 30 (0 bit)
Enumeration:
1 : Disconnected
Disconnect
0 : Connected
Connect
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.