\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Starts continuous PDM transfer
address_offset : 0x0 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
Unspecified - - Pin number configuration for PDM CLK signal
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIN : Pin number
bits : 0 - 3 (4 bit)
CONNECT : Connection
bits : 31 - 30 (0 bit)
Enumeration:
1 : Disconnected
Disconnect
0 : Connected
Connect
End of enumeration elements list.
Unspecified - - RAM address pointer to write samples to with EasyDMA
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAMPLEPTR : Address to write PDM samples to over DMA
bits : 0 - 30 (31 bit)
PDM transfer has started
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDM transfer has finished
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Enable or disable interrupt
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STARTED : Enable or disable interrupt for STARTED event
bits : 0 - -1 (0 bit)
Enumeration:
0 : Disabled
Disable
1 : Enabled
Enable
End of enumeration elements list.
STOPPED : Enable or disable interrupt for STOPPED event
bits : 1 - 0 (0 bit)
Enumeration:
0 : Disabled
Disable
1 : Enabled
Enable
End of enumeration elements list.
END : Enable or disable interrupt for END event
bits : 2 - 1 (0 bit)
Enumeration:
0 : Disabled
Disable
1 : Enabled
Enable
End of enumeration elements list.
Enable interrupt
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STARTED : Write '1' to Enable interrupt for STARTED event
bits : 0 - -1 (0 bit)
Enumeration: ( write )
1 : Set
Enable
End of enumeration elements list.
STOPPED : Write '1' to Enable interrupt for STOPPED event
bits : 1 - 0 (0 bit)
Enumeration: ( write )
1 : Set
Enable
End of enumeration elements list.
END : Write '1' to Enable interrupt for END event
bits : 2 - 1 (0 bit)
Enumeration: ( write )
1 : Set
Enable
End of enumeration elements list.
Disable interrupt
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STARTED : Write '1' to Disable interrupt for STARTED event
bits : 0 - -1 (0 bit)
Enumeration: ( write )
1 : Clear
Disable
End of enumeration elements list.
STOPPED : Write '1' to Disable interrupt for STOPPED event
bits : 1 - 0 (0 bit)
Enumeration: ( write )
1 : Clear
Disable
End of enumeration elements list.
END : Write '1' to Disable interrupt for END event
bits : 2 - 1 (0 bit)
Enumeration: ( write )
1 : Clear
Disable
End of enumeration elements list.
Stops PDM transfer
address_offset : 0x4 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
Unspecified - - Pin number configuration for PDM DIN signal
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIN : Pin number
bits : 0 - 3 (4 bit)
CONNECT : Connection
bits : 31 - 30 (0 bit)
Enumeration:
1 : Disconnected
Disconnect
0 : Connected
Connect
End of enumeration elements list.
Unspecified - - Number of samples to allocate memory for in EasyDMA mode
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFFSIZE : Length of DMA RAM allocation in number of samples
bits : 0 - 13 (14 bit)
PDM module enable register
address_offset : 0x500 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Enable or disable PDM module
bits : 0 - -1 (0 bit)
Enumeration:
0 : Disabled
Disable
1 : Enabled
Enable
End of enumeration elements list.
PDM clock generator control
address_offset : 0x504 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQ : PDM_CLK frequency
bits : 0 - 30 (31 bit)
Enumeration:
0x08000000 : 1000K
PDM_CLK = 32 MHz / 32 = 1.000 MHz
0x08400000 : Default
PDM_CLK = 32 MHz / 31 = 1.032 MHz
0x08800000 : 1067K
PDM_CLK = 32 MHz / 30 = 1.067 MHz
End of enumeration elements list.
Defines the routing of the connected PDM microphones' signals
address_offset : 0x508 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERATION : Mono or stereo operation
bits : 0 - -1 (0 bit)
Enumeration:
0 : Stereo
Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0]
1 : Mono
Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0]
End of enumeration elements list.
EDGE : Defines on which PDM_CLK edge Left (or mono) is sampled
bits : 1 - 0 (0 bit)
Enumeration:
0 : LeftFalling
Left (or mono) is sampled on falling edge of PDM_CLK
1 : LeftRising
Left (or mono) is sampled on rising edge of PDM_CLK
End of enumeration elements list.
Left output gain adjustment
address_offset : 0x518 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAINL : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust
bits : 0 - 5 (6 bit)
Enumeration:
0x00 : MinGain
-20dB gain adjustment (minimum)
0x28 : DefaultGain
0dB gain adjustment ('2500 RMS' requirement)
0x50 : MaxGain
+20dB gain adjustment (maximum)
End of enumeration elements list.
Right output gain adjustment
address_offset : 0x51C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAINR : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters)
bits : 0 - 6 (7 bit)
Enumeration:
0x00 : MinGain
-20dB gain adjustment (minimum)
0x28 : DefaultGain
0dB gain adjustment ('2500 RMS' requirement)
0x50 : MaxGain
+20dB gain adjustment (maximum)
End of enumeration elements list.
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