\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Unspecified - - Pin select for SCK
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIN : Pin number
bits : 0 - 3 (4 bit)
PORT : Port number
bits : 5 - 4 (0 bit)
CONNECT : Connection
bits : 31 - 30 (0 bit)
Enumeration:
1 : Disconnected
Disconnect
0 : Connected
Connect
End of enumeration elements list.
RXD EasyDMA channel - - Data pointer
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PTR : Data pointer
bits : 0 - 30 (31 bit)
TXD EasyDMA channel - - Data pointer
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PTR : Data pointer
bits : 0 - 30 (31 bit)
Unspecified - - Sample delay for input serial data on MISO
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDELAY : Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK.
bits : 0 - 1 (2 bit)
Start SPI transaction
address_offset : 0x10 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TASKS_START : Start SPI transaction
bits : 0 - -1 (0 bit)
Enumeration:
1 : Trigger
Trigger task
End of enumeration elements list.
SPI transaction has stopped
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVENTS_STOPPED : SPI transaction has stopped
bits : 0 - -1 (0 bit)
Enumeration:
0 : NotGenerated
Event not generated
1 : Generated
Event generated
End of enumeration elements list.
End of RXD buffer reached
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVENTS_ENDRX : End of RXD buffer reached
bits : 0 - -1 (0 bit)
Enumeration:
0 : NotGenerated
Event not generated
1 : Generated
Event generated
End of enumeration elements list.
End of RXD buffer and TXD buffer reached
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVENTS_END : End of RXD buffer and TXD buffer reached
bits : 0 - -1 (0 bit)
Enumeration:
0 : NotGenerated
Event not generated
1 : Generated
Event generated
End of enumeration elements list.
End of TXD buffer reached
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVENTS_ENDTX : End of TXD buffer reached
bits : 0 - -1 (0 bit)
Enumeration:
0 : NotGenerated
Event not generated
1 : Generated
Event generated
End of enumeration elements list.
Stop SPI transaction
address_offset : 0x14 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TASKS_STOP : Stop SPI transaction
bits : 0 - -1 (0 bit)
Enumeration:
1 : Trigger
Trigger task
End of enumeration elements list.
Transaction started
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVENTS_STARTED : Transaction started
bits : 0 - -1 (0 bit)
Enumeration:
0 : NotGenerated
Event not generated
1 : Generated
Event generated
End of enumeration elements list.
Publish configuration for event STOPPED
address_offset : 0x184 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIDX : DPPI channel that event STOPPED will publish to.
bits : 0 - 6 (7 bit)
EN :
bits : 31 - 30 (0 bit)
Enumeration:
0 : Disabled
Disable publishing
1 : Enabled
Enable publishing
End of enumeration elements list.
Publish configuration for event ENDRX
address_offset : 0x190 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIDX : DPPI channel that event ENDRX will publish to.
bits : 0 - 6 (7 bit)
EN :
bits : 31 - 30 (0 bit)
Enumeration:
0 : Disabled
Disable publishing
1 : Enabled
Enable publishing
End of enumeration elements list.
Publish configuration for event END
address_offset : 0x198 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIDX : DPPI channel that event END will publish to.
bits : 0 - 6 (7 bit)
EN :
bits : 31 - 30 (0 bit)
Enumeration:
0 : Disabled
Disable publishing
1 : Enabled
Enable publishing
End of enumeration elements list.
Publish configuration for event ENDTX
address_offset : 0x1A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIDX : DPPI channel that event ENDTX will publish to.
bits : 0 - 6 (7 bit)
EN :
bits : 31 - 30 (0 bit)
Enumeration:
0 : Disabled
Disable publishing
1 : Enabled
Enable publishing
End of enumeration elements list.
Suspend SPI transaction
address_offset : 0x1C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TASKS_SUSPEND : Suspend SPI transaction
bits : 0 - -1 (0 bit)
Enumeration:
1 : Trigger
Trigger task
End of enumeration elements list.
Publish configuration for event STARTED
address_offset : 0x1CC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIDX : DPPI channel that event STARTED will publish to.
bits : 0 - 6 (7 bit)
EN :
bits : 31 - 30 (0 bit)
Enumeration:
0 : Disabled
Disable publishing
1 : Enabled
Enable publishing
End of enumeration elements list.
Resume SPI transaction
address_offset : 0x20 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TASKS_RESUME : Resume SPI transaction
bits : 0 - -1 (0 bit)
Enumeration:
1 : Trigger
Trigger task
End of enumeration elements list.
Shortcuts between local events and tasks
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
END_START : Shortcut between event END and task START
bits : 17 - 16 (0 bit)
Enumeration:
0 : Disabled
Disable shortcut
1 : Enabled
Enable shortcut
End of enumeration elements list.
Enable interrupt
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STOPPED : Write '1' to enable interrupt for event STOPPED
bits : 1 - 0 (0 bit)
Enumeration: ( write )
1 : Set
Enable
End of enumeration elements list.
ENDRX : Write '1' to enable interrupt for event ENDRX
bits : 4 - 3 (0 bit)
Enumeration: ( write )
1 : Set
Enable
End of enumeration elements list.
END : Write '1' to enable interrupt for event END
bits : 6 - 5 (0 bit)
Enumeration: ( write )
1 : Set
Enable
End of enumeration elements list.
ENDTX : Write '1' to enable interrupt for event ENDTX
bits : 8 - 7 (0 bit)
Enumeration: ( write )
1 : Set
Enable
End of enumeration elements list.
STARTED : Write '1' to enable interrupt for event STARTED
bits : 19 - 18 (0 bit)
Enumeration: ( write )
1 : Set
Enable
End of enumeration elements list.
Disable interrupt
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STOPPED : Write '1' to disable interrupt for event STOPPED
bits : 1 - 0 (0 bit)
Enumeration: ( write )
1 : Clear
Disable
End of enumeration elements list.
ENDRX : Write '1' to disable interrupt for event ENDRX
bits : 4 - 3 (0 bit)
Enumeration: ( write )
1 : Clear
Disable
End of enumeration elements list.
END : Write '1' to disable interrupt for event END
bits : 6 - 5 (0 bit)
Enumeration: ( write )
1 : Clear
Disable
End of enumeration elements list.
ENDTX : Write '1' to disable interrupt for event ENDTX
bits : 8 - 7 (0 bit)
Enumeration: ( write )
1 : Clear
Disable
End of enumeration elements list.
STARTED : Write '1' to disable interrupt for event STARTED
bits : 19 - 18 (0 bit)
Enumeration: ( write )
1 : Clear
Disable
End of enumeration elements list.
Unspecified - - Pin select for MOSI signal
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIN : Pin number
bits : 0 - 3 (4 bit)
PORT : Port number
bits : 5 - 4 (0 bit)
CONNECT : Connection
bits : 31 - 30 (0 bit)
Enumeration:
1 : Disconnected
Disconnect
0 : Connected
Connect
End of enumeration elements list.
RXD EasyDMA channel - - Maximum number of bytes in receive buffer
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXCNT : Maximum number of bytes in receive buffer
bits : 0 - 14 (15 bit)
TXD EasyDMA channel - - Number of bytes in transmit buffer
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXCNT : Maximum number of bytes in transmit buffer
bits : 0 - 14 (15 bit)
Unspecified - - Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSNDUR : Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns).
bits : 0 - 6 (7 bit)
Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU.
address_offset : 0x400 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX : Stall status for EasyDMA RAM reads
bits : 0 - -1 (0 bit)
Enumeration:
0 : NOSTALL
No stall
1 : STALL
A stall has occurred
End of enumeration elements list.
RX : Stall status for EasyDMA RAM writes
bits : 1 - 0 (0 bit)
Enumeration:
0 : NOSTALL
No stall
1 : STALL
A stall has occurred
End of enumeration elements list.
Enable SPIM
address_offset : 0x500 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Enable or disable SPIM
bits : 0 - 2 (3 bit)
Enumeration:
0 : Disabled
Disable SPIM
7 : Enabled
Enable SPIM
End of enumeration elements list.
SPI frequency. Accuracy depends on the HFCLK source selected.
address_offset : 0x524 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQUENCY : SPI master data rate
bits : 0 - 30 (31 bit)
Enumeration:
0x02000000 : K125
125 kbps
0x04000000 : K250
250 kbps
0x08000000 : K500
500 kbps
0x10000000 : M1
1 Mbps
0x20000000 : M2
2 Mbps
0x40000000 : M4
4 Mbps
0x80000000 : M8
8 Mbps
0x0A000000 : M16
16 Mbps
0x14000000 : M32
32 Mbps
End of enumeration elements list.
Configuration register
address_offset : 0x554 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ORDER : Bit order
bits : 0 - -1 (0 bit)
Enumeration:
0 : MsbFirst
Most significant bit shifted out first
1 : LsbFirst
Least significant bit shifted out first
End of enumeration elements list.
CPHA : Serial clock (SCK) phase
bits : 1 - 0 (0 bit)
Enumeration:
0 : Leading
Sample on leading edge of clock, shift serial data on trailing edge
1 : Trailing
Sample on trailing edge of clock, shift serial data on leading edge
End of enumeration elements list.
CPOL : Serial clock (SCK) polarity
bits : 2 - 1 (0 bit)
Enumeration:
0 : ActiveHigh
Active high
1 : ActiveLow
Active low
End of enumeration elements list.
Polarity of CSN output
address_offset : 0x568 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSNPOL : Polarity of CSN output
bits : 0 - -1 (0 bit)
Enumeration:
0 : LOW
Active low (idle state high)
1 : HIGH
Active high (idle state low)
End of enumeration elements list.
Pin select for DCX signal
address_offset : 0x56C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIN : Pin number
bits : 0 - 3 (4 bit)
PORT : Port number
bits : 5 - 4 (0 bit)
CONNECT : Connection
bits : 31 - 30 (0 bit)
Enumeration:
1 : Disconnected
Disconnect
0 : Connected
Connect
End of enumeration elements list.
DCX configuration
address_offset : 0x570 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCXCNT : This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes.
bits : 0 - 2 (3 bit)
Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT
address_offset : 0x5C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ORC : Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT.
bits : 0 - 6 (7 bit)
Unspecified - - Pin select for MISO signal
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIN : Pin number
bits : 0 - 3 (4 bit)
PORT : Port number
bits : 5 - 4 (0 bit)
CONNECT : Connection
bits : 31 - 30 (0 bit)
Enumeration:
1 : Disconnected
Disconnect
0 : Connected
Connect
End of enumeration elements list.
RXD EasyDMA channel - - Number of bytes transferred in the last transaction
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AMOUNT : Number of bytes transferred in the last transaction
bits : 0 - 14 (15 bit)
TXD EasyDMA channel - - Number of bytes transferred in the last transaction
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AMOUNT : Number of bytes transferred in the last transaction
bits : 0 - 14 (15 bit)
Subscribe configuration for task START
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIDX : DPPI channel that task START will subscribe to
bits : 0 - 6 (7 bit)
EN :
bits : 31 - 30 (0 bit)
Enumeration:
0 : Disabled
Disable subscription
1 : Enabled
Enable subscription
End of enumeration elements list.
Subscribe configuration for task STOP
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIDX : DPPI channel that task STOP will subscribe to
bits : 0 - 6 (7 bit)
EN :
bits : 31 - 30 (0 bit)
Enumeration:
0 : Disabled
Disable subscription
1 : Enabled
Enable subscription
End of enumeration elements list.
Subscribe configuration for task SUSPEND
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIDX : DPPI channel that task SUSPEND will subscribe to
bits : 0 - 6 (7 bit)
EN :
bits : 31 - 30 (0 bit)
Enumeration:
0 : Disabled
Disable subscription
1 : Enabled
Enable subscription
End of enumeration elements list.
Subscribe configuration for task RESUME
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIDX : DPPI channel that task RESUME will subscribe to
bits : 0 - 6 (7 bit)
EN :
bits : 31 - 30 (0 bit)
Enumeration:
0 : Disabled
Disable subscription
1 : Enabled
Enable subscription
End of enumeration elements list.
Unspecified - - Pin select for CSN
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIN : Pin number
bits : 0 - 3 (4 bit)
PORT : Port number
bits : 5 - 4 (0 bit)
CONNECT : Connection
bits : 31 - 30 (0 bit)
Enumeration:
1 : Disconnected
Disconnect
0 : Connected
Connect
End of enumeration elements list.
RXD EasyDMA channel - - EasyDMA list type
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LIST : List type
bits : 0 - 0 (1 bit)
Enumeration:
0 : Disabled
Disable EasyDMA list
1 : ArrayList
Use array list
End of enumeration elements list.
TXD EasyDMA channel - - EasyDMA list type
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LIST : List type
bits : 0 - 0 (1 bit)
Enumeration:
0 : Disabled
Disable EasyDMA list
1 : ArrayList
Use array list
End of enumeration elements list.
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