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SPIM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PSEL - SCK

RXD - PTR

TXD - PTR

IFTIMING - RXDELAY

TASKS_START

EVENTS_STOPPED

EVENTS_ENDRX

EVENTS_END

EVENTS_ENDTX

TASKS_STOP

EVENTS_STARTED

PUBLISH_STOPPED

PUBLISH_ENDRX

PUBLISH_END

PUBLISH_ENDTX

TASKS_SUSPEND

PUBLISH_STARTED

TASKS_RESUME

SHORTS

INTENSET

INTENCLR

PSEL - MOSI

RXD - MAXCNT

TXD - MAXCNT

IFTIMING - CSNDUR

STALLSTAT

ENABLE

FREQUENCY

CONFIG

CSNPOL

PSELDCX

DCXCNT

ORC

PSEL - MISO

RXD - AMOUNT

TXD - AMOUNT

SUBSCRIBE_START

SUBSCRIBE_STOP

SUBSCRIBE_SUSPEND

SUBSCRIBE_RESUME

PSEL - CSN

RXD - LIST

TXD - LIST


PSEL - SCK

Unspecified - - Pin select for SCK
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSEL - SCK PSEL - SCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN PORT CONNECT

PIN : Pin number
bits : 0 - 3 (4 bit)

PORT : Port number
bits : 5 - 4 (0 bit)

CONNECT : Connection
bits : 31 - 30 (0 bit)

Enumeration:

1 : Disconnected

Disconnect

0 : Connected

Connect

End of enumeration elements list.


RXD - PTR

RXD EasyDMA channel - - Data pointer
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXD - PTR RXD - PTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTR

PTR : Data pointer
bits : 0 - 30 (31 bit)


TXD - PTR

TXD EasyDMA channel - - Data pointer
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXD - PTR TXD - PTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTR

PTR : Data pointer
bits : 0 - 30 (31 bit)


IFTIMING - RXDELAY

Unspecified - - Sample delay for input serial data on MISO
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFTIMING - RXDELAY IFTIMING - RXDELAY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDELAY

RXDELAY : Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK.
bits : 0 - 1 (2 bit)


TASKS_START

Start SPI transaction
address_offset : 0x10 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_START TASKS_START write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_START

TASKS_START : Start SPI transaction
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


EVENTS_STOPPED

SPI transaction has stopped
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_STOPPED EVENTS_STOPPED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_STOPPED

EVENTS_STOPPED : SPI transaction has stopped
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


EVENTS_ENDRX

End of RXD buffer reached
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_ENDRX EVENTS_ENDRX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_ENDRX

EVENTS_ENDRX : End of RXD buffer reached
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


EVENTS_END

End of RXD buffer and TXD buffer reached
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_END EVENTS_END read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_END

EVENTS_END : End of RXD buffer and TXD buffer reached
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


EVENTS_ENDTX

End of TXD buffer reached
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_ENDTX EVENTS_ENDTX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_ENDTX

EVENTS_ENDTX : End of TXD buffer reached
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


TASKS_STOP

Stop SPI transaction
address_offset : 0x14 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_STOP TASKS_STOP write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_STOP

TASKS_STOP : Stop SPI transaction
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


EVENTS_STARTED

Transaction started
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_STARTED EVENTS_STARTED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_STARTED

EVENTS_STARTED : Transaction started
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


PUBLISH_STOPPED

Publish configuration for event STOPPED
address_offset : 0x184 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUBLISH_STOPPED PUBLISH_STOPPED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that event STOPPED will publish to.
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable publishing

1 : Enabled

Enable publishing

End of enumeration elements list.


PUBLISH_ENDRX

Publish configuration for event ENDRX
address_offset : 0x190 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUBLISH_ENDRX PUBLISH_ENDRX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that event ENDRX will publish to.
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable publishing

1 : Enabled

Enable publishing

End of enumeration elements list.


PUBLISH_END

Publish configuration for event END
address_offset : 0x198 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUBLISH_END PUBLISH_END read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that event END will publish to.
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable publishing

1 : Enabled

Enable publishing

End of enumeration elements list.


PUBLISH_ENDTX

Publish configuration for event ENDTX
address_offset : 0x1A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUBLISH_ENDTX PUBLISH_ENDTX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that event ENDTX will publish to.
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable publishing

1 : Enabled

Enable publishing

End of enumeration elements list.


TASKS_SUSPEND

Suspend SPI transaction
address_offset : 0x1C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_SUSPEND TASKS_SUSPEND write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_SUSPEND

TASKS_SUSPEND : Suspend SPI transaction
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


PUBLISH_STARTED

Publish configuration for event STARTED
address_offset : 0x1CC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUBLISH_STARTED PUBLISH_STARTED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that event STARTED will publish to.
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable publishing

1 : Enabled

Enable publishing

End of enumeration elements list.


TASKS_RESUME

Resume SPI transaction
address_offset : 0x20 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_RESUME TASKS_RESUME write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_RESUME

TASKS_RESUME : Resume SPI transaction
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


SHORTS

Shortcuts between local events and tasks
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHORTS SHORTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 END_START

END_START : Shortcut between event END and task START
bits : 17 - 16 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.


INTENSET

Enable interrupt
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STOPPED ENDRX END ENDTX STARTED

STOPPED : Write '1' to enable interrupt for event STOPPED
bits : 1 - 0 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

ENDRX : Write '1' to enable interrupt for event ENDRX
bits : 4 - 3 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

END : Write '1' to enable interrupt for event END
bits : 6 - 5 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

ENDTX : Write '1' to enable interrupt for event ENDTX
bits : 8 - 7 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

STARTED : Write '1' to enable interrupt for event STARTED
bits : 19 - 18 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.


INTENCLR

Disable interrupt
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STOPPED ENDRX END ENDTX STARTED

STOPPED : Write '1' to disable interrupt for event STOPPED
bits : 1 - 0 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

ENDRX : Write '1' to disable interrupt for event ENDRX
bits : 4 - 3 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

END : Write '1' to disable interrupt for event END
bits : 6 - 5 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

ENDTX : Write '1' to disable interrupt for event ENDTX
bits : 8 - 7 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

STARTED : Write '1' to disable interrupt for event STARTED
bits : 19 - 18 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.


PSEL - MOSI

Unspecified - - Pin select for MOSI signal
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSEL - MOSI PSEL - MOSI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN PORT CONNECT

PIN : Pin number
bits : 0 - 3 (4 bit)

PORT : Port number
bits : 5 - 4 (0 bit)

CONNECT : Connection
bits : 31 - 30 (0 bit)

Enumeration:

1 : Disconnected

Disconnect

0 : Connected

Connect

End of enumeration elements list.


RXD - MAXCNT

RXD EasyDMA channel - - Maximum number of bytes in receive buffer
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXD - MAXCNT RXD - MAXCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAXCNT

MAXCNT : Maximum number of bytes in receive buffer
bits : 0 - 14 (15 bit)


TXD - MAXCNT

TXD EasyDMA channel - - Number of bytes in transmit buffer
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXD - MAXCNT TXD - MAXCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAXCNT

MAXCNT : Maximum number of bytes in transmit buffer
bits : 0 - 14 (15 bit)


IFTIMING - CSNDUR

Unspecified - - Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFTIMING - CSNDUR IFTIMING - CSNDUR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSNDUR

CSNDUR : Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns).
bits : 0 - 6 (7 bit)


STALLSTAT

Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU.
address_offset : 0x400 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STALLSTAT STALLSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX RX

TX : Stall status for EasyDMA RAM reads
bits : 0 - -1 (0 bit)

Enumeration:

0 : NOSTALL

No stall

1 : STALL

A stall has occurred

End of enumeration elements list.

RX : Stall status for EasyDMA RAM writes
bits : 1 - 0 (0 bit)

Enumeration:

0 : NOSTALL

No stall

1 : STALL

A stall has occurred

End of enumeration elements list.


ENABLE

Enable SPIM
address_offset : 0x500 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENABLE ENABLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE

ENABLE : Enable or disable SPIM
bits : 0 - 2 (3 bit)

Enumeration:

0 : Disabled

Disable SPIM

7 : Enabled

Enable SPIM

End of enumeration elements list.


FREQUENCY

SPI frequency. Accuracy depends on the HFCLK source selected.
address_offset : 0x524 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FREQUENCY FREQUENCY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FREQUENCY

FREQUENCY : SPI master data rate
bits : 0 - 30 (31 bit)

Enumeration:

0x02000000 : K125

125 kbps

0x04000000 : K250

250 kbps

0x08000000 : K500

500 kbps

0x10000000 : M1

1 Mbps

0x20000000 : M2

2 Mbps

0x40000000 : M4

4 Mbps

0x80000000 : M8

8 Mbps

0x0A000000 : M16

16 Mbps

0x14000000 : M32

32 Mbps

End of enumeration elements list.


CONFIG

Configuration register
address_offset : 0x554 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONFIG CONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ORDER CPHA CPOL

ORDER : Bit order
bits : 0 - -1 (0 bit)

Enumeration:

0 : MsbFirst

Most significant bit shifted out first

1 : LsbFirst

Least significant bit shifted out first

End of enumeration elements list.

CPHA : Serial clock (SCK) phase
bits : 1 - 0 (0 bit)

Enumeration:

0 : Leading

Sample on leading edge of clock, shift serial data on trailing edge

1 : Trailing

Sample on trailing edge of clock, shift serial data on leading edge

End of enumeration elements list.

CPOL : Serial clock (SCK) polarity
bits : 2 - 1 (0 bit)

Enumeration:

0 : ActiveHigh

Active high

1 : ActiveLow

Active low

End of enumeration elements list.


CSNPOL

Polarity of CSN output
address_offset : 0x568 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSNPOL CSNPOL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSNPOL

CSNPOL : Polarity of CSN output
bits : 0 - -1 (0 bit)

Enumeration:

0 : LOW

Active low (idle state high)

1 : HIGH

Active high (idle state low)

End of enumeration elements list.


PSELDCX

Pin select for DCX signal
address_offset : 0x56C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSELDCX PSELDCX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN PORT CONNECT

PIN : Pin number
bits : 0 - 3 (4 bit)

PORT : Port number
bits : 5 - 4 (0 bit)

CONNECT : Connection
bits : 31 - 30 (0 bit)

Enumeration:

1 : Disconnected

Disconnect

0 : Connected

Connect

End of enumeration elements list.


DCXCNT

DCX configuration
address_offset : 0x570 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCXCNT DCXCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCXCNT

DCXCNT : This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes.
bits : 0 - 2 (3 bit)


ORC

Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT
address_offset : 0x5C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ORC ORC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ORC

ORC : Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT.
bits : 0 - 6 (7 bit)


PSEL - MISO

Unspecified - - Pin select for MISO signal
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSEL - MISO PSEL - MISO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN PORT CONNECT

PIN : Pin number
bits : 0 - 3 (4 bit)

PORT : Port number
bits : 5 - 4 (0 bit)

CONNECT : Connection
bits : 31 - 30 (0 bit)

Enumeration:

1 : Disconnected

Disconnect

0 : Connected

Connect

End of enumeration elements list.


RXD - AMOUNT

RXD EasyDMA channel - - Number of bytes transferred in the last transaction
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXD - AMOUNT RXD - AMOUNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMOUNT

AMOUNT : Number of bytes transferred in the last transaction
bits : 0 - 14 (15 bit)


TXD - AMOUNT

TXD EasyDMA channel - - Number of bytes transferred in the last transaction
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXD - AMOUNT TXD - AMOUNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMOUNT

AMOUNT : Number of bytes transferred in the last transaction
bits : 0 - 14 (15 bit)


SUBSCRIBE_START

Subscribe configuration for task START
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_START SUBSCRIBE_START read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task START will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


SUBSCRIBE_STOP

Subscribe configuration for task STOP
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_STOP SUBSCRIBE_STOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task STOP will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


SUBSCRIBE_SUSPEND

Subscribe configuration for task SUSPEND
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_SUSPEND SUBSCRIBE_SUSPEND read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task SUSPEND will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


SUBSCRIBE_RESUME

Subscribe configuration for task RESUME
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_RESUME SUBSCRIBE_RESUME read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task RESUME will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


PSEL - CSN

Unspecified - - Pin select for CSN
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSEL - CSN PSEL - CSN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN PORT CONNECT

PIN : Pin number
bits : 0 - 3 (4 bit)

PORT : Port number
bits : 5 - 4 (0 bit)

CONNECT : Connection
bits : 31 - 30 (0 bit)

Enumeration:

1 : Disconnected

Disconnect

0 : Connected

Connect

End of enumeration elements list.


RXD - LIST

RXD EasyDMA channel - - EasyDMA list type
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXD - LIST RXD - LIST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIST

LIST : List type
bits : 0 - 0 (1 bit)

Enumeration:

0 : Disabled

Disable EasyDMA list

1 : ArrayList

Use array list

End of enumeration elements list.


TXD - LIST

TXD EasyDMA channel - - EasyDMA list type
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXD - LIST TXD - LIST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIST

LIST : List type
bits : 0 - 0 (1 bit)

Enumeration:

0 : Disabled

Disable EasyDMA list

1 : ArrayList

Use array list

End of enumeration elements list.



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