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GPIOTE

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TASKS_OUT[0]

SUBSCRIBE_OUT[0]

TASKS_SET[3]

TASKS_CLR[1]

CONFIG[2]

TASKS_SET[4]

SUBSCRIBE_SET[0]

EVENTS_PORT

TASKS_OUT[3]

SUBSCRIBE_OUT[1]

TASKS_SET[5]

TASKS_CLR[2]

CONFIG[3]

SUBSCRIBE_CLR[0]

TASKS_SET[6]

CONFIG[4]

TASKS_CLR[3]

PUBLISH_PORT

EVENTS_IN[0]

SUBSCRIBE_OUT[2]

SUBSCRIBE_SET[1]

TASKS_SET[7]

CONFIG[5]

TASKS_CLR[4]

TASKS_OUT[4]

CONFIG[6]

SUBSCRIBE_OUT[3]

SUBSCRIBE_CLR[1]

SUBSCRIBE_SET[2]

TASKS_CLR[5]

CONFIG[7]

PUBLISH_IN[0]

EVENTS_IN[1]

INTENSET

INTENCLR

SUBSCRIBE_OUT[4]

TASKS_CLR[6]

SUBSCRIBE_SET[3]

SUBSCRIBE_CLR[2]

SUBSCRIBE_OUT[5]

TASKS_OUT[5]

TASKS_CLR[7]

TASKS_OUT[1]

EVENTS_IN[2]

SUBSCRIBE_SET[4]

SUBSCRIBE_OUT[6]

SUBSCRIBE_CLR[3]

PUBLISH_IN[1]

SUBSCRIBE_OUT[7]

LATENCY

SUBSCRIBE_SET[5]

EVENTS_IN[3]

TASKS_OUT[6]

SUBSCRIBE_CLR[4]

SUBSCRIBE_SET[6]

TASKS_SET[0]

PUBLISH_IN[2]

EVENTS_IN[4]

SUBSCRIBE_CLR[5]

SUBSCRIBE_SET[7]

TASKS_OUT[7]

EVENTS_IN[5]

SUBSCRIBE_CLR[6]

PUBLISH_IN[3]

SUBSCRIBE_CLR[7]

EVENTS_IN[6]

PUBLISH_IN[4]

TASKS_SET[1]

EVENTS_IN[7]

CONFIG[0]

PUBLISH_IN[5]

TASKS_OUT[2]

TASKS_CLR[0]

PUBLISH_IN[6]

TASKS_SET[2]

PUBLISH_IN[7]

CONFIG[1]


TASKS_OUT[0]

Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.
address_offset : 0x0 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_OUT[0] TASKS_OUT[0] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_OUT

TASKS_OUT : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


SUBSCRIBE_OUT[0]

Description collection: Subscribe configuration for task OUT[n]
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_OUT[0] SUBSCRIBE_OUT[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task OUT[n] will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


TASKS_SET[3]

Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.
address_offset : 0x108 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_SET[3] TASKS_SET[3] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_SET

TASKS_SET : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


TASKS_CLR[1]

Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.
address_offset : 0x124 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_CLR[1] TASKS_CLR[1] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_CLR

TASKS_CLR : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


CONFIG[2]

Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event
address_offset : 0x144C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONFIG[2] CONFIG[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE PSEL PORT POLARITY OUTINIT

MODE : Mode
bits : 0 - 0 (1 bit)

Enumeration:

0 : Disabled

Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.

1 : Event

Event mode

3 : Task

Task mode

End of enumeration elements list.

PSEL : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event
bits : 8 - 11 (4 bit)

PORT : Port number
bits : 13 - 12 (0 bit)

POLARITY : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.
bits : 16 - 16 (1 bit)

Enumeration:

0 : None

Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity.

1 : LoToHi

Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin.

2 : HiToLo

Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin.

3 : Toggle

Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.

End of enumeration elements list.

OUTINIT : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.
bits : 20 - 19 (0 bit)

Enumeration:

0 : Low

Task mode: Initial value of pin before task triggering is low

1 : High

Task mode: Initial value of pin before task triggering is high

End of enumeration elements list.


TASKS_SET[4]

Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.
address_offset : 0x148 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_SET[4] TASKS_SET[4] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_SET

TASKS_SET : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


SUBSCRIBE_SET[0]

Description collection: Subscribe configuration for task SET[n]
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_SET[0] SUBSCRIBE_SET[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task SET[n] will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


EVENTS_PORT

Event generated from multiple input GPIO pins with SENSE mechanism enabled
address_offset : 0x17C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_PORT EVENTS_PORT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_PORT

EVENTS_PORT : Event generated from multiple input GPIO pins with SENSE mechanism enabled
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


TASKS_OUT[3]

Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.
address_offset : 0x18 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_OUT[3] TASKS_OUT[3] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_OUT

TASKS_OUT : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


SUBSCRIBE_OUT[1]

Description collection: Subscribe configuration for task OUT[n]
address_offset : 0x184 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_OUT[1] SUBSCRIBE_OUT[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task OUT[n] will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


TASKS_SET[5]

Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.
address_offset : 0x18C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_SET[5] TASKS_SET[5] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_SET

TASKS_SET : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


TASKS_CLR[2]

Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.
address_offset : 0x18C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_CLR[2] TASKS_CLR[2] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_CLR

TASKS_CLR : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


CONFIG[3]

Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event
address_offset : 0x1968 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONFIG[3] CONFIG[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE PSEL PORT POLARITY OUTINIT

MODE : Mode
bits : 0 - 0 (1 bit)

Enumeration:

0 : Disabled

Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.

1 : Event

Event mode

3 : Task

Task mode

End of enumeration elements list.

PSEL : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event
bits : 8 - 11 (4 bit)

PORT : Port number
bits : 13 - 12 (0 bit)

POLARITY : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.
bits : 16 - 16 (1 bit)

Enumeration:

0 : None

Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity.

1 : LoToHi

Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin.

2 : HiToLo

Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin.

3 : Toggle

Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.

End of enumeration elements list.

OUTINIT : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.
bits : 20 - 19 (0 bit)

Enumeration:

0 : Low

Task mode: Initial value of pin before task triggering is low

1 : High

Task mode: Initial value of pin before task triggering is high

End of enumeration elements list.


SUBSCRIBE_CLR[0]

Description collection: Subscribe configuration for task CLR[n]
address_offset : 0x1C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_CLR[0] SUBSCRIBE_CLR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task CLR[n] will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


TASKS_SET[6]

Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.
address_offset : 0x1D4 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_SET[6] TASKS_SET[6] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_SET

TASKS_SET : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


CONFIG[4]

Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event
address_offset : 0x1E88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONFIG[4] CONFIG[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE PSEL PORT POLARITY OUTINIT

MODE : Mode
bits : 0 - 0 (1 bit)

Enumeration:

0 : Disabled

Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.

1 : Event

Event mode

3 : Task

Task mode

End of enumeration elements list.

PSEL : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event
bits : 8 - 11 (4 bit)

PORT : Port number
bits : 13 - 12 (0 bit)

POLARITY : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.
bits : 16 - 16 (1 bit)

Enumeration:

0 : None

Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity.

1 : LoToHi

Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin.

2 : HiToLo

Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin.

3 : Toggle

Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.

End of enumeration elements list.

OUTINIT : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.
bits : 20 - 19 (0 bit)

Enumeration:

0 : Low

Task mode: Initial value of pin before task triggering is low

1 : High

Task mode: Initial value of pin before task triggering is high

End of enumeration elements list.


TASKS_CLR[3]

Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.
address_offset : 0x1F8 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_CLR[3] TASKS_CLR[3] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_CLR

TASKS_CLR : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


PUBLISH_PORT

Publish configuration for event PORT
address_offset : 0x1FC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUBLISH_PORT PUBLISH_PORT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that event PORT will publish to.
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable publishing

1 : Enabled

Enable publishing

End of enumeration elements list.


EVENTS_IN[0]

Description collection: Event generated from pin specified in CONFIG[n].PSEL
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_IN[0] EVENTS_IN[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_IN

EVENTS_IN : Event generated from pin specified in CONFIG[n].PSEL
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


SUBSCRIBE_OUT[2]

Description collection: Subscribe configuration for task OUT[n]
address_offset : 0x20C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_OUT[2] SUBSCRIBE_OUT[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task OUT[n] will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


SUBSCRIBE_SET[1]

Description collection: Subscribe configuration for task SET[n]
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_SET[1] SUBSCRIBE_SET[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task SET[n] will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


TASKS_SET[7]

Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.
address_offset : 0x220 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_SET[7] TASKS_SET[7] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_SET

TASKS_SET : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


CONFIG[5]

Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event
address_offset : 0x23AC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONFIG[5] CONFIG[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE PSEL PORT POLARITY OUTINIT

MODE : Mode
bits : 0 - 0 (1 bit)

Enumeration:

0 : Disabled

Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.

1 : Event

Event mode

3 : Task

Task mode

End of enumeration elements list.

PSEL : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event
bits : 8 - 11 (4 bit)

PORT : Port number
bits : 13 - 12 (0 bit)

POLARITY : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.
bits : 16 - 16 (1 bit)

Enumeration:

0 : None

Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity.

1 : LoToHi

Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin.

2 : HiToLo

Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin.

3 : Toggle

Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.

End of enumeration elements list.

OUTINIT : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.
bits : 20 - 19 (0 bit)

Enumeration:

0 : Low

Task mode: Initial value of pin before task triggering is low

1 : High

Task mode: Initial value of pin before task triggering is high

End of enumeration elements list.


TASKS_CLR[4]

Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.
address_offset : 0x268 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_CLR[4] TASKS_CLR[4] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_CLR

TASKS_CLR : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


TASKS_OUT[4]

Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.
address_offset : 0x28 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_OUT[4] TASKS_OUT[4] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_OUT

TASKS_OUT : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


CONFIG[6]

Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event
address_offset : 0x28D4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONFIG[6] CONFIG[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE PSEL PORT POLARITY OUTINIT

MODE : Mode
bits : 0 - 0 (1 bit)

Enumeration:

0 : Disabled

Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.

1 : Event

Event mode

3 : Task

Task mode

End of enumeration elements list.

PSEL : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event
bits : 8 - 11 (4 bit)

PORT : Port number
bits : 13 - 12 (0 bit)

POLARITY : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.
bits : 16 - 16 (1 bit)

Enumeration:

0 : None

Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity.

1 : LoToHi

Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin.

2 : HiToLo

Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin.

3 : Toggle

Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.

End of enumeration elements list.

OUTINIT : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.
bits : 20 - 19 (0 bit)

Enumeration:

0 : Low

Task mode: Initial value of pin before task triggering is low

1 : High

Task mode: Initial value of pin before task triggering is high

End of enumeration elements list.


SUBSCRIBE_OUT[3]

Description collection: Subscribe configuration for task OUT[n]
address_offset : 0x298 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_OUT[3] SUBSCRIBE_OUT[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task OUT[n] will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


SUBSCRIBE_CLR[1]

Description collection: Subscribe configuration for task CLR[n]
address_offset : 0x2A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_CLR[1] SUBSCRIBE_CLR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task CLR[n] will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


SUBSCRIBE_SET[2]

Description collection: Subscribe configuration for task SET[n]
address_offset : 0x2CC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_SET[2] SUBSCRIBE_SET[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task SET[n] will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


TASKS_CLR[5]

Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.
address_offset : 0x2DC Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_CLR[5] TASKS_CLR[5] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_CLR

TASKS_CLR : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


CONFIG[7]

Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event
address_offset : 0x2E00 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONFIG[7] CONFIG[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE PSEL PORT POLARITY OUTINIT

MODE : Mode
bits : 0 - 0 (1 bit)

Enumeration:

0 : Disabled

Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.

1 : Event

Event mode

3 : Task

Task mode

End of enumeration elements list.

PSEL : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event
bits : 8 - 11 (4 bit)

PORT : Port number
bits : 13 - 12 (0 bit)

POLARITY : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.
bits : 16 - 16 (1 bit)

Enumeration:

0 : None

Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity.

1 : LoToHi

Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin.

2 : HiToLo

Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin.

3 : Toggle

Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.

End of enumeration elements list.

OUTINIT : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.
bits : 20 - 19 (0 bit)

Enumeration:

0 : Low

Task mode: Initial value of pin before task triggering is low

1 : High

Task mode: Initial value of pin before task triggering is high

End of enumeration elements list.


PUBLISH_IN[0]

Description collection: Publish configuration for event IN[n]
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUBLISH_IN[0] PUBLISH_IN[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that event IN[n] will publish to.
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable publishing

1 : Enabled

Enable publishing

End of enumeration elements list.


EVENTS_IN[1]

Description collection: Event generated from pin specified in CONFIG[n].PSEL
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_IN[1] EVENTS_IN[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_IN

EVENTS_IN : Event generated from pin specified in CONFIG[n].PSEL
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


INTENSET

Enable interrupt
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 PORT

IN0 : Write '1' to enable interrupt for event IN[0]
bits : 0 - -1 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

IN1 : Write '1' to enable interrupt for event IN[1]
bits : 1 - 0 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

IN2 : Write '1' to enable interrupt for event IN[2]
bits : 2 - 1 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

IN3 : Write '1' to enable interrupt for event IN[3]
bits : 3 - 2 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

IN4 : Write '1' to enable interrupt for event IN[4]
bits : 4 - 3 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

IN5 : Write '1' to enable interrupt for event IN[5]
bits : 5 - 4 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

IN6 : Write '1' to enable interrupt for event IN[6]
bits : 6 - 5 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

IN7 : Write '1' to enable interrupt for event IN[7]
bits : 7 - 6 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

PORT : Write '1' to enable interrupt for event PORT
bits : 31 - 30 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.


INTENCLR

Disable interrupt
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 PORT

IN0 : Write '1' to disable interrupt for event IN[0]
bits : 0 - -1 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

IN1 : Write '1' to disable interrupt for event IN[1]
bits : 1 - 0 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

IN2 : Write '1' to disable interrupt for event IN[2]
bits : 2 - 1 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

IN3 : Write '1' to disable interrupt for event IN[3]
bits : 3 - 2 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

IN4 : Write '1' to disable interrupt for event IN[4]
bits : 4 - 3 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

IN5 : Write '1' to disable interrupt for event IN[5]
bits : 5 - 4 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

IN6 : Write '1' to disable interrupt for event IN[6]
bits : 6 - 5 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

IN7 : Write '1' to disable interrupt for event IN[7]
bits : 7 - 6 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

PORT : Write '1' to disable interrupt for event PORT
bits : 31 - 30 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.


SUBSCRIBE_OUT[4]

Description collection: Subscribe configuration for task OUT[n]
address_offset : 0x328 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_OUT[4] SUBSCRIBE_OUT[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task OUT[n] will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


TASKS_CLR[6]

Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.
address_offset : 0x354 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_CLR[6] TASKS_CLR[6] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_CLR

TASKS_CLR : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


SUBSCRIBE_SET[3]

Description collection: Subscribe configuration for task SET[n]
address_offset : 0x388 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_SET[3] SUBSCRIBE_SET[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task SET[n] will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


SUBSCRIBE_CLR[2]

Description collection: Subscribe configuration for task CLR[n]
address_offset : 0x38C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_CLR[2] SUBSCRIBE_CLR[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task CLR[n] will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


SUBSCRIBE_OUT[5]

Description collection: Subscribe configuration for task OUT[n]
address_offset : 0x3BC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_OUT[5] SUBSCRIBE_OUT[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task OUT[n] will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


TASKS_OUT[5]

Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.
address_offset : 0x3C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_OUT[5] TASKS_OUT[5] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_OUT

TASKS_OUT : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


TASKS_CLR[7]

Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.
address_offset : 0x3D0 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_CLR[7] TASKS_CLR[7] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_CLR

TASKS_CLR : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


TASKS_OUT[1]

Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.
address_offset : 0x4 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_OUT[1] TASKS_OUT[1] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_OUT

TASKS_OUT : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


EVENTS_IN[2]

Description collection: Event generated from pin specified in CONFIG[n].PSEL
address_offset : 0x40C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_IN[2] EVENTS_IN[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_IN

EVENTS_IN : Event generated from pin specified in CONFIG[n].PSEL
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


SUBSCRIBE_SET[4]

Description collection: Subscribe configuration for task SET[n]
address_offset : 0x448 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_SET[4] SUBSCRIBE_SET[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task SET[n] will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


SUBSCRIBE_OUT[6]

Description collection: Subscribe configuration for task OUT[n]
address_offset : 0x454 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_OUT[6] SUBSCRIBE_OUT[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task OUT[n] will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


SUBSCRIBE_CLR[3]

Description collection: Subscribe configuration for task CLR[n]
address_offset : 0x478 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_CLR[3] SUBSCRIBE_CLR[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task CLR[n] will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


PUBLISH_IN[1]

Description collection: Publish configuration for event IN[n]
address_offset : 0x484 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUBLISH_IN[1] PUBLISH_IN[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that event IN[n] will publish to.
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable publishing

1 : Enabled

Enable publishing

End of enumeration elements list.


SUBSCRIBE_OUT[7]

Description collection: Subscribe configuration for task OUT[n]
address_offset : 0x4F0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_OUT[7] SUBSCRIBE_OUT[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task OUT[n] will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


LATENCY

Latency selection for Event mode (MODE=Event) with rising or falling edge detection on the pin.
address_offset : 0x504 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LATENCY LATENCY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LATENCY

LATENCY : Latency setting
bits : 0 - -1 (0 bit)

Enumeration:

0 : LowPower

Low power setting, for signals with minimum hold time tGPIOTE,HOLD,LP; refer to Electrical specification section

1 : LowLatency

Low latency setting, for signals with minimum hold time tGPIOTE,HOLD,LL; refer to Electrical specification section

End of enumeration elements list.


SUBSCRIBE_SET[5]

Description collection: Subscribe configuration for task SET[n]
address_offset : 0x50C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_SET[5] SUBSCRIBE_SET[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task SET[n] will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


EVENTS_IN[3]

Description collection: Event generated from pin specified in CONFIG[n].PSEL
address_offset : 0x518 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_IN[3] EVENTS_IN[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_IN

EVENTS_IN : Event generated from pin specified in CONFIG[n].PSEL
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


TASKS_OUT[6]

Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.
address_offset : 0x54 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_OUT[6] TASKS_OUT[6] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_OUT

TASKS_OUT : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


SUBSCRIBE_CLR[4]

Description collection: Subscribe configuration for task CLR[n]
address_offset : 0x568 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_CLR[4] SUBSCRIBE_CLR[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task CLR[n] will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


SUBSCRIBE_SET[6]

Description collection: Subscribe configuration for task SET[n]
address_offset : 0x5D4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_SET[6] SUBSCRIBE_SET[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task SET[n] will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


TASKS_SET[0]

Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.
address_offset : 0x60 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_SET[0] TASKS_SET[0] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_SET

TASKS_SET : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


PUBLISH_IN[2]

Description collection: Publish configuration for event IN[n]
address_offset : 0x60C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUBLISH_IN[2] PUBLISH_IN[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that event IN[n] will publish to.
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable publishing

1 : Enabled

Enable publishing

End of enumeration elements list.


EVENTS_IN[4]

Description collection: Event generated from pin specified in CONFIG[n].PSEL
address_offset : 0x628 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_IN[4] EVENTS_IN[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_IN

EVENTS_IN : Event generated from pin specified in CONFIG[n].PSEL
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


SUBSCRIBE_CLR[5]

Description collection: Subscribe configuration for task CLR[n]
address_offset : 0x65C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_CLR[5] SUBSCRIBE_CLR[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task CLR[n] will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


SUBSCRIBE_SET[7]

Description collection: Subscribe configuration for task SET[n]
address_offset : 0x6A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_SET[7] SUBSCRIBE_SET[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task SET[n] will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


TASKS_OUT[7]

Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.
address_offset : 0x70 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_OUT[7] TASKS_OUT[7] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_OUT

TASKS_OUT : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


EVENTS_IN[5]

Description collection: Event generated from pin specified in CONFIG[n].PSEL
address_offset : 0x73C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_IN[5] EVENTS_IN[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_IN

EVENTS_IN : Event generated from pin specified in CONFIG[n].PSEL
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


SUBSCRIBE_CLR[6]

Description collection: Subscribe configuration for task CLR[n]
address_offset : 0x754 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_CLR[6] SUBSCRIBE_CLR[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task CLR[n] will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


PUBLISH_IN[3]

Description collection: Publish configuration for event IN[n]
address_offset : 0x798 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUBLISH_IN[3] PUBLISH_IN[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that event IN[n] will publish to.
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable publishing

1 : Enabled

Enable publishing

End of enumeration elements list.


SUBSCRIBE_CLR[7]

Description collection: Subscribe configuration for task CLR[n]
address_offset : 0x850 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_CLR[7] SUBSCRIBE_CLR[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task CLR[n] will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


EVENTS_IN[6]

Description collection: Event generated from pin specified in CONFIG[n].PSEL
address_offset : 0x854 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_IN[6] EVENTS_IN[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_IN

EVENTS_IN : Event generated from pin specified in CONFIG[n].PSEL
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


PUBLISH_IN[4]

Description collection: Publish configuration for event IN[n]
address_offset : 0x928 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUBLISH_IN[4] PUBLISH_IN[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that event IN[n] will publish to.
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable publishing

1 : Enabled

Enable publishing

End of enumeration elements list.


TASKS_SET[1]

Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.
address_offset : 0x94 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_SET[1] TASKS_SET[1] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_SET

TASKS_SET : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


EVENTS_IN[7]

Description collection: Event generated from pin specified in CONFIG[n].PSEL
address_offset : 0x970 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_IN[7] EVENTS_IN[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_IN

EVENTS_IN : Event generated from pin specified in CONFIG[n].PSEL
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


CONFIG[0]

Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event
address_offset : 0xA20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONFIG[0] CONFIG[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE PSEL PORT POLARITY OUTINIT

MODE : Mode
bits : 0 - 0 (1 bit)

Enumeration:

0 : Disabled

Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.

1 : Event

Event mode

3 : Task

Task mode

End of enumeration elements list.

PSEL : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event
bits : 8 - 11 (4 bit)

PORT : Port number
bits : 13 - 12 (0 bit)

POLARITY : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.
bits : 16 - 16 (1 bit)

Enumeration:

0 : None

Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity.

1 : LoToHi

Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin.

2 : HiToLo

Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin.

3 : Toggle

Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.

End of enumeration elements list.

OUTINIT : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.
bits : 20 - 19 (0 bit)

Enumeration:

0 : Low

Task mode: Initial value of pin before task triggering is low

1 : High

Task mode: Initial value of pin before task triggering is high

End of enumeration elements list.


PUBLISH_IN[5]

Description collection: Publish configuration for event IN[n]
address_offset : 0xABC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUBLISH_IN[5] PUBLISH_IN[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that event IN[n] will publish to.
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable publishing

1 : Enabled

Enable publishing

End of enumeration elements list.


TASKS_OUT[2]

Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.
address_offset : 0xC Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_OUT[2] TASKS_OUT[2] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_OUT

TASKS_OUT : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


TASKS_CLR[0]

Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.
address_offset : 0xC0 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_CLR[0] TASKS_CLR[0] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_CLR

TASKS_CLR : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


PUBLISH_IN[6]

Description collection: Publish configuration for event IN[n]
address_offset : 0xC54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUBLISH_IN[6] PUBLISH_IN[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that event IN[n] will publish to.
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable publishing

1 : Enabled

Enable publishing

End of enumeration elements list.


TASKS_SET[2]

Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.
address_offset : 0xCC Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_SET[2] TASKS_SET[2] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_SET

TASKS_SET : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


PUBLISH_IN[7]

Description collection: Publish configuration for event IN[n]
address_offset : 0xDF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUBLISH_IN[7] PUBLISH_IN[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that event IN[n] will publish to.
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable publishing

1 : Enabled

Enable publishing

End of enumeration elements list.


CONFIG[1]

Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event
address_offset : 0xF34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONFIG[1] CONFIG[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE PSEL PORT POLARITY OUTINIT

MODE : Mode
bits : 0 - 0 (1 bit)

Enumeration:

0 : Disabled

Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.

1 : Event

Event mode

3 : Task

Task mode

End of enumeration elements list.

PSEL : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event
bits : 8 - 11 (4 bit)

PORT : Port number
bits : 13 - 12 (0 bit)

POLARITY : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.
bits : 16 - 16 (1 bit)

Enumeration:

0 : None

Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity.

1 : LoToHi

Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin.

2 : HiToLo

Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin.

3 : Toggle

Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.

End of enumeration elements list.

OUTINIT : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.
bits : 20 - 19 (0 bit)

Enumeration:

0 : Low

Task mode: Initial value of pin before task triggering is low

1 : High

Task mode: Initial value of pin before task triggering is high

End of enumeration elements list.



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