\n

RTC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TASKS_START

EVENTS_TICK

EVENTS_OVRFLW

TASKS_CAPTURE[2]

CC[2]

TASKS_CAPTURE[3]

SUBSCRIBE_CAPTURE[0]

PUBLISH_TICK

PUBLISH_OVRFLW

CC[3]

SHORTS

SUBSCRIBE_CAPTURE[1]

EVENTS_COMPARE[0]

INTENSET

INTENCLR

SUBSCRIBE_CAPTURE[2]

EVTEN

EVTENSET

EVTENCLR

PUBLISH_COMPARE[0]

EVENTS_COMPARE[1]

SUBSCRIBE_CAPTURE[3]

TASKS_STOP

COUNTER

PRESCALER

EVENTS_COMPARE[2]

PUBLISH_COMPARE[1]

EVENTS_COMPARE[3]

PUBLISH_COMPARE[2]

TASKS_CLEAR

TASKS_CAPTURE[0]

SUBSCRIBE_START

SUBSCRIBE_STOP

SUBSCRIBE_CLEAR

SUBSCRIBE_TRIGOVRFLW

PUBLISH_COMPARE[3]

CC[0]

TASKS_TRIGOVRFLW

TASKS_CAPTURE[1]

CC[1]


TASKS_START

Start RTC counter
address_offset : 0x0 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_START TASKS_START write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_START

TASKS_START : Start RTC counter
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


EVENTS_TICK

Event on counter increment
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_TICK EVENTS_TICK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_TICK

EVENTS_TICK : Event on counter increment
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


EVENTS_OVRFLW

Event on counter overflow
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_OVRFLW EVENTS_OVRFLW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_OVRFLW

EVENTS_OVRFLW : Event on counter overflow
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


TASKS_CAPTURE[2]

Description collection: Capture RTC counter to CC[n] register
address_offset : 0x10C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_CAPTURE[2] TASKS_CAPTURE[2] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_CAPTURE

TASKS_CAPTURE : Capture RTC counter to CC[n] register
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


CC[2]

Description collection: Compare register n
address_offset : 0x150C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC[2] CC[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPARE

COMPARE : Compare value
bits : 0 - 22 (23 bit)


TASKS_CAPTURE[3]

Description collection: Capture RTC counter to CC[n] register
address_offset : 0x158 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_CAPTURE[3] TASKS_CAPTURE[3] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_CAPTURE

TASKS_CAPTURE : Capture RTC counter to CC[n] register
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


SUBSCRIBE_CAPTURE[0]

Description collection: Subscribe configuration for task CAPTURE[n]
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_CAPTURE[0] SUBSCRIBE_CAPTURE[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task CAPTURE[n] will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


PUBLISH_TICK

Publish configuration for event TICK
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUBLISH_TICK PUBLISH_TICK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that event TICK will publish to.
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable publishing

1 : Enabled

Enable publishing

End of enumeration elements list.


PUBLISH_OVRFLW

Publish configuration for event OVRFLW
address_offset : 0x184 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUBLISH_OVRFLW PUBLISH_OVRFLW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that event OVRFLW will publish to.
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable publishing

1 : Enabled

Enable publishing

End of enumeration elements list.


CC[3]

Description collection: Compare register n
address_offset : 0x1A58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC[3] CC[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPARE

COMPARE : Compare value
bits : 0 - 22 (23 bit)


SHORTS

Shortcuts between local events and tasks
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHORTS SHORTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPARE0_CLEAR COMPARE1_CLEAR COMPARE2_CLEAR COMPARE3_CLEAR

COMPARE0_CLEAR : Shortcut between event COMPARE[0] and task CLEAR
bits : 0 - -1 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.

COMPARE1_CLEAR : Shortcut between event COMPARE[1] and task CLEAR
bits : 1 - 0 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.

COMPARE2_CLEAR : Shortcut between event COMPARE[2] and task CLEAR
bits : 2 - 1 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.

COMPARE3_CLEAR : Shortcut between event COMPARE[3] and task CLEAR
bits : 3 - 2 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.


SUBSCRIBE_CAPTURE[1]

Description collection: Subscribe configuration for task CAPTURE[n]
address_offset : 0x244 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_CAPTURE[1] SUBSCRIBE_CAPTURE[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task CAPTURE[n] will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


EVENTS_COMPARE[0]

Description collection: Compare event on CC[n] match
address_offset : 0x280 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_COMPARE[0] EVENTS_COMPARE[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_COMPARE

EVENTS_COMPARE : Compare event on CC[n] match
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


INTENSET

Enable interrupt
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TICK OVRFLW COMPARE0 COMPARE1 COMPARE2 COMPARE3

TICK : Write '1' to enable interrupt for event TICK
bits : 0 - -1 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

OVRFLW : Write '1' to enable interrupt for event OVRFLW
bits : 1 - 0 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

COMPARE0 : Write '1' to enable interrupt for event COMPARE[0]
bits : 16 - 15 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

COMPARE1 : Write '1' to enable interrupt for event COMPARE[1]
bits : 17 - 16 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

COMPARE2 : Write '1' to enable interrupt for event COMPARE[2]
bits : 18 - 17 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

COMPARE3 : Write '1' to enable interrupt for event COMPARE[3]
bits : 19 - 18 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.


INTENCLR

Disable interrupt
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TICK OVRFLW COMPARE0 COMPARE1 COMPARE2 COMPARE3

TICK : Write '1' to disable interrupt for event TICK
bits : 0 - -1 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

OVRFLW : Write '1' to disable interrupt for event OVRFLW
bits : 1 - 0 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

COMPARE0 : Write '1' to disable interrupt for event COMPARE[0]
bits : 16 - 15 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

COMPARE1 : Write '1' to disable interrupt for event COMPARE[1]
bits : 17 - 16 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

COMPARE2 : Write '1' to disable interrupt for event COMPARE[2]
bits : 18 - 17 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

COMPARE3 : Write '1' to disable interrupt for event COMPARE[3]
bits : 19 - 18 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.


SUBSCRIBE_CAPTURE[2]

Description collection: Subscribe configuration for task CAPTURE[n]
address_offset : 0x30C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_CAPTURE[2] SUBSCRIBE_CAPTURE[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task CAPTURE[n] will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


EVTEN

Enable or disable event routing
address_offset : 0x340 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVTEN EVTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TICK OVRFLW COMPARE0 COMPARE1 COMPARE2 COMPARE3

TICK : Enable or disable event routing for event TICK
bits : 0 - -1 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

OVRFLW : Enable or disable event routing for event OVRFLW
bits : 1 - 0 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

COMPARE0 : Enable or disable event routing for event COMPARE[0]
bits : 16 - 15 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

COMPARE1 : Enable or disable event routing for event COMPARE[1]
bits : 17 - 16 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

COMPARE2 : Enable or disable event routing for event COMPARE[2]
bits : 18 - 17 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

COMPARE3 : Enable or disable event routing for event COMPARE[3]
bits : 19 - 18 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.


EVTENSET

Enable event routing
address_offset : 0x344 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVTENSET EVTENSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TICK OVRFLW COMPARE0 COMPARE1 COMPARE2 COMPARE3

TICK : Write '1' to enable event routing for event TICK
bits : 0 - -1 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

OVRFLW : Write '1' to enable event routing for event OVRFLW
bits : 1 - 0 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

COMPARE0 : Write '1' to enable event routing for event COMPARE[0]
bits : 16 - 15 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

COMPARE1 : Write '1' to enable event routing for event COMPARE[1]
bits : 17 - 16 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

COMPARE2 : Write '1' to enable event routing for event COMPARE[2]
bits : 18 - 17 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

COMPARE3 : Write '1' to enable event routing for event COMPARE[3]
bits : 19 - 18 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.


EVTENCLR

Disable event routing
address_offset : 0x348 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVTENCLR EVTENCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TICK OVRFLW COMPARE0 COMPARE1 COMPARE2 COMPARE3

TICK : Write '1' to disable event routing for event TICK
bits : 0 - -1 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

OVRFLW : Write '1' to disable event routing for event OVRFLW
bits : 1 - 0 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

COMPARE0 : Write '1' to disable event routing for event COMPARE[0]
bits : 16 - 15 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

COMPARE1 : Write '1' to disable event routing for event COMPARE[1]
bits : 17 - 16 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

COMPARE2 : Write '1' to disable event routing for event COMPARE[2]
bits : 18 - 17 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

COMPARE3 : Write '1' to disable event routing for event COMPARE[3]
bits : 19 - 18 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.


PUBLISH_COMPARE[0]

Description collection: Publish configuration for event COMPARE[n]
address_offset : 0x380 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUBLISH_COMPARE[0] PUBLISH_COMPARE[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that event COMPARE[n] will publish to.
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable publishing

1 : Enabled

Enable publishing

End of enumeration elements list.


EVENTS_COMPARE[1]

Description collection: Compare event on CC[n] match
address_offset : 0x3C4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_COMPARE[1] EVENTS_COMPARE[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_COMPARE

EVENTS_COMPARE : Compare event on CC[n] match
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


SUBSCRIBE_CAPTURE[3]

Description collection: Subscribe configuration for task CAPTURE[n]
address_offset : 0x3D8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_CAPTURE[3] SUBSCRIBE_CAPTURE[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task CAPTURE[n] will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


TASKS_STOP

Stop RTC counter
address_offset : 0x4 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_STOP TASKS_STOP write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_STOP

TASKS_STOP : Stop RTC counter
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


COUNTER

Current counter value
address_offset : 0x504 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

COUNTER COUNTER read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNTER

COUNTER : Counter value
bits : 0 - 22 (23 bit)


PRESCALER

12-bit prescaler for counter frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped.
address_offset : 0x508 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRESCALER PRESCALER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRESCALER

PRESCALER : Prescaler value
bits : 0 - 10 (11 bit)


EVENTS_COMPARE[2]

Description collection: Compare event on CC[n] match
address_offset : 0x50C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_COMPARE[2] EVENTS_COMPARE[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_COMPARE

EVENTS_COMPARE : Compare event on CC[n] match
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


PUBLISH_COMPARE[1]

Description collection: Publish configuration for event COMPARE[n]
address_offset : 0x544 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUBLISH_COMPARE[1] PUBLISH_COMPARE[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that event COMPARE[n] will publish to.
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable publishing

1 : Enabled

Enable publishing

End of enumeration elements list.


EVENTS_COMPARE[3]

Description collection: Compare event on CC[n] match
address_offset : 0x658 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_COMPARE[3] EVENTS_COMPARE[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_COMPARE

EVENTS_COMPARE : Compare event on CC[n] match
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


PUBLISH_COMPARE[2]

Description collection: Publish configuration for event COMPARE[n]
address_offset : 0x70C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUBLISH_COMPARE[2] PUBLISH_COMPARE[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that event COMPARE[n] will publish to.
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable publishing

1 : Enabled

Enable publishing

End of enumeration elements list.


TASKS_CLEAR

Clear RTC counter
address_offset : 0x8 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_CLEAR TASKS_CLEAR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_CLEAR

TASKS_CLEAR : Clear RTC counter
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


TASKS_CAPTURE[0]

Description collection: Capture RTC counter to CC[n] register
address_offset : 0x80 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_CAPTURE[0] TASKS_CAPTURE[0] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_CAPTURE

TASKS_CAPTURE : Capture RTC counter to CC[n] register
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


SUBSCRIBE_START

Subscribe configuration for task START
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_START SUBSCRIBE_START read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task START will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


SUBSCRIBE_STOP

Subscribe configuration for task STOP
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_STOP SUBSCRIBE_STOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task STOP will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


SUBSCRIBE_CLEAR

Subscribe configuration for task CLEAR
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_CLEAR SUBSCRIBE_CLEAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task CLEAR will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


SUBSCRIBE_TRIGOVRFLW

Subscribe configuration for task TRIGOVRFLW
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_TRIGOVRFLW SUBSCRIBE_TRIGOVRFLW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task TRIGOVRFLW will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


PUBLISH_COMPARE[3]

Description collection: Publish configuration for event COMPARE[n]
address_offset : 0x8D8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUBLISH_COMPARE[3] PUBLISH_COMPARE[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that event COMPARE[n] will publish to.
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable publishing

1 : Enabled

Enable publishing

End of enumeration elements list.


CC[0]

Description collection: Compare register n
address_offset : 0xA80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC[0] CC[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPARE

COMPARE : Compare value
bits : 0 - 22 (23 bit)


TASKS_TRIGOVRFLW

Set counter to 0xFFFFF0
address_offset : 0xC Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_TRIGOVRFLW TASKS_TRIGOVRFLW write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_TRIGOVRFLW

TASKS_TRIGOVRFLW : Set counter to 0xFFFFF0
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


TASKS_CAPTURE[1]

Description collection: Capture RTC counter to CC[n] register
address_offset : 0xC4 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_CAPTURE[1] TASKS_CAPTURE[1] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_CAPTURE

TASKS_CAPTURE : Capture RTC counter to CC[n] register
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


CC[1]

Description collection: Compare register n
address_offset : 0xFC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC[1] CC[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPARE

COMPARE : Compare value
bits : 0 - 22 (23 bit)



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