\n

COMP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TASKS_START

EVENTS_READY

EVENTS_DOWN

EVENTS_UP

EVENTS_CROSS

PUBLISH_READY

PUBLISH_DOWN

PUBLISH_UP

PUBLISH_CROSS

SHORTS

INTEN

INTENSET

INTENCLR

TASKS_STOP

RESULT

ENABLE

PSEL

REFSEL

EXTREFSEL

TH

MODE

HYST

ISOURCE

TASKS_SAMPLE

SUBSCRIBE_START

SUBSCRIBE_STOP

SUBSCRIBE_SAMPLE


TASKS_START

Start comparator
address_offset : 0x0 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_START TASKS_START write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_START

TASKS_START : Start comparator
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


EVENTS_READY

COMP is ready and output is valid
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_READY EVENTS_READY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_READY

EVENTS_READY : COMP is ready and output is valid
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


EVENTS_DOWN

Downward crossing
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_DOWN EVENTS_DOWN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_DOWN

EVENTS_DOWN : Downward crossing
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


EVENTS_UP

Upward crossing
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_UP EVENTS_UP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_UP

EVENTS_UP : Upward crossing
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


EVENTS_CROSS

Downward or upward crossing
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTS_CROSS EVENTS_CROSS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVENTS_CROSS

EVENTS_CROSS : Downward or upward crossing
bits : 0 - -1 (0 bit)

Enumeration:

0 : NotGenerated

Event not generated

1 : Generated

Event generated

End of enumeration elements list.


PUBLISH_READY

Publish configuration for event READY
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUBLISH_READY PUBLISH_READY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that event READY will publish to.
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable publishing

1 : Enabled

Enable publishing

End of enumeration elements list.


PUBLISH_DOWN

Publish configuration for event DOWN
address_offset : 0x184 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUBLISH_DOWN PUBLISH_DOWN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that event DOWN will publish to.
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable publishing

1 : Enabled

Enable publishing

End of enumeration elements list.


PUBLISH_UP

Publish configuration for event UP
address_offset : 0x188 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUBLISH_UP PUBLISH_UP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that event UP will publish to.
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable publishing

1 : Enabled

Enable publishing

End of enumeration elements list.


PUBLISH_CROSS

Publish configuration for event CROSS
address_offset : 0x18C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUBLISH_CROSS PUBLISH_CROSS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that event CROSS will publish to.
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable publishing

1 : Enabled

Enable publishing

End of enumeration elements list.


SHORTS

Shortcuts between local events and tasks
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHORTS SHORTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READY_SAMPLE READY_STOP DOWN_STOP UP_STOP CROSS_STOP

READY_SAMPLE : Shortcut between event READY and task SAMPLE
bits : 0 - -1 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.

READY_STOP : Shortcut between event READY and task STOP
bits : 1 - 0 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.

DOWN_STOP : Shortcut between event DOWN and task STOP
bits : 2 - 1 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.

UP_STOP : Shortcut between event UP and task STOP
bits : 3 - 2 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.

CROSS_STOP : Shortcut between event CROSS and task STOP
bits : 4 - 3 (0 bit)

Enumeration:

0 : Disabled

Disable shortcut

1 : Enabled

Enable shortcut

End of enumeration elements list.


INTEN

Enable or disable interrupt
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READY DOWN UP CROSS

READY : Enable or disable interrupt for event READY
bits : 0 - -1 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

DOWN : Enable or disable interrupt for event DOWN
bits : 1 - 0 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

UP : Enable or disable interrupt for event UP
bits : 2 - 1 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.

CROSS : Enable or disable interrupt for event CROSS
bits : 3 - 2 (0 bit)

Enumeration:

0 : Disabled

Disable

1 : Enabled

Enable

End of enumeration elements list.


INTENSET

Enable interrupt
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READY DOWN UP CROSS

READY : Write '1' to enable interrupt for event READY
bits : 0 - -1 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

DOWN : Write '1' to enable interrupt for event DOWN
bits : 1 - 0 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

UP : Write '1' to enable interrupt for event UP
bits : 2 - 1 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.

CROSS : Write '1' to enable interrupt for event CROSS
bits : 3 - 2 (0 bit)

Enumeration: ( write )

1 : Set

Enable

End of enumeration elements list.


INTENCLR

Disable interrupt
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READY DOWN UP CROSS

READY : Write '1' to disable interrupt for event READY
bits : 0 - -1 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

DOWN : Write '1' to disable interrupt for event DOWN
bits : 1 - 0 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

UP : Write '1' to disable interrupt for event UP
bits : 2 - 1 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.

CROSS : Write '1' to disable interrupt for event CROSS
bits : 3 - 2 (0 bit)

Enumeration: ( write )

1 : Clear

Disable

End of enumeration elements list.


TASKS_STOP

Stop comparator
address_offset : 0x4 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_STOP TASKS_STOP write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_STOP

TASKS_STOP : Stop comparator
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


RESULT

Compare result
address_offset : 0x400 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESULT RESULT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT

RESULT : Result of last compare. Decision point SAMPLE task.
bits : 0 - -1 (0 bit)

Enumeration:

0 : Below

Input voltage is below the threshold (VIN+ < VIN-)

1 : Above

Input voltage is above the threshold (VIN+ > VIN-)

End of enumeration elements list.


ENABLE

COMP enable
address_offset : 0x500 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENABLE ENABLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE

ENABLE : Enable or disable COMP
bits : 0 - 0 (1 bit)

Enumeration:

0 : Disabled

Disable

2 : Enabled

Enable

End of enumeration elements list.


PSEL

Pin select
address_offset : 0x504 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSEL PSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSEL

PSEL : Analog pin select
bits : 0 - 1 (2 bit)

Enumeration:

0 : AnalogInput0

AIN0 selected as analog input

1 : AnalogInput1

AIN1 selected as analog input

2 : AnalogInput2

AIN2 selected as analog input

3 : AnalogInput3

AIN3 selected as analog input

4 : AnalogInput4

AIN4 selected as analog input

5 : AnalogInput5

AIN5 selected as analog input

6 : AnalogInput6

AIN6 selected as analog input

7 : AnalogInput7

AIN7 selected as analog input

End of enumeration elements list.


REFSEL

Reference source select for single-ended mode
address_offset : 0x508 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REFSEL REFSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REFSEL

REFSEL : Reference select
bits : 0 - 1 (2 bit)

Enumeration:

0 : Int1V2

VREF = internal 1.2 V reference (VDD >= 1.7 V)

1 : Int1V8

VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V)

2 : Int2V4

VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V)

4 : VDD

VREF = VDD

5 : ARef

VREF = AREF

End of enumeration elements list.


EXTREFSEL

External reference select
address_offset : 0x50C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTREFSEL EXTREFSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTREFSEL

EXTREFSEL : External analog reference select
bits : 0 - 1 (2 bit)

Enumeration:

0 : AnalogReference0

Use AIN0 as external analog reference

1 : AnalogReference1

Use AIN1 as external analog reference

2 : AnalogReference2

Use AIN2 as external analog reference

3 : AnalogReference3

Use AIN3 as external analog reference

4 : AnalogReference4

Use AIN4 as external analog reference

5 : AnalogReference5

Use AIN5 as external analog reference

6 : AnalogReference6

Use AIN6 as external analog reference

7 : AnalogReference7

Use AIN7 as external analog reference

End of enumeration elements list.


TH

Threshold configuration for hysteresis unit
address_offset : 0x530 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TH TH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 THDOWN THUP

THDOWN : VDOWN = (THDOWN+1)/64*VREF
bits : 0 - 4 (5 bit)

THUP : VUP = (THUP+1)/64*VREF
bits : 8 - 12 (5 bit)


MODE

Mode configuration
address_offset : 0x534 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SP MAIN

SP : Speed and power modes
bits : 0 - 0 (1 bit)

Enumeration:

0 : Low

Low-power mode

1 : Normal

Normal mode

2 : High

High-speed mode

End of enumeration elements list.

MAIN : Main operation modes
bits : 8 - 7 (0 bit)

Enumeration:

0 : SE

Single-ended mode

1 : Diff

Differential mode

End of enumeration elements list.


HYST

Comparator hysteresis enable
address_offset : 0x538 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HYST HYST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HYST

HYST : Comparator hysteresis
bits : 0 - -1 (0 bit)

Enumeration:

0 : NoHyst

Comparator hysteresis disabled

1 : Hyst50mV

Comparator hysteresis enabled

End of enumeration elements list.


ISOURCE

Current source select on analog input
address_offset : 0x53C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISOURCE ISOURCE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISOURCE

ISOURCE : Comparator hysteresis
bits : 0 - 0 (1 bit)

Enumeration:

0 : Off

Current source disabled

1 : Ien2mA5

Current source enabled (+/- 2.5 uA)

2 : Ien5mA

Current source enabled (+/- 5 uA)

3 : Ien10mA

Current source enabled (+/- 10 uA)

End of enumeration elements list.


TASKS_SAMPLE

Sample comparator value
address_offset : 0x8 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TASKS_SAMPLE TASKS_SAMPLE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TASKS_SAMPLE

TASKS_SAMPLE : Sample comparator value
bits : 0 - -1 (0 bit)

Enumeration:

1 : Trigger

Trigger task

End of enumeration elements list.


SUBSCRIBE_START

Subscribe configuration for task START
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_START SUBSCRIBE_START read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task START will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


SUBSCRIBE_STOP

Subscribe configuration for task STOP
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_STOP SUBSCRIBE_STOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task STOP will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.


SUBSCRIBE_SAMPLE

Subscribe configuration for task SAMPLE
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSCRIBE_SAMPLE SUBSCRIBE_SAMPLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIDX EN

CHIDX : DPPI channel that task SAMPLE will subscribe to
bits : 0 - 6 (7 bit)

EN :
bits : 31 - 30 (0 bit)

Enumeration:

0 : Disabled

Disable subscription

1 : Enabled

Enable subscription

End of enumeration elements list.



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