Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Starts continuous I2S transfer. Also starts MCK generator when this is enabled
address_offset : 0x0 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TASKS_START : Starts continuous I2S transfer. Also starts MCK generator when this is enabled
bits : 0 - -1 (0 bit)
Enumeration:
1 : Trigger
Trigger task
End of enumeration elements list.
Unspecified - - I2S mode
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : I2S mode
bits : 0 - -1 (0 bit)
Enumeration:
0 : Master
Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx.
1 : Slave
Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx
End of enumeration elements list.
Unspecified - - Receive buffer RAM start address.
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PTR : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address.
bits : 0 - 30 (31 bit)
Unspecified - - Transmit buffer RAM start address
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PTR : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address.
bits : 0 - 30 (31 bit)
Unspecified - - Size of RXD and TXD buffers
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXCNT : Size of RXD and TXD buffers in number of 32 bit words
bits : 0 - 12 (13 bit)
Unspecified - - Pin select for MCK signal
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIN : Pin number
bits : 0 - 3 (4 bit)
PORT : Port number
bits : 5 - 4 (0 bit)
CONNECT : Connection
bits : 31 - 30 (0 bit)
Enumeration:
1 : Disconnected
Disconnect
0 : Connected
Connect
End of enumeration elements list.
Unspecified - - I2S clock generator control
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCKFREQ : I2S MCK frequency configuration NOTE: Enumerations are deprecated, use MCKFREQ equation. NOTE: The 12 least significant bits of the register are ignored and shall be set to zero.
bits : 0 - 30 (31 bit)
Enumeration:
0x80000000 : 32MDIV2
32 MHz / 2 = 16.0 MHz Deprecated, use MCKFREQ equation.
0x50000000 : 32MDIV3
32 MHz / 3 = 10.6666667 MHz Deprecated, use MCKFREQ equation.
0x40000000 : 32MDIV4
32 MHz / 4 = 8.0 MHz Deprecated, use MCKFREQ equation.
0x30000000 : 32MDIV5
32 MHz / 5 = 6.4 MHz Deprecated, use MCKFREQ equation.
0x28000000 : 32MDIV6
32 MHz / 6 = 5.3333333 MHz Deprecated, use MCKFREQ equation.
0x20000000 : 32MDIV8
32 MHz / 8 = 4.0 MHz Deprecated, use MCKFREQ equation.
0x18000000 : 32MDIV10
32 MHz / 10 = 3.2 MHz Deprecated, use MCKFREQ equation.
0x16000000 : 32MDIV11
32 MHz / 11 = 2.9090909 MHz Deprecated, use MCKFREQ equation.
0x11000000 : 32MDIV15
32 MHz / 15 = 2.1333333 MHz Deprecated, use MCKFREQ equation.
0x10000000 : 32MDIV16
32 MHz / 16 = 2.0 MHz Deprecated, use MCKFREQ equation.
0x0C000000 : 32MDIV21
32 MHz / 21 = 1.5238095 Deprecated, use MCKFREQ equation.
0x0B000000 : 32MDIV23
32 MHz / 23 = 1.3913043 MHz Deprecated, use MCKFREQ equation.
0x08800000 : 32MDIV30
32 MHz / 30 = 1.0666667 MHz Deprecated, use MCKFREQ equation.
0x08400000 : 32MDIV31
32 MHz / 31 = 1.0322581 MHz Deprecated, use MCKFREQ equation.
0x08000000 : 32MDIV32
32 MHz / 32 = 1.0 MHz Deprecated, use MCKFREQ equation.
0x06000000 : 32MDIV42
32 MHz / 42 = 0.7619048 MHz Deprecated, use MCKFREQ equation.
0x04100000 : 32MDIV63
32 MHz / 63 = 0.5079365 MHz Deprecated, use MCKFREQ equation.
0x020C0000 : 32MDIV125
32 MHz / 125 = 0.256 MHz Deprecated, use MCKFREQ equation.
End of enumeration elements list.
Unspecified - - Pin select for SDOUT signal
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIN : Pin number
bits : 0 - 3 (4 bit)
PORT : Port number
bits : 5 - 4 (0 bit)
CONNECT : Connection
bits : 31 - 30 (0 bit)
Enumeration:
1 : Disconnected
Disconnect
0 : Connected
Connect
End of enumeration elements list.
The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin.
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVENTS_RXPTRUPD : The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin.
bits : 0 - -1 (0 bit)
Enumeration:
0 : NotGenerated
Event not generated
1 : Generated
Event generated
End of enumeration elements list.
I2S transfer stopped.
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVENTS_STOPPED : I2S transfer stopped.
bits : 0 - -1 (0 bit)
Enumeration:
0 : NotGenerated
Event not generated
1 : Generated
Event generated
End of enumeration elements list.
The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin.
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVENTS_TXPTRUPD : The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin.
bits : 0 - -1 (0 bit)
Enumeration:
0 : NotGenerated
Event not generated
1 : Generated
Event generated
End of enumeration elements list.
Frame start event, generated on the active edge of LRCK
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVENTS_FRAMESTART : Frame start event, generated on the active edge of LRCK
bits : 0 - -1 (0 bit)
Enumeration:
0 : NotGenerated
Event not generated
1 : Generated
Event generated
End of enumeration elements list.
Unspecified - - MCK / LRCK ratio
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RATIO : MCK / LRCK ratio
bits : 0 - 2 (3 bit)
Enumeration:
0 : 32X
LRCK = MCK / 32
1 : 48X
LRCK = MCK / 48
2 : 64X
LRCK = MCK / 64
3 : 96X
LRCK = MCK / 96
4 : 128X
LRCK = MCK / 128
5 : 192X
LRCK = MCK / 192
6 : 256X
LRCK = MCK / 256
7 : 384X
LRCK = MCK / 384
8 : 512X
LRCK = MCK / 512
End of enumeration elements list.
Unspecified - - Sample width
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWIDTH : Sample and half-frame width
bits : 0 - 1 (2 bit)
Enumeration:
0 : 8Bit
8 bit sample.
1 : 16Bit
16 bit sample.
2 : 24Bit
24 bit sample.
3 : 32Bit
32-bit sample.
4 : 8BitIn16
8 bit sample in a 16 bit half-frame.
5 : 8BitIn32
8 bit sample in a 32-bit half-frame.
6 : 16BitIn32
16 bit sample in a 32-bit half-frame.
7 : 24BitIn32
24 bit sample in a 32-bit half-frame.
End of enumeration elements list.
Publish configuration for event RXPTRUPD
address_offset : 0x184 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIDX : DPPI channel that event RXPTRUPD will publish to.
bits : 0 - 6 (7 bit)
EN :
bits : 31 - 30 (0 bit)
Enumeration:
0 : Disabled
Disable publishing
1 : Enabled
Enable publishing
End of enumeration elements list.
Publish configuration for event STOPPED
address_offset : 0x188 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIDX : DPPI channel that event STOPPED will publish to.
bits : 0 - 6 (7 bit)
EN :
bits : 31 - 30 (0 bit)
Enumeration:
0 : Disabled
Disable publishing
1 : Enabled
Enable publishing
End of enumeration elements list.
Publish configuration for event TXPTRUPD
address_offset : 0x194 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIDX : DPPI channel that event TXPTRUPD will publish to.
bits : 0 - 6 (7 bit)
EN :
bits : 31 - 30 (0 bit)
Enumeration:
0 : Disabled
Disable publishing
1 : Enabled
Enable publishing
End of enumeration elements list.
Publish configuration for event FRAMESTART
address_offset : 0x19C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIDX : DPPI channel that event FRAMESTART will publish to.
bits : 0 - 6 (7 bit)
EN :
bits : 31 - 30 (0 bit)
Enumeration:
0 : Disabled
Disable publishing
1 : Enabled
Enable publishing
End of enumeration elements list.
Unspecified - - Alignment of sample within a frame
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALIGN : Alignment of sample within a frame
bits : 0 - -1 (0 bit)
Enumeration:
0 : Left
Left-aligned.
1 : Right
Right-aligned.
End of enumeration elements list.
Unspecified - - Frame format
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FORMAT : Frame format
bits : 0 - -1 (0 bit)
Enumeration:
0 : I2S
Original I2S format.
1 : Aligned
Alternate (left- or right-aligned) format.
End of enumeration elements list.
Unspecified - - Enable channels
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNELS : Enable channels
bits : 0 - 0 (1 bit)
Enumeration:
0 : Stereo
Stereo.
1 : Left
Left only.
2 : Right
Right only.
End of enumeration elements list.
Unspecified - - Clock source selection for the I2S module
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKSRC : Clock source selection
bits : 0 - -1 (0 bit)
Enumeration:
0 : PCLK32M
32MHz peripheral clock
1 : ACLK
Audio PLL clock
End of enumeration elements list.
BYPASS : Bypass clock generator. MCK will be equal to source input. If bypass is enabled the MCKFREQ setting has no effect.
bits : 8 - 7 (0 bit)
Enumeration:
0 : Disable
Disable bypass
1 : Enable
Enable bypass
End of enumeration elements list.
Enable or disable interrupt
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXPTRUPD : Enable or disable interrupt for event RXPTRUPD
bits : 1 - 0 (0 bit)
Enumeration:
0 : Disabled
Disable
1 : Enabled
Enable
End of enumeration elements list.
STOPPED : Enable or disable interrupt for event STOPPED
bits : 2 - 1 (0 bit)
Enumeration:
0 : Disabled
Disable
1 : Enabled
Enable
End of enumeration elements list.
TXPTRUPD : Enable or disable interrupt for event TXPTRUPD
bits : 5 - 4 (0 bit)
Enumeration:
0 : Disabled
Disable
1 : Enabled
Enable
End of enumeration elements list.
FRAMESTART : Enable or disable interrupt for event FRAMESTART
bits : 7 - 6 (0 bit)
Enumeration:
0 : Disabled
Disable
1 : Enabled
Enable
End of enumeration elements list.
Enable interrupt
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXPTRUPD : Write '1' to enable interrupt for event RXPTRUPD
bits : 1 - 0 (0 bit)
Enumeration: ( write )
1 : Set
Enable
End of enumeration elements list.
STOPPED : Write '1' to enable interrupt for event STOPPED
bits : 2 - 1 (0 bit)
Enumeration: ( write )
1 : Set
Enable
End of enumeration elements list.
TXPTRUPD : Write '1' to enable interrupt for event TXPTRUPD
bits : 5 - 4 (0 bit)
Enumeration: ( write )
1 : Set
Enable
End of enumeration elements list.
FRAMESTART : Write '1' to enable interrupt for event FRAMESTART
bits : 7 - 6 (0 bit)
Enumeration: ( write )
1 : Set
Enable
End of enumeration elements list.
Disable interrupt
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXPTRUPD : Write '1' to disable interrupt for event RXPTRUPD
bits : 1 - 0 (0 bit)
Enumeration: ( write )
1 : Clear
Disable
End of enumeration elements list.
STOPPED : Write '1' to disable interrupt for event STOPPED
bits : 2 - 1 (0 bit)
Enumeration: ( write )
1 : Clear
Disable
End of enumeration elements list.
TXPTRUPD : Write '1' to disable interrupt for event TXPTRUPD
bits : 5 - 4 (0 bit)
Enumeration: ( write )
1 : Clear
Disable
End of enumeration elements list.
FRAMESTART : Write '1' to disable interrupt for event FRAMESTART
bits : 7 - 6 (0 bit)
Enumeration: ( write )
1 : Clear
Disable
End of enumeration elements list.
Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the event STOPPED to be generated.
address_offset : 0x4 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TASKS_STOP : Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the event STOPPED to be generated.
bits : 0 - -1 (0 bit)
Enumeration:
1 : Trigger
Trigger task
End of enumeration elements list.
Unspecified - - Reception (RX) enable
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXEN : Reception (RX) enable
bits : 0 - -1 (0 bit)
Enumeration:
0 : Disabled
Reception disabled and now data will be written to the RXD.PTR address.
1 : Enabled
Reception enabled.
End of enumeration elements list.
Unspecified - - Pin select for SCK signal
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIN : Pin number
bits : 0 - 3 (4 bit)
PORT : Port number
bits : 5 - 4 (0 bit)
CONNECT : Connection
bits : 31 - 30 (0 bit)
Enumeration:
1 : Disconnected
Disconnect
0 : Connected
Connect
End of enumeration elements list.
Enable I2S module
address_offset : 0x500 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Enable I2S module
bits : 0 - -1 (0 bit)
Enumeration:
0 : Disabled
Disable
1 : Enabled
Enable
End of enumeration elements list.
Unspecified - - Transmission (TX) enable
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXEN : Transmission (TX) enable
bits : 0 - -1 (0 bit)
Enumeration:
0 : Disabled
Transmission disabled and now data will be read from the RXD.TXD address.
1 : Enabled
Transmission enabled.
End of enumeration elements list.
Unspecified - - Pin select for LRCK signal
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIN : Pin number
bits : 0 - 3 (4 bit)
PORT : Port number
bits : 5 - 4 (0 bit)
CONNECT : Connection
bits : 31 - 30 (0 bit)
Enumeration:
1 : Disconnected
Disconnect
0 : Connected
Connect
End of enumeration elements list.
Subscribe configuration for task START
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIDX : DPPI channel that task START will subscribe to
bits : 0 - 6 (7 bit)
EN :
bits : 31 - 30 (0 bit)
Enumeration:
0 : Disabled
Disable subscription
1 : Enabled
Enable subscription
End of enumeration elements list.
Subscribe configuration for task STOP
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIDX : DPPI channel that task STOP will subscribe to
bits : 0 - 6 (7 bit)
EN :
bits : 31 - 30 (0 bit)
Enumeration:
0 : Disabled
Disable subscription
1 : Enabled
Enable subscription
End of enumeration elements list.
Unspecified - - Master clock generator enable
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCKEN : Master clock generator enable
bits : 0 - -1 (0 bit)
Enumeration:
0 : Disabled
Master clock generator disabled and PSEL.MCK not connected(available as GPIO).
1 : Enabled
Master clock generator running and MCK output on PSEL.MCK.
End of enumeration elements list.
Unspecified - - Pin select for SDIN signal
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIN : Pin number
bits : 0 - 3 (4 bit)
PORT : Port number
bits : 5 - 4 (0 bit)
CONNECT : Connection
bits : 31 - 30 (0 bit)
Enumeration:
1 : Disconnected
Disconnect
0 : Connected
Connect
End of enumeration elements list.
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