PPR

CMR0

PDR0

CNR1

CMR1

PDR1

CNR2

CMR2

PDR2

CNR3

CMR3

PDR3

PBCR

CSR

PIER

PIIR

CCR0

CCR2

CRLR0

CFLR0

CRLR1

CFLR1

CRLR2

CFLR2

CRLR3

CFLR3

CAPENR

POE

PCR

CNR0

CP01 : Clock prescaler 0 (PWM-timer 0 & 1 for group A and PWM-timer 4 & 5 for group B) Clock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-timer If CP01=0, then the clock prescaler 0 output clock will be stopped. So corresponding PWM-timer will be stopped also.
bits : 0 - 7 (8 bit)
access : read-write

CP23 : Clock prescaler 2 (PWM-timer2 & 3 for group A and PWM-timer 6 & 7 for group B) Clock input is divided by (CP23 + 1) before it is fed to the corresponding PWM-timer. If CP23=0, then the clock prescaler 2 output clock will be stopped. So corresponding PWM-timer will be stopped also.
bits : 8 - 15 (8 bit)
access : read-write

DZI01 : Dead Zone Interval for Pair of Channel 0 and Channel 1 (PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B) These 8 bits determine dead zone length. The unit time of dead zone length is received from corresponding CSR bits.
bits : 16 - 23 (8 bit)
access : read-write

DZI23 : Dead Zone Interval for Pair of Channel2 and Channel3 (PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B) These 8 bits determine dead zone length. The unit time of dead zone length is received from corresponding CSR bits.
bits : 24 - 31 (8 bit)
access : read-write

CMR : PWM Comparator Register CMR determines the PWM duty. PWM frequency = PWM01_CLK/(prescale+1)*(clock divider)/(CNR+1). Duty ratio = (CMR+1)/(CNR+1). CMR >= CNR: PWM output is always high. CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit (Unit : 1 PWM clock cycle) Note: Any write to CMR will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write

PDR : PWM Data Register User can monitor PDR to know current value in 16-bit down counter.
bits : 0 - 15 (16 bit)
access : read-only

CNR : PWM Counter/Timer Loaded Value CNR determines the PWM period. PWM frequency = PWM01_CLK/(prescale+1)*(clock divider)/(CNR+1). Duty ratio = (CMR+1)/(CNR+1). CMR >= CNR: PWM output is always high. CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit (Unit : 1 PWM clock cycle) Note: Any write to CNR will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write

CMR : PWM Comparator Register CMR determines the PWM duty. PWM frequency = PWM01_CLK/(prescale+1)*(clock divider)/(CNR+1). Duty ratio = (CMR+1)/(CNR+1). CMR >= CNR: PWM output is always high. CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit (Unit : 1 PWM clock cycle) Note: Any write to CMR will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write

PDR : PWM Data Register User can monitor PDR to know current value in 16-bit down counter.
bits : 0 - 15 (16 bit)
access : read-only

CNR : PWM Counter/Timer Loaded Value CNR determines the PWM period. PWM frequency = PWM23_CLK/(prescale+1)*(clock divider)/(CNR+1). Duty ratio = (CMR+1)/(CNR+1). CMR >= CNR: PWM output is always high. CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit (Unit : 1 PWM clock cycle) Note: Any write to CNR will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write

CMR : PWM Comparator Register CMR determines the PWM duty. PWM frequency = PWM23_CLK/(prescale+1)*(clock divider)/(CNR+1). Duty ratio = (CMR+1)/(CNR+1). CMR >= CNR: PWM output is always high. CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit (Unit : 1 PWM clock cycle) Note: Any write to CMR will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write

PDR : PWM Data Register User can monitor PDR to know current value in 16-bit down counter.
bits : 0 - 15 (16 bit)
access : read-only

CNR : PWM Counter/Timer Loaded Value CNR determines the PWM period. PWM frequency = PWM23_CLK/(prescale+1)*(clock divider)/(CNR+1). Duty ratio = (CMR+1)/(CNR+1). CMR >= CNR: PWM output is always high. CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit (Unit : 1 PWM clock cycle) Note: Any write to CNR will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write

CMR : PWM Comparator Register CMR determines the PWM duty. PWM frequency = PWM23_CLK/(prescale+1)*(clock divider)/(CNR+1). Duty ratio = (CMR+1)/(CNR+1). CMR >= CNR: PWM output is always high. CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit (Unit : 1 PWM clock cycle) Note: Any write to CMR will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write

PDR : PWM Data Register User can monitor PDR to know current value in 16-bit down counter.
bits : 0 - 15 (16 bit)
access : read-only

BCn : PWM Backward Compatible Register 0 = PWM register action is compatible with Medium Density 1 = PWM register action is not compatible with Medium Density Please reference CCR0/CCR2 register bit 6, 7, 22, 23 description
bits : 0 - 0 (1 bit)
access : read-write

CSR0 : PWM Timer 0 Clock Source Selection (PWM timer 0 for group A and PWM timer 4 for group B) Select clock input for PWM timer. (Table is the same as CSR3)
bits : 0 - 2 (3 bit)
access : read-write

CSR1 : PWM Timer 1 Clock Source Selection (PWM timer 1 for group A and PWM timer 5 for group B) Select clock input for PWM timer. (Table is the same as CSR3)
bits : 4 - 6 (3 bit)
access : read-write

CSR2 : PWM Timer 2 Clock Source Selection (PWM timer 2 for group A and PWM timer 6 for group B) Select clock input for PWM timer. (Table is the same as CSR3)
bits : 8 - 10 (3 bit)
access : read-write

CSR3 : PWM Timer 3 Clock Source Selection (PWM timer 3 for group A and PWM timer 7 for group B) Select clock input for PWM timer. CSR3 [14:12] Input clock divided by 100 1 011 16 010 8 001 4 000 2
bits : 12 - 14 (3 bit)
access : read-write

PWMIE0 : PWM Channel 0 Interrupt Enable 1 = Enable 0 = Disable
bits : 0 - 0 (1 bit)
access : read-write

PWMIE1 : PWM Channel 1 Interrupt Enable 1 = Enable 0 = Disable
bits : 1 - 1 (1 bit)
access : read-write

PWMIE2 : PWM Channel 2 Interrupt Enable 1 = Enable 0 = Disable
bits : 2 - 2 (1 bit)
access : read-write

PWMIE3 : PWM Channel 3 Interrupt Enable 1 = Enable 0 = Disable
bits : 3 - 3 (1 bit)
access : read-write

PWMIF0 : PWM Channel 0 Interrupt Status Flag is set by hardware when PWM0 down counter reaches zero, software can write 1 to clear this bit to zero.
bits : 0 - 0 (1 bit)
access : read-write

PWMIF1 : PWM Channel 1 Interrupt Status Flag is set by hardware when PWM1 down counter reaches zero, software can write 1 to clear this bit to zero.
bits : 1 - 1 (1 bit)
access : read-write

PWMIF2 : PWM Channel 2 Interrupt Status Flag is set by hardware when PWM2 down counter reaches zero, software can write 1 to clear this bit to zero.
bits : 2 - 2 (1 bit)
access : read-write

PWMIF3 : PWM Channel 3 Interrupt Status Flag is set by hardware when PWM3 down counter reaches zero, software can write 1 to clear this bit to zero.
bits : 3 - 3 (1 bit)
access : read-write

INV0 : Channel 0 Inverter Enable 1 = Inverter enable. Reverse the input signal from GPIO before fed to Capture timer 0 = Inverter disable
bits : 0 - 0 (1 bit)
access : read-write

CRL_IE0 : Channel 0 Rising Latch Interrupt Enable 1 = Enable rising latch interrupt 0 = Disable rising latch interrupt When Enable, if Capture detects PWM group channel 0 has rising transition, Capture issues an Interrupt.
bits : 1 - 1 (1 bit)
access : read-write

CFL_IE0 : Channel 0 Falling Latch Interrupt Enable 1 = Enable falling latch interrupt 0 = Disable falling latch interrupt When Enable, if Capture detects PWM group channel 0 has falling transition, Capture issues an Interrupt.
bits : 2 - 2 (1 bit)
access : read-write

CAPCH0EN : Channel 0 Capture Function Enable 1 = Enable capture function on PWM group channel 0. 0 = Disable capture function on PWM group channel 0. When Enable, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch). When Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 0 Interrupt.
bits : 3 - 3 (1 bit)
access : read-write

CAPIF0 : Channel 0 Capture Interrupt Indication Flag If PWM group channel 0 rising latch interrupt is enabled (CRL_IE0=1), a rising transition occurs at PWM group channel 0 will result in CAPIF0 to high; Similarly, a falling transition will cause CAPIF0 to be set high if PWM group channel 0 falling latch interrupt is enabled (CFL_IE0=1). Write 1 to clear this bit to zero
bits : 4 - 4 (1 bit)
access : read-write

CRLRI0 : CRLR0 Latched Indicator Bit When PWM group input channel 0 has a rising transition, CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware. In Medium Density, software can write 0 to clear this bit to zero. In Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1.
bits : 6 - 6 (1 bit)
access : read-write

CFLRI0 : CFLR0 Latched Indicator Bit When PWM group input channel 0 has a falling transition, CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware. In Medium Density, software can write 0 to clear this bit to zero. In Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1.
bits : 7 - 7 (1 bit)
access : read-write

INV1 : Channel 1 Inverter Enable 1 = Inverter enable. Reverse the input signal from GPIO before fed to Capture timer 0 = Inverter disable
bits : 16 - 16 (1 bit)
access : read-write

CRL_IE1 : Channel 1 Rising Latch Interrupt Enable 1 = Enable rising latch interrupt 0 = Disable rising latch interrupt When Enable, if Capture detects PWM group channel 1 has rising transition, Capture issues an Interrupt.
bits : 17 - 17 (1 bit)
access : read-write

CFL_IE1 : Channel 1 Falling Latch Interrupt Enable 1 = Enable falling latch interrupt 0 = Disable falling latch interrupt When Enable, if Capture detects PWM group channel 1 has falling transition, Capture issues an Interrupt.
bits : 18 - 18 (1 bit)
access : read-write

CAPCH1EN : Channel 1 Capture Function Enable 1 = Enable capture function on PWM group channel 1. 0 = Disable capture function on PWM group channel 1. When Enable, Capture latched the PMW-counter and saved to CRLR (Rising latch) and CFLR (Falling latch). When Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 1 Interrupt.
bits : 19 - 19 (1 bit)
access : read-write

CAPIF1 : Channel 1 Capture Interrupt Indication Flag If PWM group channel 1 rising latch interrupt is enabled (CRL_IE1=1), a rising transition occurs at PWM group channel 1 will result in CAPIF1 to high; Similarly, a falling transition will cause CAPIF1 to be set high if PWM group channel 1 falling latch interrupt is enabled (CFL_IE1=1). Write 1 to clear this bit to zero
bits : 20 - 20 (1 bit)
access : read-write

CRLRI1 : CRLR1 Latched Indicator Bit When PWM group input channel 1 has a rising transition, CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware. In Medium Density, software can write 0 to clear this bit to zero. In Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1.
bits : 22 - 22 (1 bit)
access : read-write

CFLRI1 : CFLR1 Latched Indicator Bit When PWM group input channel 1 has a falling transition, CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware. In Medium Density, software can write 0 to clear this bit to zero. In Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1.
bits : 23 - 23 (1 bit)
access : read-write

INV2 : Channel 2 Inverter Enable 1 = Inverter enable. Reverse the input signal from GPIO before fed to Capture timer 0 = Inverter disable
bits : 0 - 0 (1 bit)
access : read-write

CRL_IE2 : Channel 2 Rising Latch Interrupt Enable 1 = Enable rising latch interrupt 0 = Disable rising latch interrupt When Enable, if Capture detects PWM group channel 2 has rising transition, Capture issues an Interrupt.
bits : 1 - 1 (1 bit)
access : read-write

CFL_IE2 : Channel 2 Falling Latch Interrupt Enable 1 = Enable falling latch interrupt 0 = Disable falling latch interrupt When Enable, if Capture detects PWM group channel 2 has falling transition, Capture issues an Interrupt.
bits : 2 - 2 (1 bit)
access : read-write

CAPCH2EN : Channel 2 Capture Function Enable 1 = Enable capture function on PWM group channel 2. 0 = Disable capture function on PWM group channel 2. When Enable, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch). When Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 2 Interrupt.
bits : 3 - 3 (1 bit)
access : read-write

CAPIF2 : Channel 2 Capture Interrupt Indication Flag If PWM group channel 2 rising latch interrupt is enabled (CRL_IE2=1), a rising transition occurs at PWM group channel 2 will result in CAPIF2 to high; Similarly, a falling transition will cause CAPIF2 to be set high if PWM group channel 2 falling latch interrupt is enabled (CFL_IE2=1). Write 1 to clear this bit to zero
bits : 4 - 4 (1 bit)
access : read-write

CRLRI2 : CRLR2 Latched Indicator Bit When PWM group input channel 2 has a rising transition, CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware. In Medium Density, software can write 0 to clear this bit to zero. In Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1.
bits : 6 - 6 (1 bit)
access : read-write

CFLRI2 : CFLR2 Latched Indicator Bit When PWM group input channel 2 has a falling transition, CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware. In Medium Density, software can write 0 to clear this bit to zero. In Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1.
bits : 7 - 7 (1 bit)
access : read-write

INV3 : Channel 3 Inverter Enable 1 = Inverter enable. Reverse the input signal from GPIO before fed to Capture timer 0 = Inverter disable
bits : 16 - 16 (1 bit)
access : read-write

CRL_IE3 : Channel 3 Rising Latch Interrupt Enable 1 = Enable rising latch interrupt 0 = Disable rising latch interrupt When Enable, if Capture detects PWM group channel 3 has rising transition, Capture issues an Interrupt.
bits : 17 - 17 (1 bit)
access : read-write

CFL_IE3 : Channel 3 Falling Latch Interrupt Enable 1 = Enable falling latch interrupt 0 = Disable falling latch interrupt When Enable, if Capture detects PWM group channel 3 has falling transition, Capture issues an Interrupt.
bits : 18 - 18 (1 bit)
access : read-write

CAPCH3EN : Channel 3 Capture Function Enable 1 = Enable capture function on PWM group channel 3. 0 = Disable capture function on PWM group channel 3. When Enable, Capture latched the PMW-counter and saved to CRLR (Rising latch) and CFLR (Falling latch). When Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 3 Interrupt.
bits : 19 - 19 (1 bit)
access : read-write

CAPIF3 : Channel 3 Capture Interrupt Indication Flag If PWM group channel 3 rising latch interrupt is enabled (CRL_IE3=1), a rising transition occurs at PWM group channel 3 will result in CAPIF3 to high; Similarly, a falling transition will cause CAPIF3 to be set high if PWM group channel 3 falling latch interrupt is enabled (CFL_IE3=1). Write 1 to clear this bit to zero
bits : 20 - 20 (1 bit)
access : read-write

CRLRI3 : CRLR3 Latched Indicator Bit When PWM group input channel 3 has a rising transition, CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware. In Medium Density, software can write 0 to clear this bit to zero. In Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1.
bits : 22 - 22 (1 bit)
access : read-write

CFLRI3 : CFLR3 Latched Indicator Bit When PWM group input channel 3 has a falling transition, CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware. In Medium Density, software can write 0 to clear this bit to zero. In Low Density, software can write 0 to clear this bit to zero if BCn bit is 0, and can Write 1 to clear this bit to zero if BCn bit is 1.
bits : 23 - 23 (1 bit)
access : read-write

CRLR : Capture Rising Latch Register Latch the PWM counter when Channel 0 has rising transition.
bits : 0 - 15 (16 bit)
access : read-only

CFLR : Capture Falling Latch Register Latch the PWM counter when Channel 0 has Falling transition.
bits : 0 - 15 (16 bit)
access : read-only

CRLR : Capture Rising Latch Register Latch the PWM counter when Channel 1 has rising transition.
bits : 0 - 15 (16 bit)
access : read-only

CFLR : Capture Falling Latch Register Latch the PWM counter when Channel 1 has Falling transition.
bits : 0 - 15 (16 bit)
access : read-only

CRLR : Capture Rising Latch Register Latch the PWM counter when Channel 2 has rising transition.
bits : 0 - 15 (16 bit)
access : read-only

CFLR : Capture Falling Latch Register Latch the PWM counter when Channel 2 has Falling transition.
bits : 0 - 15 (16 bit)
access : read-only

CRLR : Capture Rising Latch Register Latch the PWM counter when Channel 3 has rising transition.
bits : 0 - 15 (16 bit)
access : read-only

CFLR : Capture Falling Latch Register Latch the PWM counter when Channel 3 has Falling transition.
bits : 0 - 15 (16 bit)
access : read-only

CAPENR : Capture Input Enable Register There are four capture inputs from pad. Bit0~Bit3 are used to control each inputs enable or disable. 0 = Disable (PWMx multi-function pin input does not affect input capture function) 1 = Enable (PWMx multi-function pin input will affect its input capture function.) CAPENR Bit 3210 for PWM group A Bit xxx1 Capture channel 0 is from pin PA.12 Bit xx1x Capture channel 1 is from pin PA.13 Bit x1xx Capture channel 2 is from pin PA.14 Bit 1xxx Capture channel 3 is from pin PA.15 Bit 3210 for PWM group B Bit xxx1 Capture channel 0 is from pin PE.11 Bit xx1x Capture channel 1 is from pin PE.5 Bit x1xx Capture channel 2 is from pin PE.0 Bit 1xxx Capture channel 3 is from pin PE.1
bits : 0 - 3 (4 bit)
access : read-write

PWM0 : PWM Channel 0 Output Enable Register 1 = Enable PWM channel 0 output to pin 0 = Disable PWM channel 0 output to pin Note: The corresponding GPIO pin also must be switched to PWM function.
bits : 0 - 0 (1 bit)
access : read-write

PWM1 : PWM Channel 1 Output Enable Register 1 = Enable PWM channel 1 output to pin 0 = Disable PWM channel 1 output to pin Note: The corresponding GPIO pin also must be switched to PWM function.
bits : 1 - 1 (1 bit)
access : read-write

PWM2 : PWM Channel 2 Output Enable Register 1 = Enable PWM channel 2 output to pin 0 = Disable PWM channel 2 output to pin Note: The corresponding GPIO pin also must be switched to PWM function.
bits : 2 - 2 (1 bit)
access : read-write

PWM3 : PWM Channel 3 Output Enable Register 1 = Enable PWM channel 3 output to pin 0 = Disable PWM channel 3 output to pin Note: The corresponding GPIO pin also must be switched to PWM function.
bits : 3 - 3 (1 bit)
access : read-write

CH0EN : PWM-Timer 0 Enable (PWM timer 0 for group A and PWM timer 4 for group B) 1 = Enable corresponding PWM-Timer Start Run 0 = Stop corresponding PWM-Timer Running
bits : 0 - 0 (1 bit)
access : read-write

CH0INV : PWM-Timer 0 Output Inverter Enable (PWM timer 0 for group A and PWM timer 4 for group B) 1 = Inverter enable 0 = Inverter disable
bits : 2 - 2 (1 bit)
access : read-write

CH0MOD : PWM-Timer 0 Auto-reload/One-Shot Mode (PWM timer 0 for group A and PWM timer 4 for group B) 1 = Auto-reload Mode 0 = One-Shot Mode Note: If there is a rising transition at this bit, it will cause CNR0 and CMR0 be clear.
bits : 3 - 3 (1 bit)
access : read-write

DZEN01 : Dead-Zone 0 Generator Enable (PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B) 1 = Enable 0 = Disable Note: When Dead-Zone Generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A and the pair of PWM4 and PWM5 becomes a complementary pair for PWM group B.
bits : 4 - 4 (1 bit)
access : read-write

DZEN23 : Dead-Zone 2 Generator Enable (PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B) 1 = Enable 0 = Disable Note: When Dead-Zone Generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A and the pair of PWM6 and PWM7 becomes a complementary pair for PWM group B.
bits : 5 - 5 (1 bit)
access : read-write

CH1EN : PWM-Timer 1 Enable (PWM timer 1 for group A and PWM timer 5 for group B) 1 = Enable corresponding PWM-Timer Start Run 0 = Stop corresponding PWM-Timer Running
bits : 8 - 8 (1 bit)
access : read-write

CH1INV : PWM-Timer 1 Output Inverter Enable (PWM timer 1 for group A and PWM timer 5 for group B) 1 = Inverter enable 0 = Inverter disable
bits : 10 - 10 (1 bit)
access : read-write

CH1MOD : PWM-Timer 1 Auto-reload/One-Shot Mode (PWM timer 1 for group A and PWM timer 5 for group B) 1 = Auto-load Mode 0 = One-Shot Mode Note: If there is a rising transition at this bit, it will cause CNR1 and CMR1 be clear.
bits : 11 - 11 (1 bit)
access : read-write

CH2EN : PWM-Timer 2 Enable (PWM timer 2 for group A and PWM timer 6 for group B) 1 = Enable corresponding PWM-Timer Start Run 0 = Stop corresponding PWM-Timer Running
bits : 16 - 16 (1 bit)
access : read-write

CH2INV : PWM-Timer 2 Output Inverter Enable (PWM timer 2 for group A and PWM timer 6 for group B) 1 = Inverter enable 0 = Inverter disable
bits : 18 - 18 (1 bit)
access : read-write

CH2MOD : PWM-Timer 2 Auto-reload/One-Shot Mode (PWM timer 2 for group A and PWM timer 6 for group B) 1 = Auto-reload Mode 0 = One-Shot Mode Note: If there is a rising transition at this bit, it will cause CNR2 and CMR2 be clear.
bits : 19 - 19 (1 bit)
access : read-write

CH3EN : PWM-Timer 3 Enable (PWM timer 3 for group A and PWM timer 7 for group B) 1 = Enable corresponding PWM-Timer Start Run 0 = Stop corresponding PWM-Timer Running
bits : 24 - 24 (1 bit)
access : read-write

CH3INV : PWM-Timer 3 Output Inverter Enable (PWM timer 3 for group A and PWM timer 7 for group B) 1 = Inverter enable 0 = Inverter disable
bits : 26 - 26 (1 bit)
access : read-write

CH3MOD : PWM-Timer 3 Auto-reload/One-Shot Mode (PWM timer 3 for group A and PWM timer 7 for group B) 1 = Auto-reload Mode 0 = One-Shot Mode Note: If there is a rising transition at this bit, it will cause CNR3 and CMR3 be clear.
bits : 27 - 27 (1 bit)
access : read-write

CNR : PWM Counter/Timer Loaded Value CNR determines the PWM period. PWM frequency = PWM01_CLK/(prescale+1)*(clock divider)/(CNR+1). Duty ratio = (CMR+1)/(CNR+1). CMR >= CNR: PWM output is always high. CMR < CNR: PWM low width = (CNR-CMR) unit; PWM high width = (CMR+1) unit. CMR = 0: PWM low width = (CNR) unit; PWM high width = 1 unit (Unit : 1 PWM clock cycle) Note: Any write to CNR will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write