ADDR0

ADDR4

ADDR5

ADDR6

ADDR7

ADCR

ADCHER

ADCMPR0

ADCMPR1

ADSR

ADCALR

ADDR1

ADPDMA

ADDR2

ADDR3

RSLT : A/D Conversion Result This field contains conversion result of ADC. For Medium density, RSLT[15:12] always read as 0. For Low density, if DMOF bit (ADCR[31]) set to 0, 12 bits ADC conversion result with unsigned format will be filled in RSLT[11:0] and zero will be filled in RSLT[15:12]. If DMOF bit (ADCR[31]) set to 1, 12 bits ADC conversion result with 2's complement format will be filled in RSLT[11:0] and signed bits will be filled in RSLT[15:12]
bits : 0 - 15 (16 bit)
access : read-only

OVERRUN : Over Run Flag 1 = Data in RSLT[11:0] is overwrite. 0 = Data in RSLT[11:0] is recent conversion result. If converted data in RSLT[11:0] has not been read before new conversion result is loaded to this register, OVERRUN is set to 1 and previous conversion result is gone. It will be cleared by hardware after ADDR register is read.
bits : 16 - 16 (1 bit)
access : read-only

VALID : Valid Flag 1 = Data in RSLT[11:0] bits is valid. 0 = Data in RSLT[11:0] bits is not valid. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.
bits : 17 - 17 (1 bit)
access : read-only

RSLT : A/D Conversion Result This field contains conversion result of ADC. For Medium density, RSLT[15:12] always read as 0. For Low density, if DMOF bit (ADCR[31]) set to 0, 12 bits ADC conversion result with unsigned format will be filled in RSLT[11:0] and zero will be filled in RSLT[15:12]. If DMOF bit (ADCR[31]) set to 1, 12 bits ADC conversion result with 2's complement format will be filled in RSLT[11:0] and signed bits will be filled in RSLT[15:12].
bits : 0 - 15 (16 bit)
access : read-only

OVERRUN : Over Run Flag 1 = Data in RSLT[11:0] is overwrite. 0 = Data in RSLT[11:0] is recent conversion result. If converted data in RSLT[11:0] has not been read before new conversion result is loaded to this register, OVERRUN is set to 1 and previous conversion result is gone. It will be cleared by hardware after ADDR register is read.
bits : 16 - 16 (1 bit)
access : read-only

VALID : Valid Flag 1 = Data in RSLT[11:0] bits is valid. 0 = Data in RSLT[11:0] bits is not valid. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.
bits : 17 - 17 (1 bit)
access : read-only

RSLT : A/D Conversion Result This field contains conversion result of ADC. For Medium density, RSLT[15:12] always read as 0. For Low density, if DMOF bit (ADCR[31]) set to 0, 12 bits ADC conversion result with unsigned format will be filled in RSLT[11:0] and zero will be filled in RSLT[15:12]. If DMOF bit (ADCR[31]) set to 1, 12 bits ADC conversion result with 2's complement format will be filled in RSLT[11:0] and signed bits will be filled in RSLT[15:12].
bits : 0 - 15 (16 bit)
access : read-only

OVERRUN : Over Run Flag 1 = Data in RSLT[11:0] is overwrite. 0 = Data in RSLT[11:0] is recent conversion result. If converted data in RSLT[11:0] has not been read before new conversion result is loaded to this register, OVERRUN is set to 1 and previous conversion result is gone. It will be cleared by hardware after ADDR register is read.
bits : 16 - 16 (1 bit)
access : read-only

VALID : Valid Flag 1 = Data in RSLT[11:0] bits is valid. 0 = Data in RSLT[11:0] bits is not valid. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.
bits : 17 - 17 (1 bit)
access : read-only

RSLT : A/D Conversion Result This field contains conversion result of ADC. For Medium density, RSLT[15:12] always read as 0. For Low density, if DMOF bit (ADCR[31]) set to 0, 12 bits ADC conversion result with unsigned format will be filled in RSLT[11:0] and zero will be filled in RSLT[15:12]. If DMOF bit (ADCR[31]) set to 1, 12 bits ADC conversion result with 2's complement format will be filled in RSLT[11:0] and signed bits will be filled in RSLT[15:12].
bits : 0 - 15 (16 bit)
access : read-only

OVERRUN : Over Run Flag 1 = Data in RSLT[11:0] is overwrite. 0 = Data in RSLT[11:0] is recent conversion result. If converted data in RSLT[11:0] has not been read before new conversion result is loaded to this register, OVERRUN is set to 1 and previous conversion result is gone. It will be cleared by hardware after ADDR register is read.
bits : 16 - 16 (1 bit)
access : read-only

VALID : Valid Flag 1 = Data in RSLT[11:0] bits is valid. 0 = Data in RSLT[11:0] bits is not valid. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.
bits : 17 - 17 (1 bit)
access : read-only

RSLT : A/D Conversion Result This field contains conversion result of ADC. For Medium density, RSLT[15:12] always read as 0. For Low density, if DMOF bit (ADCR[31]) set to 0, 12 bits ADC conversion result with unsigned format will be filled in RSLT[11:0] and zero will be filled in RSLT[15:12]. If DMOF bit (ADCR[31]) set to 1, 12 bits ADC conversion result with 2's complement format will be filled in RSLT[11:0] and signed bits will be filled in RSLT[15:12].
bits : 0 - 15 (16 bit)
access : read-only

OVERRUN : Over Run Flag 1 = Data in RSLT[11:0] is overwrite. 0 = Data in RSLT[11:0] is recent conversion result. If converted data in RSLT[11:0] has not been read before new conversion result is loaded to this register, OVERRUN is set to 1 and previous conversion result is gone. It will be cleared by hardware after ADDR register is read.
bits : 16 - 16 (1 bit)
access : read-only

VALID : Valid Flag 1 = Data in RSLT[11:0] bits is valid. 0 = Data in RSLT[11:0] bits is not valid. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.
bits : 17 - 17 (1 bit)
access : read-only

ADEN : A/D Converter Enable 1 = Enable 0 = Disable Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit for saving power consumption.
bits : 0 - 0 (1 bit)
access : read-write

ADIE : A/D Interrupt Enable 1 = Enable A/D interrupt function 0 = Disable A/D interrupt function A/D conversion end interrupt request is generated if ADIE bit is set to 1.
bits : 1 - 1 (1 bit)
access : read-write

ADMD : A/D Converter Operation Mode 00 = Single conversion 01 = Reserved 10 = Single-cycle scan 11 = Continuous scan When changing the operation mode, software should disable ADST bit firstly.
bits : 2 - 3 (2 bit)
access : read-write

TRGS : Hardware Trigger Source 00 = A/D conversion is started by external STADC pin. Others = Reserved Software should disable TRGE and ADST before change TRGS. In hardware trigger mode, the ADST bit is set by the external trigger from STADC.
bits : 4 - 5 (2 bit)
access : read-write

TRGCOND : External Trigger Condition These two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state for edge trigger. 00 = Low level 01 = High level 10 = Falling edge 11 = Positive edge
bits : 6 - 7 (2 bit)
access : read-write

TRGEN : External Trigger Enable Enable or disable triggering of A/D conversion by external STADC pin. 1= Enable 0= Disable
bits : 8 - 8 (1 bit)
access : read-write

PTEN : PDMA Transfer Enable 1 = Enable PDMA data transfer in ADDR 0~7 0 = Disable PDMA data transfer. When A/D conversion is completed, the converted data is loaded into ADDR 0~7, software can enable this bit to generate a PDMA data transfer request. When PTEN=1, software must set ADIE=0 to disable interrupt.
bits : 9 - 9 (1 bit)
access : read-write

DIFFEN : A/D Differential Input Mode Enable 1 = A/D is in differential analog input mode 0 = A/D is in single-end analog input mode Differential input voltage (Vdiff) = Vplus - Vminus The Vplus of differential input paired channel 0 is from ADC0 pin; Vminus is from ADC1 pin. The Vplus of differential input paired channel 1 is from ADC2 pin; Vminus is from ADC3 pin. The Vplus of differential input paired channel 2 is from ADC4 pin; Vminus is from ADC5 pin. The Vplus of differential input paired channel 3 is from ADC6 pin; Vminus is from ADC7 pin. In differential input mode, only one of the two corresponding channels needs to be enabled in ADCHER. The conversion result will be placed to the corresponding data register of the enabled channel. If both channels of a differential input paired channel are enabled, the ADC will convert it twice in scan mode. And then write the conversion result to the two corresponding data registers.
bits : 10 - 10 (1 bit)
access : read-write

ADST : A/D Conversion Start 1 = Conversion start. 0 = Conversion stopped and A/D converter enter idle state. ADST bit can be controlled by two sources: software write and external pin STADC. ADST is cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode on specified channels. In continuous scan mode, A/D conversion is continuously performed sequentially until this bit is cleared to 0 or chip reset.
bits : 11 - 11 (1 bit)
access : read-write

DMOF : A/D differential input Mode Output Format This bit is only supported in Low Density. 1 = A/D Conversion result will be filled in RSLT at ADDRx registers with 2'complement format. 0 = A/D Conversion result will be filled in RSLT at ADDRx registers with unsigned format.
bits : 31 - 31 (1 bit)
access : read-write

CHEN0 : Analog Input Channel 0 Enable 1 = Enable 0 = Disable Channel 0 is the default enable channel if CHEN0~7 are set as 0s.
bits : 0 - 0 (1 bit)
access : read-write

CHEN1 : Analog Input Channel 1 Enable 1 = Enable 0 = Disable
bits : 1 - 1 (1 bit)
access : read-write

CHEN2 : Analog Input Channel 2 Enable 1 = Enable 0 = Disable
bits : 2 - 2 (1 bit)
access : read-write

CHEN3 : Analog Input Channel 3 Enable 1 = Enable 0 = Disable
bits : 3 - 3 (1 bit)
access : read-write

CHEN4 : Analog Input Channel 4 Enable 1 = Enable 0 = Disable
bits : 4 - 4 (1 bit)
access : read-write

CHEN5 : Analog Input Channel 5 Enable 1 = Enable 0 = Disable
bits : 5 - 5 (1 bit)
access : read-write

CHEN6 : Analog Input Channel 6 Enable 1 = Enable 0 = Disable
bits : 6 - 6 (1 bit)
access : read-write

CHEN7 : Analog Input Channel 7 Enable 1 = Enable 0 = Disable
bits : 7 - 7 (1 bit)
access : read-write

PRESEL : Analog Input Channel 7 select 00: External analog input 01: Internal bandgap voltage 10: Internal temperature sensor 11: Reserved
bits : 8 - 9 (2 bit)
access : read-write

CMPEN : Compare Enable 1 = Enable compare. 0 = Disable compare. Set this bit to 1 to enable ADC controller to compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADDR register.
bits : 0 - 0 (1 bit)
access : read-write

CMPIE : Compare Interrupt Enable 1 = Enable 0 = Disable If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF0 bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated.
bits : 1 - 1 (1 bit)
access : read-write

CMPCOND : Compare Condition 1 = Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (ADCMPR0[27:16]), the internal match counter will increase one. 0 = Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD (ADCMPR0[27:16]), the internal match counter will increase one. When the internal counter reaches the value to (CMPMATCNT +1), the CMPF0 bit will be set.
bits : 2 - 2 (1 bit)
access : read-write

CMPCH : Compare Channel Selection 000 = Channel 0 conversion result is selected to be compared. 001 = Channel 1 conversion result is selected to be compared. 010 = Channel 2 conversion result is selected to be compared. 011 = Channel 3 conversion result is selected to be compared. 100 = Channel 4 conversion result is selected to be compared. 101 = Channel 5 conversion result is selected to be compared. 110 = Channel 6 conversion result is selected to be compared. 111 = Channel 7 conversion result is selected to be compared.
bits : 3 - 5 (3 bit)
access : read-write

CMPMATCNT : Compare Match Count When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPF0 bit will be set.
bits : 8 - 11 (4 bit)
access : read-write

CMPD : Comparison Data The 12 bits data is used to compare with conversion result of specified channel. Software can use it to monitor the external analog input pin voltage transition in scan mode without imposing a load on software. The following description is only supported in Low Density. When DMOF bit is set to 0, ADC comparator compares CMPD with conversion result with unsigned format. CMPD should be filled in unsigned format. When DMOF bit is set to 1, ADC comparator compares CMPD with conversion result with 2's complement format. CMPD should be filled in 2's complement format.
bits : 16 - 27 (12 bit)
access : read-write

CMPEN : Compare Enable 1 = Enable compare. 0 = Disable compare. Set this bit to 1 to enable ADC controller to compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADDR register.
bits : 0 - 0 (1 bit)
access : read-write

CMPIE : Compare Interrupt Enable 1 = Enable 0 = Disable If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF1 bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated.
bits : 1 - 1 (1 bit)
access : read-write

CMPCOND : Compare Condition 1 = Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (ADCMPR1[27:16]), the internal match counter will increase one. 0 = Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD (ADCMPR1[27:16]), the internal match counter will increase one. When the internal counter reaches the value to (CMPMATCNT +1), the CMPF1 bit will be set.
bits : 2 - 2 (1 bit)
access : read-write

CMPCH : Compare Channel Selection 000 = Channel 0 conversion result is selected to be compared. 001 = Channel 1 conversion result is selected to be compared. 010 = Channel 2 conversion result is selected to be compared. 011 = Channel 3 conversion result is selected to be compared. 100 = Channel 4 conversion result is selected to be compared. 101 = Channel 5 conversion result is selected to be compared. 110 = Channel 6 conversion result is selected to be compared. 111 = Channel 7 conversion result is selected to be compared.
bits : 3 - 5 (3 bit)
access : read-write

CMPMATCNT : Compare Match Count When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPF1 bit will be set.
bits : 8 - 11 (4 bit)
access : read-write

CMPD : Comparison Data The 12 bits data is used to compare with conversion result of specified channel. Software can use it to monitor the external analog input pin voltage transition in scan mode without imposing a load on software. The following description is only supported in Low Density. When DMOF bit is set to 0, ADC comparator compares CMPD with conversion result with unsigned format. CMPD should be filled in unsigned format. When DMOF bit is set to 1, ADC comparator compares CMPD with conversion result with 2's complement format. CMPD should be filled in 2's complement format.
bits : 16 - 27 (12 bit)
access : read-write

ADF : A/D Conversion End Flag A status flag that indicates the end of A/D conversion. ADF is set to 1 at these two conditions: When A/D conversion ends in single mode When A/D conversion ends on all specified channels in scan mode. This flag can be cleared by writing 1 to itself.
bits : 0 - 0 (1 bit)
access : read-write

CMPF0 : Compare Flag When the selected channel A/D conversion result meets the setting conditions of ADCMPR0 then this bit will be set to 1. And it can be cleared by writing 1 to itself. 1 = Conversion result in ADDR meets ADCMPR0 setting 0 = Conversion result in ADDR does not meet ADCMPR0 setting
bits : 1 - 1 (1 bit)
access : read-write

CMPF1 : Compare Flag When the selected channel A/D conversion result meets the setting conditions of ADCMPR1 then this bit will be set to 1. And it can be cleared by writing 1 to itself. 1 = Conversion result in ADDR meets ADCMPR1 setting 0 = Conversion result in ADDR does not meet ADCMPR1 setting
bits : 2 - 2 (1 bit)
access : read-write

BUSY : BUSY/IDLE 1 = A/D converter is busy at conversion. 0 = A/D converter is in idle state. This bit is mirror of as ADST bit in ADCR. It is read only.
bits : 3 - 3 (1 bit)
access : read-only

CHANNEL : Current Conversion Channel This filed reflects current conversion channel when BUSY=1. When BUSY=0, it shows the next channel will be converted. It is read only.
bits : 4 - 6 (3 bit)
access : read-only

VALID : Data Valid flag It is a mirror of VALID bit in ADDRx It is read only.
bits : 8 - 15 (8 bit)
access : read-only

OVERRUN : Over Run flag It is a mirror of OVERRUN bit in ADDRx It is read only.
bits : 16 - 23 (8 bit)
access : read-only

CALEN : Self Calibration Enable 1 = Enable self calibration 0 = Disable self calibration Software can set this bit to 1 enables A/D converter to do self calibration function. It needs 127 ADC clocks to complete calibration. This bit must be kept at 1 after CALDONE asserted. Clearing this bit will disable self calibration function.
bits : 0 - 0 (1 bit)
access : read-write

CALDONE : Calibration is Done 1 = A/D converter self calibration is done 0 = A/D converter has not been calibrated or calibration is in progress if CALEN bit is set. When 0 is written to CALEN bit, CALDONE bit is cleared by hardware immediately. It is a read only bit.
bits : 1 - 1 (1 bit)
access : read-only

RSLT : A/D Conversion Result This field contains conversion result of ADC. For Medium density, RSLT[15:12] always read as 0. For Low density, if DMOF bit (ADCR[31]) set to 0, 12 bits ADC conversion result with unsigned format will be filled in RSLT[11:0] and zero will be filled in RSLT[15:12]. If DMOF bit (ADCR[31]) set to 1, 12 bits ADC conversion result with 2's complement format will be filled in RSLT[11:0] and signed bits will be filled in RSLT[15:12].
bits : 0 - 15 (16 bit)
access : read-only

OVERRUN : Over Run Flag 1 = Data in RSLT[11:0] is overwrite. 0 = Data in RSLT[11:0] is recent conversion result. If converted data in RSLT[11:0] has not been read before new conversion result is loaded to this register, OVERRUN is set to 1 and previous conversion result is gone. It will be cleared by hardware after ADDR register is read.
bits : 16 - 16 (1 bit)
access : read-only

VALID : Valid Flag 1 = Data in RSLT[11:0] bits is valid. 0 = Data in RSLT[11:0] bits is not valid. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.
bits : 17 - 17 (1 bit)
access : read-only

AD_PDMA : ADC PDMA current transfer data register When PDMA transferring, read this register can monitor current PDMA transfer data. This is a read only register.
bits : 0 - 11 (12 bit)
access : read-only

RSLT : A/D Conversion Result This field contains conversion result of ADC. For Medium density, RSLT[15:12] always read as 0. For Low density, if DMOF bit (ADCR[31]) set to 0, 12 bits ADC conversion result with unsigned format will be filled in RSLT[11:0] and zero will be filled in RSLT[15:12]. If DMOF bit (ADCR[31]) set to 1, 12 bits ADC conversion result with 2's complement format will be filled in RSLT[11:0] and signed bits will be filled in RSLT[15:12].
bits : 0 - 15 (16 bit)
access : read-only

OVERRUN : Over Run Flag 1 = Data in RSLT[11:0] is overwrite. 0 = Data in RSLT[11:0] is recent conversion result. If converted data in RSLT[11:0] has not been read before new conversion result is loaded to this register, OVERRUN is set to 1 and previous conversion result is gone. It will be cleared by hardware after ADDR register is read.
bits : 16 - 16 (1 bit)
access : read-only

VALID : Valid Flag 1 = Data in RSLT[11:0] bits is valid. 0 = Data in RSLT[11:0] bits is not valid. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.
bits : 17 - 17 (1 bit)
access : read-only

RSLT : A/D Conversion Result This field contains conversion result of ADC. For Medium density, RSLT[15:12] always read as 0. For Low density, if DMOF bit (ADCR[31]) set to 0, 12 bits ADC conversion result with unsigned format will be filled in RSLT[11:0] and zero will be filled in RSLT[15:12]. If DMOF bit (ADCR[31]) set to 1, 12 bits ADC conversion result with 2's complement format will be filled in RSLT[11:0] and signed bits will be filled in RSLT[15:12].
bits : 0 - 15 (16 bit)
access : read-only

OVERRUN : Over Run Flag 1 = Data in RSLT[11:0] is overwrite. 0 = Data in RSLT[11:0] is recent conversion result. If converted data in RSLT[11:0] has not been read before new conversion result is loaded to this register, OVERRUN is set to 1 and previous conversion result is gone. It will be cleared by hardware after ADDR register is read.
bits : 16 - 16 (1 bit)
access : read-only

VALID : Valid Flag 1 = Data in RSLT[11:0] bits is valid. 0 = Data in RSLT[11:0] bits is not valid. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.
bits : 17 - 17 (1 bit)
access : read-only