PWRCON

CLKSEL0

CLKSEL1

CLKDIV

CLKSEL2

PLLCON

FRQDIV

AHBCLK

APBCLK

CLKSTATUS

XTL12M_EN : External 4~24 MHz Crystal Enable (write-protection bit) The bit default value is set by flash controller user configuration register config0 [26:24]. When the default clock source is from external 4~24 MHz crystal, this bit is set to 1 automatically 1 = Enable external 4~24 MHz crystal 0 = Disable external 4~24 MHz crystal
bits : 0 - 0 (1 bit)
access : read-write

XTL32K_EN : External 32.768 KHz Crystal Enable (write-protection bit) 1 = Enable external 32.768 kHz Crystal (Normal operation) 0 = Disable external 32.768 kHz Crystal
bits : 1 - 1 (1 bit)
access : read-write

OSC22M_EN : Internal 22.1184MHz Oscillator Enable (write-protection bit) 1 = Enable 22.1184MHz Oscillation 0 = Disable 22.1184MHz Oscillation
bits : 2 - 2 (1 bit)
access : read-write

OSC10K_EN : Internal 10KHz Oscillator Enable (write-protection bit) 1 = Enable 10KHz Oscillation 0 = Disable 10KHz Oscillation
bits : 3 - 3 (1 bit)
access : read-write

PD_WU_DLY : Enable the wake up delay counter (write-protection bit) When the chip wakes up from power down mode, the clock control will delay certain clock cycles to wait system clock stable. The delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz crystal, and 256 clock cycles when chip work at internal 22.1184 MHz oscillator. 1 = Enable clock cycles delay 0 = Disable clock cycles delay
bits : 4 - 4 (1 bit)
access : read-write

PD_WU_INT_EN : Power down mode wake up Interrupt enable (write-protection bit) 0 = Disable 1 = Enable. The interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.
bits : 5 - 5 (1 bit)
access : read-write

PD_WU_STS : Power down mode wake up interrupt status Set by "power down wake up", it indicates that resume from power down mode The flag is set if the GPIO, USB, UART, WDT, CAN, ACMP, BOD or RTC wakeup occurred Write 1 to clear the bit Note: This bit is working only if PD_WU_INT_EN (PWRCON[5]) set to 1.
bits : 6 - 6 (1 bit)
access : read-write

PWR_DOWN_EN : System power down enable bit (write-protection bit) When CPU sets this bit "1" the chip power down mode is enabled, and chip power-down behavior will depends on the PD_WAIT_CPU bit. (a) If the PD_WAIT_CPU is "0", then the chip enters power down mode immediately after the PWR_DOWN_EN bit set. (b) if the PD_WAIT_CPU is "1", then the chip keeps active till the CPU sleep mode is also active and then the chip enters power down mode. When chip wakes up from power down mode, this bit is auto cleared. Users need to set this bit again for next power down. When in power down mode, external 4~24 MHz crystal and the internal 22.1184 MHz oscillator will be disabled in this mode, but the external 32 kHz crystal and internal 10 kHz oscillator are not controlled by power down mode. When in power down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by power down mode, if the peripheral clock source is from 32 kHz crystal or the 10 kHz oscillator. 1 = Chip enter the power down mode instant or wait CPU sleep command WFI. 0 = Chip operate in normal mode or CPU in idle mode (sleep mode) because of WFI command.
bits : 7 - 7 (1 bit)
access : read-write

PD_WAIT_CPU : This bit control the power down entry condition (write-protection bit) 1 = Chip enter power down mode when the both PWR_DOWN_EN bit is set to 1 and CPU run WFI instruction. 0 = Chip entry power down mode when the PWR_DOWN_EN bit is set to 1.
bits : 8 - 8 (1 bit)
access : read-write

HCLK_S : HCLK clock source select (write-protection bits) Note: 1. Before clock switching, the related clock sources (both pre-select and new-select) must be turn on 2. The 3-bit default value is reloaded from the value of CFOSC (Config0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b. 3. These bits are protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100. 000 = Clock source from external 4~24 MHz crystal clock 001 = Clock source from external 32.768 kHz crystal clock 010 = Clock source from PLL clock 011 = Clock source from internal 10 kHz oscillator clock 111 = Clock source from internal 22.1184 MHz oscillator clock Others = reserved
bits : 0 - 2 (3 bit)
access : read-write

STCLK_S : Cortex_M0 SysTick clock source select (write-protection bits) If SYST_CSR[2]=0, SysTick uses listed clock source below These bits are protected bit. It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100. 000 = clock source from 4~24 MHz crystal clock 001 = Clock source from external 32.768 kHz crystal clock 010 = clock source from 12MHz crystal clock / 2 011 = clock source from HCLK / 2 1xx = Clock source from internal 22.1184 MHz oscillator clock / 2
bits : 3 - 5 (3 bit)
access : read-write

WDT_S : Watchdog Timer clock source select (write-protection bits) These bits are protected bit, program this need to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100. 00 = Clock source from external 4~24 MHz crystal clock. 01 = Reserved 10 = Clock source from HCLK/2048 clock. 11 = Clock source from internal 10 kHz oscillator clock.
bits : 0 - 1 (2 bit)
access : read-write

ADC_S : ADC clock source select 00 = Clock source from external 4~24 MHz crystal clock. 01 = clock source from PLL clock 1x = Clock source from internal 22.1184 MHz oscillator clock.
bits : 2 - 3 (2 bit)
access : read-write

TMR0_S : TIMER0 clock source select. 000 = Clock source from external 4~24 MHz crystal clock. 001 = Clock source from external 32.768 kHz crystal clock. 010 = Clock source from HCLK. 011 = Clock source from external trigger. 1xx = Clock source from internal 22.1184 MHz oscillator clock.
bits : 8 - 10 (3 bit)
access : read-write

TMR1_S : TIMER1 clock source select. 000 = Clock source from external 4~24 MHz crystal clock. 001 = Clock source from external 32.768 kHz crystal clock. 010 = Clock source from HCLK. 011 = Clock source from external trigger. 1xx = Clock source from internal 22.1184 MHz oscillator clock.
bits : 12 - 14 (3 bit)
access : read-write

TMR2_S : TIMER2 clock source select. 000 = Clock source from external 4~24 MHz crystal clock. 001 = Clock source from external 32.768 kHz crystal clock. 010 = Clock source from HCLK. 011 = Clock source from external trigger. 1xx = Clock source from internal 22.1184 MHz oscillator clock.
bits : 16 - 18 (3 bit)
access : read-write

TMR3_S : TIMER3 clock source select. 000 = Clock source from external 4~24 MHz crystal clock. 001 = Clock source from external 32.768 kHz crystal clock. 010 = Clock source from HCLK. 011 = Clock source from external trigger. 1xx = Clock source from internal 22.1184 MHz oscillator clock.
bits : 20 - 22 (3 bit)
access : read-write

UART_S : UART clock source select. 00 = Clock source from external 4~24 MHz crystal clock. 01 = Clock source from PLL clock. 1x = Clock source from internal 22.1184 MHz oscillator clock.
bits : 24 - 25 (2 bit)
access : read-write

CAN_S : CAN clock source select 00 = Clock source from external 4~24 MHz crystal clock. 01 = Clock source from PLL clock. 1x = Clock source from internal 22.1184 MHz oscillator clock.
bits : 26 - 27 (2 bit)
access : read-write

PWM01_S : PWM0 and PWM1 clock source select PWM0 and PWM1 uses the same Engine clock source, both of them use the same prescaler. 00 = Clock source from external 4~24 MHz crystal clock. 01 = Clock source from external 32.768 kHz crystal clock. 10 = Clock source from HCLK. 11 = Clock source from internal 22.1184 MHz oscillator clock.
bits : 28 - 29 (2 bit)
access : read-write

PWM23_S : PWM2 and PWM3 clock source select PWM2 and PWM3 uses the same Engine clock source, both of them use the same prescaler. 00 = Clock source from external 4~24 MHz crystal clock. 01 = Clock source from external 32.768 kHz crystal clock. 10 = Clock source from HCLK. 11 = Clock source from internal 22.1184 MHz oscillator clock.
bits : 30 - 31 (2 bit)
access : read-write

HCLK_N : HCLK clock divide number from HCLK clock source The HCLK clock frequency = (HCLK clock source frequency) / (HCLK_N + 1)
bits : 0 - 3 (4 bit)
access : read-write

USB_N : USB clock divide number from PLL clock The USB clock frequency = (PLL frequency ) / (USB_N + 1)
bits : 4 - 7 (4 bit)
access : read-write

UART_N : UART clock divide number from UART clock source The UART clock frequency = (UART clock source frequency ) / (UART_N + 1)
bits : 8 - 11 (4 bit)
access : read-write

CAN_N_L : CAN clock divide number from CAN clock source The CAN clock frequency = (CAN clock source frequency ) / (CAN_N + 1) Which CAN_N = 16 * CAN_N_H + CAN_N_L
bits : 12 - 15 (4 bit)
access : read-write

ADC_N : ADC clock divide number from ADC clock source The ADC clock frequency = (ADC engine clock source frequency ) / (ADC_N + 1)
bits : 16 - 23 (8 bit)
access : read-write

CAN_N_H : CAN clock divide number from CAN clock source (Low Density Only) The CAN clock frequency = (CAN clock source frequency ) / (CAN_N + 1) Which CAN_N = 16 * CAN_N_H + CAN_N_L
bits : 24 - 29 (6 bit)
access : read-write

I2S_S : I2S clock source select. 00 = Clock source from external 4~24 MHz crystal clock. 01 = Clock source from PLL clock. 10 = Clock source from HCLK. 11 = Clock source from internal 22.1184 MHz oscillator clock.
bits : 0 - 1 (2 bit)
access : read-write

FRQDIV_S : Clock Divider Clock Source Select. 00 = Clock source from external 4~24 MHz crystal clock. 01 = Clock source from external 32.768 kHz crystal clock. 10 = Clock source from HCLK. 11 = Clock source from internal 22.1184 MHz oscillator clock.
bits : 2 - 3 (2 bit)
access : read-write

PWM45_S : PWM4 and PWM5 Clock Source Select.(Medium Density Only) PWM4 and PWM5 used the same Engine clock source, both of them use the same prescaler. 00 = Clock source from external 4~24 MHz crystal clock. 01 = Clock source from external 32.768 kHz crystal clock. 10 = Clock source from HCLK. 11 = Clock source from internal 22.1184 MHz oscillator clock.
bits : 4 - 5 (2 bit)
access : read-write

PWM67_S : PWM6 and PWM7 Clock Source Select.(Medium Density Only) PWM6 and PWM7 used the same Engine clock source, both of them use the same prescaler. 00 = Clock source from external 4~24 MHz crystal clock. 01 = Clock source from external 32.768 kHz crystal clock. 10 = Clock source from HCLK. 11 = Clock source from internal 22.1184 MHz oscillator clock.
bits : 6 - 7 (2 bit)
access : read-write

FB_DV : PLL Feedback Divider Control Pins Refer to the formulas below the table. FOUT = FIN x NF/NR x 1/NO Constrain: 1. 3.2MHz < FIN < 150MHz 2. 800KHz < FIN/(2xNR) < 8MHz 3. 100MHz < FCO = FINxNF/NR < 200MHz , 120M < FCO is preferred. Symbol Description FOUT Output Clock Frequency FIN Input (Reference) Clock Frequency NR Input Divider (IN_DV + 2) NF Feedback Divider (FB_DV + 2) NO OUT_DV = "00":NO = 1 OUT_DV = "01":NO = 2 OUT_DV = "10":NO = 2 OUT_DV = "11":NO = 4
bits : 0 - 8 (9 bit)
access : read-write

IN_DV : PLL Input Divider Control Pins Refer to the formulas below the table. (Table is the same as FB_DV).
bits : 9 - 13 (5 bit)
access : read-write

OUT_DV : PLL Output Divider Control Pins Refer to the formulas below the table. (Table is the same as FB_DV).
bits : 14 - 15 (2 bit)
access : read-write

PD : Power Down Mode. If set the IDLE bit "1" in PWRCON register, the PLL will enter power down mode too 0 = PLL is in normal mode 1 = PLL is in power-down mode(default)
bits : 16 - 16 (1 bit)
access : read-write

BP : PLL Bypass Control 0 = PLL is in normal mode (default) 1 = PLL clock output is same as clock input (XTALin)
bits : 17 - 17 (1 bit)
access : read-write

OE : PLL OE (FOUT enable) pin Control 0 = PLL FOUT enable 1 = PLL FOUT is fixed low
bits : 18 - 18 (1 bit)
access : read-write

PLL_SRC : PLL Source Clock Select 1 = PLL source clock from 22.1184 MHz oscillator 0 = PLL source clock from 4~24 MHz crystal
bits : 19 - 19 (1 bit)
access : read-write

FSEL : Divider Output Frequency Selection Bits The formula of output frequency is Fout = Fin/(2^(N+1)), Fin is the input clock frequency. Fout is the frequency of divider output clock. N is the 4-bit value of FSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write

DIVIDER_EN : Frequency Divider Enable Bit 0 = Disable Frequency Divider 1 = Enable Frequency Divider
bits : 4 - 4 (1 bit)
access : read-write

PDMA_EN : PDMA Controller Clock Enable Control. 1 = Enable the PDMA engine clock. 0 = Disable the PDMA engine clock.
bits : 1 - 1 (1 bit)
access : read-write

ISP_EN : Flash ISP Controller Clock Enable Control. 1 = Enable the Flash ISP engine clock. 0 = Disable the Flash ISP engine clock.
bits : 2 - 2 (1 bit)
access : read-write

EBI_EN : EBI Controller Clock Enable Control (Low Density Only) 1 = Enable the EBI engine clock. 0 = Disable the EBI engine clock.
bits : 3 - 3 (1 bit)
access : read-write

WDT_EN : Watch Dog Timer Clock Enable (write-protection bit) This bit is the protected bit. It means programming this needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100. The bit default value is set by flash controller. User configuration register config0 bit[31] 1 = Enable Watchdog Timer Clock 0 = Disable Watchdog Timer Clock
bits : 0 - 0 (1 bit)
access : read-write

RTC_EN : Real-Time-Clock APB interface Clock Enable. This bit is used to control the RTC APB clock only, The RTC engine clock source is from the 32.768KHz crystal. 1 = Enable RTC Clock 0 = Disable RTC Clock
bits : 1 - 1 (1 bit)
access : read-write

TMR0_EN : Timer0 Clock Enable 1 = Enable Timer0 Clock 0 = Disable Timer0 Clock
bits : 2 - 2 (1 bit)
access : read-write

TMR1_EN : Timer1 Clock Enable 1 = Enable Timer1 Clock 0 = Disable Timer1 Clock
bits : 3 - 3 (1 bit)
access : read-write

TMR2_EN : Timer2 Clock Enable 1 = Enable Timer2 Clock 0 = Disable Timer2 Clock
bits : 4 - 4 (1 bit)
access : read-write

TMR3_EN : Timer3 Clock Enable 1 = Enable Timer3 Clock 0 = Disable Timer3 Clock
bits : 5 - 5 (1 bit)
access : read-write

FDIV_EN : Frequency Divider Output Clock Enable 1 = Enable FDIV Clock 0 = Disable FDIV Clock
bits : 6 - 6 (1 bit)
access : read-write

I2C0_EN : I2C0 Clock Enable . 1 = Enable I2C0 Clock 0 = Disable I2C0 Clock
bits : 8 - 8 (1 bit)
access : read-write

I2C1_EN : I2C1 Clock Enable. 1 = Enable I2C1 Clock 0 = Disable I2C1 Clock
bits : 9 - 9 (1 bit)
access : read-write

SPI0_EN : SPI0 Clock Enable. 1 = Enable SPI0 Clock 0 = Disable SPI0 Clock
bits : 12 - 12 (1 bit)
access : read-write

SPI1_EN : SPI1 Clock Enable. 1 = Enable SPI1 Clock 0 = Disable SPI1 Clock
bits : 13 - 13 (1 bit)
access : read-write

SPI2_EN : SPI2 Clock Enable. (Medium Density Only) 1 = Enable SPI2 Clock 0 = Disable SPI2 Clock
bits : 14 - 14 (1 bit)
access : read-write

SPI3_EN : SPI3 Clock Enable. (Medium Density Only) 1 = Enable SPI3 Clock 0 = Disable SPI3 Clock
bits : 15 - 15 (1 bit)
access : read-write

UART0_EN : UART0 Clock Enable. 1 = Enable UART0 clock 0 = Disable UART0 clock
bits : 16 - 16 (1 bit)
access : read-write

UART1_EN : UART1 Clock Enable. 1 = Enable UART1 clock 0 = Disable UART1 clock
bits : 17 - 17 (1 bit)
access : read-write

UART2_EN : UART2 Clock Enable.(Medium Density Only) 1 = Enable UART2 clock 0 = Disable UART2 clock
bits : 18 - 18 (1 bit)
access : read-write

PWM01_EN : PWM_01 Clock Enable. 1 = Enable PWM01 clock 0 = Disable PWM01 clock
bits : 20 - 20 (1 bit)
access : read-write

PWM23_EN : PWM_23 Clock Enable. 1 = Enable PWM23 clock 0 = Disable PWM23 clock
bits : 21 - 21 (1 bit)
access : read-write

PWM45_EN : PWM_45 Clock Enable.(Medium Density Only) 1 = Enable PWM45 clock 0 = Disable PWM45 clock
bits : 22 - 22 (1 bit)
access : read-write

PWM67_EN : PWM_67 Clock Enable.(Medium Density Only) 1 = Enable PWM67 clock 0 = Disable PWM67 clock
bits : 23 - 23 (1 bit)
access : read-write

CAN0_EN : CAN Bus Controller-0 Clock Enable 1 = Enable CAN0 clock 0 = Disable CAN0 clock
bits : 24 - 24 (1 bit)
access : read-write

USBD_EN : USB 2.0 FS Device Controller Clock Enable 1 = Enable USB clock 0 = Disable USB clock
bits : 27 - 27 (1 bit)
access : read-write

ADC_EN : Analog-Digital-Converter (ADC) Clock Enable. 1 = Enable ADC clock 0 = Disable ADC clock
bits : 28 - 28 (1 bit)
access : read-write

I2S_EN : I2S Clock Enable 1 = Enable I2S Clock 0 = Disable I2S Clock
bits : 29 - 29 (1 bit)
access : read-write

ACMP_EN : Analog Comparator Clock Enable. 1 = Enable the Analog Comparator Clock 0 = Disable the Analog Comparator Clock
bits : 30 - 30 (1 bit)
access : read-write

PS2_EN : PS2 Clock Enable. 1 = Enable PS2 clock 0 = Disable PS2 clock
bits : 31 - 31 (1 bit)
access : read-write

XTL12M_STB : XTL12M clock source stable flag 1 = XTL12M clock is stable 0 = XTL12M clock is not stable or disabled This is read only bit
bits : 0 - 0 (1 bit)
access : read-only

XTL32K_STB : XTL32K clock source stable flag 1 = XTL32K clock is stable 0 = XTL32K clock is not stable or disabled This is read only bit
bits : 1 - 1 (1 bit)
access : read-only

PLL_STB : PLL clock source stable flag 1 = PLL clock is stable 0 = PLL clock is not stable or disabled This is read only bit
bits : 2 - 2 (1 bit)
access : read-only

OSC10K_STB : OSC10K clock source stable flag 1 = OSC10K clock is stable 0 = OSC10K clock is not stable or disabled This is read only bit
bits : 3 - 3 (1 bit)
access : read-only

OSC22M_STB : OSC22M clock source stable flag 1 = OSC22M clock is stable 0 = OSC22M clock is not stable or disabled This is read only bit
bits : 4 - 4 (1 bit)
access : read-only

CLK_SW_FAIL : Clock switching fail flag 1 = Clock switching failure 0 = Clock switching success This bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 1'b0. If switch target clock is not stable, this bit will be set to 1'b1. Write 1 to clear the bit to zero
bits : 7 - 7 (1 bit)
access : read-write