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address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
External Bus Interface General Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ExtEN : EBI Enable This bit is the functional enable bit for EBI. 1: EBI function is enabled 0: EBI function is disabled
bits : 0 - 0 (1 bit)
access : read-write
ExtBW16 : EBI data width 16 bit This bit defines if the data bus is 8-bit or 16-bit. 1: EBI data width is 16 bit 0: EBI data width is 8 bit
bits : 1 - 1 (1 bit)
access : read-write
MCLKDIV : External Output Clock Divider The frequency of EBI output clock is controlled by MCLKDIV as follows table: MCLKDIV Output clock (MCLK) 000 HCLK/1 001 HCLK/2 010 HCLK/4 011 HCLK/8 100 HCLK/16 101 HCLK/32 11X default Notice: Default value of output clock is HCLK/1
bits : 8 - 10 (3 bit)
access : read-write
ExttALE : Expand Time of ALE The ALE width (tALE) to latch the address can be controlled by ExttALE. tALE = (ExttALE+1)*MCLK
bits : 16 - 18 (3 bit)
access : read-write
External Bus Interface Timing Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ExttACC : EBI Data Access Time ExttACC define data access time (tACC). tACC = (ExttACC+1)*MCLK
bits : 3 - 7 (5 bit)
access : read-write
ExttAHD : EBI Data Access Hold Time ExttAHD define data access hold time (tAHD). tAHD = (ExttAHD+1)*MCLK
bits : 8 - 10 (3 bit)
access : read-write
ExtIW2X : Idle State Cycle After Write When write action is finish, idle state is inserted and nCS return to high if ExtIW2X is not zero. Idle state cycle = (ExtIW2X)*MCLK
bits : 12 - 15 (4 bit)
access : read-write
ExtIR2R : Idle State Cycle Between Read-Read When read action is finish and next action is going to read, idle state is inserted and nCS return to high if ExtIR2R is not zero. Idle state cycle = (ExtIR2R)*MCLK
bits : 24 - 27 (4 bit)
access : read-write
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