ISPCON

ISPTRG

DFBADR

FATCON

ISPADR

ISPDAT

ISPCMD

ISPEN : ISP Enable ISP function enable bit. Set this bit to enable ISP function. 1 = Enable ISP function 0 = Disable ISP function
bits : 0 - 0 (1 bit)
access : read-write

BS : Boot Select Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in Config0 after power-on reset; It keeps the same value at other reset. 1 = boot from LDROM 0 = boot from APROM
bits : 1 - 1 (1 bit)
access : read-write

CFGUEN : Enable Config-bits Update by ISP LDROM update enable bit. 1 = Enable ISP can update config-bits. 0 = Disable ISP can update config-bits.
bits : 4 - 4 (1 bit)
access : read-write

LDUEN : LDROM Update Enable LDROM update enable bit. 1 = LDROM can be updated when the MCU runs in APROM. 0 = LDROM can not be updated
bits : 5 - 5 (1 bit)
access : read-write

ISPFF : ISP Fail Flag This bit is set by hardware when a triggered ISP meets any of the following conditions: (1) APROM writes to itself. (2) LDROM writes to itself. (3) CONFIG is erased/programmed if CFGUEN is set to 0. (4) Destination address is illegal, such as over an available range. Write 1 to clear.
bits : 6 - 6 (1 bit)
access : read-write

PT : Flash Program Time PT[2] PT[1] PT[0] Program Time (us) 0 0 0 40 0 0 1 45 0 1 0 50 0 1 1 55 1 0 0 20 1 0 1 25 1 1 0 30 1 1 1 35
bits : 8 - 10 (3 bit)
access : read-write

ET : Flash Erase Time ET[2] ET[1] ET[0] Erase Time (ms) 0 0 0 20 (default) 0 0 1 25 0 1 0 30 0 1 1 35 1 0 0 3 1 0 1 5 1 1 0 10 1 1 1 15
bits : 12 - 14 (3 bit)
access : read-write

ISPGO : ISP start trigger Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. 1 = ISP is on going 0 = ISP is operation is finished
bits : 0 - 0 (1 bit)
access : read-write

DFBADR : Data Flash Base Address This register indicates data flash start address. It is a read only register. For 128kB flash memory device, the data flash size is defined by user configuration, register content is loaded from Config1 when chip power on but for 64/32kB device, it is fixed at 0x01_f000
bits : 0 - 31 (32 bit)
access : read-only

FPSEN : Flash Power Save Enable If CPU clock is slower than 24 MHz, then s/w can enable flash power saving function. 1 = Enable flash power saving 0 = Disable flash power saving
bits : 0 - 0 (1 bit)
access : read-write

FATS : Flash Access Time Window Select These bits are used to decide flash sense amplifier active duration. FATS Access Time window (ns) 000 40 001 50 010 60 011 70 100 80 101 90 110 100 111 reserved
bits : 1 - 3 (3 bit)
access : read-write

ISPADR : ISP Address NuMicro(TM) NUC100 Series equips with a maximum 32Kx32 embedded flash, it supports word program only. ISPARD[1:0] must be kept 00b for ISP operation.
bits : 0 - 31 (32 bit)
access : read-write

ISPDAT : ISP Data Write data to this register before ISP program operation Read data from this register after ISP read operation
bits : 0 - 31 (32 bit)
access : read-write

FCTRL : ISP Command ISP command table is showed below: Operation Mode FOEN FCEN FCTRL[3:0] Read 0 0 0 0 0 0 Program 1 0 0 0 0 1 Page Erase 1 0 0 0 1 0
bits : 0 - 3 (4 bit)
access : read-write

FCEN : ISP Command ISP command table is showed below: Operation Mode FOEN FCEN FCTRL[3:0] Read 0 0 0 0 0 0 Program 1 0 0 0 0 1 Page Erase 1 0 0 0 1 0
bits : 4 - 4 (1 bit)
access : read-write

FOEN : ISP Command ISP command table is showed below: Operation Mode FOEN FCEN FCTRL[3:0] Read 0 0 0 0 0 0 Program 1 0 0 0 0 1 Page Erase 1 0 0 0 1 0
bits : 5 - 5 (1 bit)
access : read-write